1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * AD7298 SPI ADC driver
4 *
5 * Copyright 2011 Analog Devices Inc.
6 */
7
8 #include <linux/device.h>
9 #include <linux/kernel.h>
10 #include <linux/slab.h>
11 #include <linux/sysfs.h>
12 #include <linux/spi/spi.h>
13 #include <linux/regulator/consumer.h>
14 #include <linux/err.h>
15 #include <linux/delay.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/bitops.h>
19
20 #include <linux/iio/iio.h>
21 #include <linux/iio/sysfs.h>
22 #include <linux/iio/buffer.h>
23 #include <linux/iio/trigger_consumer.h>
24 #include <linux/iio/triggered_buffer.h>
25
26 #define AD7298_WRITE BIT(15) /* write to the control register */
27 #define AD7298_REPEAT BIT(14) /* repeated conversion enable */
28 #define AD7298_CH(x) BIT(13 - (x)) /* channel select */
29 #define AD7298_TSENSE BIT(5) /* temperature conversion enable */
30 #define AD7298_EXTREF BIT(2) /* external reference enable */
31 #define AD7298_TAVG BIT(1) /* temperature sensor averaging enable */
32 #define AD7298_PDD BIT(0) /* partial power down enable */
33
34 #define AD7298_MAX_CHAN 8
35 #define AD7298_INTREF_mV 2500
36
37 #define AD7298_CH_TEMP 9
38
39 struct ad7298_state {
40 struct spi_device *spi;
41 struct regulator *reg;
42 unsigned ext_ref;
43 struct spi_transfer ring_xfer[10];
44 struct spi_transfer scan_single_xfer[3];
45 struct spi_message ring_msg;
46 struct spi_message scan_single_msg;
47 /*
48 * DMA (thus cache coherency maintenance) requires the
49 * transfer buffers to live in their own cache lines.
50 */
51 __be16 rx_buf[12] __aligned(IIO_DMA_MINALIGN);
52 __be16 tx_buf[2];
53 };
54
55 #define AD7298_V_CHAN(index) \
56 { \
57 .type = IIO_VOLTAGE, \
58 .indexed = 1, \
59 .channel = index, \
60 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
61 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
62 .address = index, \
63 .scan_index = index, \
64 .scan_type = { \
65 .sign = 'u', \
66 .realbits = 12, \
67 .storagebits = 16, \
68 .endianness = IIO_BE, \
69 }, \
70 }
71
72 static const struct iio_chan_spec ad7298_channels[] = {
73 {
74 .type = IIO_TEMP,
75 .indexed = 1,
76 .channel = 0,
77 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
78 BIT(IIO_CHAN_INFO_SCALE) |
79 BIT(IIO_CHAN_INFO_OFFSET),
80 .address = AD7298_CH_TEMP,
81 .scan_index = -1,
82 .scan_type = {
83 .sign = 's',
84 .realbits = 32,
85 .storagebits = 32,
86 },
87 },
88 AD7298_V_CHAN(0),
89 AD7298_V_CHAN(1),
90 AD7298_V_CHAN(2),
91 AD7298_V_CHAN(3),
92 AD7298_V_CHAN(4),
93 AD7298_V_CHAN(5),
94 AD7298_V_CHAN(6),
95 AD7298_V_CHAN(7),
96 IIO_CHAN_SOFT_TIMESTAMP(8),
97 };
98
99 /*
100 * ad7298_update_scan_mode() setup the spi transfer buffer for the new scan mask
101 */
ad7298_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * active_scan_mask)102 static int ad7298_update_scan_mode(struct iio_dev *indio_dev,
103 const unsigned long *active_scan_mask)
104 {
105 struct ad7298_state *st = iio_priv(indio_dev);
106 int i, m;
107 unsigned short command;
108 int scan_count;
109
110 /* Now compute overall size */
111 scan_count = bitmap_weight(active_scan_mask,
112 iio_get_masklength(indio_dev));
113
114 command = AD7298_WRITE | st->ext_ref;
115
116 for (i = 0, m = AD7298_CH(0); i < AD7298_MAX_CHAN; i++, m >>= 1)
117 if (test_bit(i, active_scan_mask))
118 command |= m;
119
120 st->tx_buf[0] = cpu_to_be16(command);
121
122 /* build spi ring message */
123 st->ring_xfer[0].tx_buf = &st->tx_buf[0];
124 st->ring_xfer[0].len = 2;
125 st->ring_xfer[0].cs_change = 1;
126 st->ring_xfer[1].tx_buf = &st->tx_buf[1];
127 st->ring_xfer[1].len = 2;
128 st->ring_xfer[1].cs_change = 1;
129
130 spi_message_init(&st->ring_msg);
131 spi_message_add_tail(&st->ring_xfer[0], &st->ring_msg);
132 spi_message_add_tail(&st->ring_xfer[1], &st->ring_msg);
133
134 for (i = 0; i < scan_count; i++) {
135 st->ring_xfer[i + 2].rx_buf = &st->rx_buf[i];
136 st->ring_xfer[i + 2].len = 2;
137 st->ring_xfer[i + 2].cs_change = 1;
138 spi_message_add_tail(&st->ring_xfer[i + 2], &st->ring_msg);
139 }
140 /* make sure last transfer cs_change is not set */
141 st->ring_xfer[i + 1].cs_change = 0;
142
143 return 0;
144 }
145
ad7298_trigger_handler(int irq,void * p)146 static irqreturn_t ad7298_trigger_handler(int irq, void *p)
147 {
148 struct iio_poll_func *pf = p;
149 struct iio_dev *indio_dev = pf->indio_dev;
150 struct ad7298_state *st = iio_priv(indio_dev);
151 int b_sent;
152
153 b_sent = spi_sync(st->spi, &st->ring_msg);
154 if (b_sent)
155 goto done;
156
157 iio_push_to_buffers_with_ts(indio_dev, st->rx_buf, sizeof(st->rx_buf),
158 iio_get_time_ns(indio_dev));
159
160 done:
161 iio_trigger_notify_done(indio_dev->trig);
162
163 return IRQ_HANDLED;
164 }
165
ad7298_scan_direct(struct ad7298_state * st,unsigned ch)166 static int ad7298_scan_direct(struct ad7298_state *st, unsigned ch)
167 {
168 int ret;
169 st->tx_buf[0] = cpu_to_be16(AD7298_WRITE | st->ext_ref |
170 (AD7298_CH(0) >> ch));
171
172 ret = spi_sync(st->spi, &st->scan_single_msg);
173 if (ret)
174 return ret;
175
176 return be16_to_cpu(st->rx_buf[0]);
177 }
178
ad7298_scan_temp(struct ad7298_state * st,int * val)179 static int ad7298_scan_temp(struct ad7298_state *st, int *val)
180 {
181 int ret;
182 __be16 buf;
183
184 buf = cpu_to_be16(AD7298_WRITE | AD7298_TSENSE |
185 AD7298_TAVG | st->ext_ref);
186
187 ret = spi_write(st->spi, (u8 *)&buf, 2);
188 if (ret)
189 return ret;
190
191 buf = cpu_to_be16(0);
192
193 ret = spi_write(st->spi, (u8 *)&buf, 2);
194 if (ret)
195 return ret;
196
197 usleep_range(101, 1000); /* sleep > 100us */
198
199 ret = spi_read(st->spi, (u8 *)&buf, 2);
200 if (ret)
201 return ret;
202
203 *val = sign_extend32(be16_to_cpu(buf), 11);
204
205 return 0;
206 }
207
ad7298_get_ref_voltage(struct ad7298_state * st)208 static int ad7298_get_ref_voltage(struct ad7298_state *st)
209 {
210 int vref;
211
212 if (st->reg) {
213 vref = regulator_get_voltage(st->reg);
214 if (vref < 0)
215 return vref;
216
217 return vref / 1000;
218 } else {
219 return AD7298_INTREF_mV;
220 }
221 }
222
ad7298_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)223 static int ad7298_read_raw(struct iio_dev *indio_dev,
224 struct iio_chan_spec const *chan,
225 int *val,
226 int *val2,
227 long m)
228 {
229 int ret;
230 struct ad7298_state *st = iio_priv(indio_dev);
231
232 switch (m) {
233 case IIO_CHAN_INFO_RAW:
234 if (!iio_device_claim_direct(indio_dev))
235 return -EBUSY;
236
237 if (chan->address == AD7298_CH_TEMP)
238 ret = ad7298_scan_temp(st, val);
239 else
240 ret = ad7298_scan_direct(st, chan->address);
241
242 iio_device_release_direct(indio_dev);
243
244 if (ret < 0)
245 return ret;
246
247 if (chan->address != AD7298_CH_TEMP)
248 *val = ret & GENMASK(chan->scan_type.realbits - 1, 0);
249
250 return IIO_VAL_INT;
251 case IIO_CHAN_INFO_SCALE:
252 switch (chan->type) {
253 case IIO_VOLTAGE:
254 *val = ad7298_get_ref_voltage(st);
255 *val2 = chan->scan_type.realbits;
256 return IIO_VAL_FRACTIONAL_LOG2;
257 case IIO_TEMP:
258 *val = ad7298_get_ref_voltage(st);
259 *val2 = 10;
260 return IIO_VAL_FRACTIONAL;
261 default:
262 return -EINVAL;
263 }
264 case IIO_CHAN_INFO_OFFSET:
265 *val = 1093 - 2732500 / ad7298_get_ref_voltage(st);
266 return IIO_VAL_INT;
267 }
268 return -EINVAL;
269 }
270
271 static const struct iio_info ad7298_info = {
272 .read_raw = &ad7298_read_raw,
273 .update_scan_mode = ad7298_update_scan_mode,
274 };
275
ad7298_reg_disable(void * data)276 static void ad7298_reg_disable(void *data)
277 {
278 struct regulator *reg = data;
279
280 regulator_disable(reg);
281 }
282
ad7298_probe(struct spi_device * spi)283 static int ad7298_probe(struct spi_device *spi)
284 {
285 struct ad7298_state *st;
286 struct iio_dev *indio_dev;
287 int ret;
288
289 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
290 if (indio_dev == NULL)
291 return -ENOMEM;
292
293 st = iio_priv(indio_dev);
294
295 st->reg = devm_regulator_get_optional(&spi->dev, "vref");
296 if (!IS_ERR(st->reg)) {
297 st->ext_ref = AD7298_EXTREF;
298 } else {
299 ret = PTR_ERR(st->reg);
300 if (ret != -ENODEV)
301 return ret;
302
303 st->reg = NULL;
304 }
305
306 if (st->reg) {
307 ret = regulator_enable(st->reg);
308 if (ret)
309 return ret;
310
311 ret = devm_add_action_or_reset(&spi->dev, ad7298_reg_disable,
312 st->reg);
313 if (ret)
314 return ret;
315 }
316
317 st->spi = spi;
318
319 indio_dev->name = spi_get_device_id(spi)->name;
320 indio_dev->modes = INDIO_DIRECT_MODE;
321 indio_dev->channels = ad7298_channels;
322 indio_dev->num_channels = ARRAY_SIZE(ad7298_channels);
323 indio_dev->info = &ad7298_info;
324
325 /* Setup default message */
326
327 st->scan_single_xfer[0].tx_buf = &st->tx_buf[0];
328 st->scan_single_xfer[0].len = 2;
329 st->scan_single_xfer[0].cs_change = 1;
330 st->scan_single_xfer[1].tx_buf = &st->tx_buf[1];
331 st->scan_single_xfer[1].len = 2;
332 st->scan_single_xfer[1].cs_change = 1;
333 st->scan_single_xfer[2].rx_buf = &st->rx_buf[0];
334 st->scan_single_xfer[2].len = 2;
335
336 spi_message_init(&st->scan_single_msg);
337 spi_message_add_tail(&st->scan_single_xfer[0], &st->scan_single_msg);
338 spi_message_add_tail(&st->scan_single_xfer[1], &st->scan_single_msg);
339 spi_message_add_tail(&st->scan_single_xfer[2], &st->scan_single_msg);
340
341 ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, NULL,
342 &ad7298_trigger_handler, NULL);
343 if (ret)
344 return ret;
345
346 return devm_iio_device_register(&spi->dev, indio_dev);
347 }
348
349 static const struct acpi_device_id ad7298_acpi_ids[] = {
350 { "INT3494", 0 },
351 { }
352 };
353 MODULE_DEVICE_TABLE(acpi, ad7298_acpi_ids);
354
355 static const struct spi_device_id ad7298_id[] = {
356 { .name = "ad7298" },
357 { }
358 };
359 MODULE_DEVICE_TABLE(spi, ad7298_id);
360
361 static struct spi_driver ad7298_driver = {
362 .driver = {
363 .name = "ad7298",
364 .acpi_match_table = ad7298_acpi_ids,
365 },
366 .probe = ad7298_probe,
367 .id_table = ad7298_id,
368 };
369 module_spi_driver(ad7298_driver);
370
371 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
372 MODULE_DESCRIPTION("Analog Devices AD7298 ADC");
373 MODULE_LICENSE("GPL v2");
374