1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * AD7293 driver
4 *
5 * Copyright 2021 Analog Devices Inc.
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/bits.h>
10 #include <linux/delay.h>
11 #include <linux/device.h>
12 #include <linux/gpio/consumer.h>
13 #include <linux/iio/iio.h>
14 #include <linux/module.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/spi/spi.h>
17
18 #include <linux/unaligned.h>
19
20 #define AD7293_R1B BIT(16)
21 #define AD7293_R2B BIT(17)
22 #define AD7293_PAGE_ADDR_MSK GENMASK(15, 8)
23 #define AD7293_PAGE(x) FIELD_PREP(AD7293_PAGE_ADDR_MSK, x)
24
25 /* AD7293 Register Map Common */
26 #define AD7293_REG_NO_OP (AD7293_R1B | AD7293_PAGE(0x0) | 0x0)
27 #define AD7293_REG_PAGE_SELECT (AD7293_R1B | AD7293_PAGE(0x0) | 0x1)
28 #define AD7293_REG_CONV_CMD (AD7293_R2B | AD7293_PAGE(0x0) | 0x2)
29 #define AD7293_REG_RESULT (AD7293_R1B | AD7293_PAGE(0x0) | 0x3)
30 #define AD7293_REG_DAC_EN (AD7293_R1B | AD7293_PAGE(0x0) | 0x4)
31 #define AD7293_REG_DEVICE_ID (AD7293_R2B | AD7293_PAGE(0x0) | 0xC)
32 #define AD7293_REG_SOFT_RESET (AD7293_R2B | AD7293_PAGE(0x0) | 0xF)
33
34 /* AD7293 Register Map Page 0x0 */
35 #define AD7293_REG_VIN0 (AD7293_R2B | AD7293_PAGE(0x0) | 0x10)
36 #define AD7293_REG_VIN1 (AD7293_R2B | AD7293_PAGE(0x0) | 0x11)
37 #define AD7293_REG_VIN2 (AD7293_R2B | AD7293_PAGE(0x0) | 0x12)
38 #define AD7293_REG_VIN3 (AD7293_R2B | AD7293_PAGE(0x0) | 0x13)
39 #define AD7293_REG_TSENSE_INT (AD7293_R2B | AD7293_PAGE(0x0) | 0x20)
40 #define AD7293_REG_TSENSE_D0 (AD7293_R2B | AD7293_PAGE(0x0) | 0x21)
41 #define AD7293_REG_TSENSE_D1 (AD7293_R2B | AD7293_PAGE(0x0) | 0x22)
42 #define AD7293_REG_ISENSE_0 (AD7293_R2B | AD7293_PAGE(0x0) | 0x28)
43 #define AD7293_REG_ISENSE_1 (AD7293_R2B | AD7293_PAGE(0x0) | 0x29)
44 #define AD7293_REG_ISENSE_2 (AD7293_R2B | AD7293_PAGE(0x0) | 0x2A)
45 #define AD7293_REG_ISENSE_3 (AD7293_R2B | AD7293_PAGE(0x0) | 0x2B)
46 #define AD7293_REG_UNI_VOUT0 (AD7293_R2B | AD7293_PAGE(0x0) | 0x30)
47 #define AD7293_REG_UNI_VOUT1 (AD7293_R2B | AD7293_PAGE(0x0) | 0x31)
48 #define AD7293_REG_UNI_VOUT2 (AD7293_R2B | AD7293_PAGE(0x0) | 0x32)
49 #define AD7293_REG_UNI_VOUT3 (AD7293_R2B | AD7293_PAGE(0x0) | 0x33)
50 #define AD7293_REG_BI_VOUT0 (AD7293_R2B | AD7293_PAGE(0x0) | 0x34)
51 #define AD7293_REG_BI_VOUT1 (AD7293_R2B | AD7293_PAGE(0x0) | 0x35)
52 #define AD7293_REG_BI_VOUT2 (AD7293_R2B | AD7293_PAGE(0x0) | 0x36)
53 #define AD7293_REG_BI_VOUT3 (AD7293_R2B | AD7293_PAGE(0x0) | 0x37)
54
55 /* AD7293 Register Map Page 0x2 */
56 #define AD7293_REG_DIGITAL_OUT_EN (AD7293_R2B | AD7293_PAGE(0x2) | 0x11)
57 #define AD7293_REG_DIGITAL_INOUT_FUNC (AD7293_R2B | AD7293_PAGE(0x2) | 0x12)
58 #define AD7293_REG_DIGITAL_FUNC_POL (AD7293_R2B | AD7293_PAGE(0x2) | 0x13)
59 #define AD7293_REG_GENERAL (AD7293_R2B | AD7293_PAGE(0x2) | 0x14)
60 #define AD7293_REG_VINX_RANGE0 (AD7293_R2B | AD7293_PAGE(0x2) | 0x15)
61 #define AD7293_REG_VINX_RANGE1 (AD7293_R2B | AD7293_PAGE(0x2) | 0x16)
62 #define AD7293_REG_VINX_DIFF_SE (AD7293_R2B | AD7293_PAGE(0x2) | 0x17)
63 #define AD7293_REG_VINX_FILTER (AD7293_R2B | AD7293_PAGE(0x2) | 0x18)
64 #define AD7293_REG_BG_EN (AD7293_R2B | AD7293_PAGE(0x2) | 0x19)
65 #define AD7293_REG_CONV_DELAY (AD7293_R2B | AD7293_PAGE(0x2) | 0x1A)
66 #define AD7293_REG_TSENSE_BG_EN (AD7293_R2B | AD7293_PAGE(0x2) | 0x1B)
67 #define AD7293_REG_ISENSE_BG_EN (AD7293_R2B | AD7293_PAGE(0x2) | 0x1C)
68 #define AD7293_REG_ISENSE_GAIN (AD7293_R2B | AD7293_PAGE(0x2) | 0x1D)
69 #define AD7293_REG_DAC_SNOOZE_O (AD7293_R2B | AD7293_PAGE(0x2) | 0x1F)
70 #define AD7293_REG_DAC_SNOOZE_1 (AD7293_R2B | AD7293_PAGE(0x2) | 0x20)
71 #define AD7293_REG_RSX_MON_BG_EN (AD7293_R2B | AD7293_PAGE(0x2) | 0x23)
72 #define AD7293_REG_INTEGR_CL (AD7293_R2B | AD7293_PAGE(0x2) | 0x28)
73 #define AD7293_REG_PA_ON_CTRL (AD7293_R2B | AD7293_PAGE(0x2) | 0x29)
74 #define AD7293_REG_RAMP_TIME_0 (AD7293_R2B | AD7293_PAGE(0x2) | 0x2A)
75 #define AD7293_REG_RAMP_TIME_1 (AD7293_R2B | AD7293_PAGE(0x2) | 0x2B)
76 #define AD7293_REG_RAMP_TIME_2 (AD7293_R2B | AD7293_PAGE(0x2) | 0x2C)
77 #define AD7293_REG_RAMP_TIME_3 (AD7293_R2B | AD7293_PAGE(0x2) | 0x2D)
78 #define AD7293_REG_CL_FR_IT (AD7293_R2B | AD7293_PAGE(0x2) | 0x2E)
79 #define AD7293_REG_INTX_AVSS_AVDD (AD7293_R2B | AD7293_PAGE(0x2) | 0x2F)
80
81 /* AD7293 Register Map Page 0x3 */
82 #define AD7293_REG_VINX_SEQ (AD7293_R2B | AD7293_PAGE(0x3) | 0x10)
83 #define AD7293_REG_ISENSEX_TSENSEX_SEQ (AD7293_R2B | AD7293_PAGE(0x3) | 0x11)
84 #define AD7293_REG_RSX_MON_BI_VOUTX_SEQ (AD7293_R2B | AD7293_PAGE(0x3) | 0x12)
85
86 /* AD7293 Register Map Page 0xE */
87 #define AD7293_REG_VIN0_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x10)
88 #define AD7293_REG_VIN1_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x11)
89 #define AD7293_REG_VIN2_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x12)
90 #define AD7293_REG_VIN3_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x13)
91 #define AD7293_REG_TSENSE_INT_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x20)
92 #define AD7293_REG_TSENSE_D0_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x21)
93 #define AD7293_REG_TSENSE_D1_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x22)
94 #define AD7293_REG_ISENSE0_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x28)
95 #define AD7293_REG_ISENSE1_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x29)
96 #define AD7293_REG_ISENSE2_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x2A)
97 #define AD7293_REG_ISENSE3_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x2B)
98 #define AD7293_REG_UNI_VOUT0_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x30)
99 #define AD7293_REG_UNI_VOUT1_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x31)
100 #define AD7293_REG_UNI_VOUT2_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x32)
101 #define AD7293_REG_UNI_VOUT3_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x33)
102 #define AD7293_REG_BI_VOUT0_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x34)
103 #define AD7293_REG_BI_VOUT1_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x35)
104 #define AD7293_REG_BI_VOUT2_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x36)
105 #define AD7293_REG_BI_VOUT3_OFFSET (AD7293_R1B | AD7293_PAGE(0xE) | 0x37)
106
107 /* AD7293 Miscellaneous Definitions */
108 #define AD7293_READ BIT(7)
109 #define AD7293_TRANSF_LEN_MSK GENMASK(17, 16)
110
111 #define AD7293_REG_ADDR_MSK GENMASK(7, 0)
112 #define AD7293_REG_VOUT_OFFSET_MSK GENMASK(5, 4)
113 #define AD7293_REG_DATA_RAW_MSK GENMASK(15, 4)
114 #define AD7293_REG_VINX_RANGE_GET_CH_MSK(x, ch) (((x) >> (ch)) & 0x1)
115 #define AD7293_REG_VINX_RANGE_SET_CH_MSK(x, ch) (((x) & 0x1) << (ch))
116 #define AD7293_GENERAL_ADC_REF_MSK BIT(7)
117 #define AD7293_CHIP_ID 0x18
118
119 enum ad7293_ch_type {
120 AD7293_ADC_VINX,
121 AD7293_ADC_TSENSE,
122 AD7293_ADC_ISENSE,
123 AD7293_DAC,
124 };
125
126 enum ad7293_max_offset {
127 AD7293_TSENSE_MIN_OFFSET_CH = 4,
128 AD7293_ISENSE_MIN_OFFSET_CH = 7,
129 AD7293_VOUT_MIN_OFFSET_CH = 11,
130 AD7293_VOUT_MAX_OFFSET_CH = 18,
131 };
132
133 static const int dac_offset_table[] = {0, 1, 2};
134
135 static const int isense_gain_table[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10};
136
137 static const int adc_range_table[] = {0, 1, 2, 3};
138
139 struct ad7293_state {
140 struct spi_device *spi;
141 /* Protect against concurrent accesses to the device, page selection and data content */
142 struct mutex lock;
143 struct gpio_desc *gpio_reset;
144 bool vrefin_en;
145 u8 page_select;
146 u8 data[3] __aligned(IIO_DMA_MINALIGN);
147 };
148
ad7293_page_select(struct ad7293_state * st,unsigned int reg)149 static int ad7293_page_select(struct ad7293_state *st, unsigned int reg)
150 {
151 int ret;
152
153 if (st->page_select != FIELD_GET(AD7293_PAGE_ADDR_MSK, reg)) {
154 st->data[0] = FIELD_GET(AD7293_REG_ADDR_MSK, AD7293_REG_PAGE_SELECT);
155 st->data[1] = FIELD_GET(AD7293_PAGE_ADDR_MSK, reg);
156
157 ret = spi_write(st->spi, &st->data[0], 2);
158 if (ret)
159 return ret;
160
161 st->page_select = FIELD_GET(AD7293_PAGE_ADDR_MSK, reg);
162 }
163
164 return 0;
165 }
166
__ad7293_spi_read(struct ad7293_state * st,unsigned int reg,u16 * val)167 static int __ad7293_spi_read(struct ad7293_state *st, unsigned int reg,
168 u16 *val)
169 {
170 int ret;
171 unsigned int length;
172 struct spi_transfer t = {0};
173
174 length = FIELD_GET(AD7293_TRANSF_LEN_MSK, reg);
175
176 ret = ad7293_page_select(st, reg);
177 if (ret)
178 return ret;
179
180 st->data[0] = AD7293_READ | FIELD_GET(AD7293_REG_ADDR_MSK, reg);
181 st->data[1] = 0x0;
182 st->data[2] = 0x0;
183
184 t.tx_buf = &st->data[0];
185 t.rx_buf = &st->data[0];
186 t.len = length + 1;
187
188 ret = spi_sync_transfer(st->spi, &t, 1);
189 if (ret)
190 return ret;
191
192 if (length == 1)
193 *val = st->data[1];
194 else
195 *val = get_unaligned_be16(&st->data[1]);
196
197 return 0;
198 }
199
ad7293_spi_read(struct ad7293_state * st,unsigned int reg,u16 * val)200 static int ad7293_spi_read(struct ad7293_state *st, unsigned int reg,
201 u16 *val)
202 {
203 int ret;
204
205 mutex_lock(&st->lock);
206 ret = __ad7293_spi_read(st, reg, val);
207 mutex_unlock(&st->lock);
208
209 return ret;
210 }
211
__ad7293_spi_write(struct ad7293_state * st,unsigned int reg,u16 val)212 static int __ad7293_spi_write(struct ad7293_state *st, unsigned int reg,
213 u16 val)
214 {
215 int ret;
216 unsigned int length;
217
218 length = FIELD_GET(AD7293_TRANSF_LEN_MSK, reg);
219
220 ret = ad7293_page_select(st, reg);
221 if (ret)
222 return ret;
223
224 st->data[0] = FIELD_GET(AD7293_REG_ADDR_MSK, reg);
225
226 if (length == 1)
227 st->data[1] = val;
228 else
229 put_unaligned_be16(val, &st->data[1]);
230
231 return spi_write(st->spi, &st->data[0], length + 1);
232 }
233
ad7293_spi_write(struct ad7293_state * st,unsigned int reg,u16 val)234 static int ad7293_spi_write(struct ad7293_state *st, unsigned int reg,
235 u16 val)
236 {
237 int ret;
238
239 mutex_lock(&st->lock);
240 ret = __ad7293_spi_write(st, reg, val);
241 mutex_unlock(&st->lock);
242
243 return ret;
244 }
245
__ad7293_spi_update_bits(struct ad7293_state * st,unsigned int reg,u16 mask,u16 val)246 static int __ad7293_spi_update_bits(struct ad7293_state *st, unsigned int reg,
247 u16 mask, u16 val)
248 {
249 int ret;
250 u16 data, temp;
251
252 ret = __ad7293_spi_read(st, reg, &data);
253 if (ret)
254 return ret;
255
256 temp = (data & ~mask) | (val & mask);
257
258 return __ad7293_spi_write(st, reg, temp);
259 }
260
ad7293_spi_update_bits(struct ad7293_state * st,unsigned int reg,u16 mask,u16 val)261 static int ad7293_spi_update_bits(struct ad7293_state *st, unsigned int reg,
262 u16 mask, u16 val)
263 {
264 int ret;
265
266 mutex_lock(&st->lock);
267 ret = __ad7293_spi_update_bits(st, reg, mask, val);
268 mutex_unlock(&st->lock);
269
270 return ret;
271 }
272
ad7293_adc_get_scale(struct ad7293_state * st,unsigned int ch,u16 * range)273 static int ad7293_adc_get_scale(struct ad7293_state *st, unsigned int ch,
274 u16 *range)
275 {
276 int ret;
277 u16 data;
278
279 mutex_lock(&st->lock);
280
281 ret = __ad7293_spi_read(st, AD7293_REG_VINX_RANGE1, &data);
282 if (ret)
283 goto exit;
284
285 *range = AD7293_REG_VINX_RANGE_GET_CH_MSK(data, ch);
286
287 ret = __ad7293_spi_read(st, AD7293_REG_VINX_RANGE0, &data);
288 if (ret)
289 goto exit;
290
291 *range |= AD7293_REG_VINX_RANGE_GET_CH_MSK(data, ch) << 1;
292
293 exit:
294 mutex_unlock(&st->lock);
295
296 return ret;
297 }
298
ad7293_adc_set_scale(struct ad7293_state * st,unsigned int ch,u16 range)299 static int ad7293_adc_set_scale(struct ad7293_state *st, unsigned int ch,
300 u16 range)
301 {
302 int ret;
303 unsigned int ch_msk = BIT(ch);
304
305 mutex_lock(&st->lock);
306 ret = __ad7293_spi_update_bits(st, AD7293_REG_VINX_RANGE1, ch_msk,
307 AD7293_REG_VINX_RANGE_SET_CH_MSK(range, ch));
308 if (ret)
309 goto exit;
310
311 ret = __ad7293_spi_update_bits(st, AD7293_REG_VINX_RANGE0, ch_msk,
312 AD7293_REG_VINX_RANGE_SET_CH_MSK((range >> 1), ch));
313
314 exit:
315 mutex_unlock(&st->lock);
316
317 return ret;
318 }
319
ad7293_get_offset(struct ad7293_state * st,unsigned int ch,u16 * offset)320 static int ad7293_get_offset(struct ad7293_state *st, unsigned int ch,
321 u16 *offset)
322 {
323 if (ch < AD7293_TSENSE_MIN_OFFSET_CH)
324 return ad7293_spi_read(st, AD7293_REG_VIN0_OFFSET + ch, offset);
325 else if (ch < AD7293_ISENSE_MIN_OFFSET_CH)
326 return ad7293_spi_read(st, AD7293_REG_TSENSE_INT_OFFSET + (ch - 4), offset);
327 else if (ch < AD7293_VOUT_MIN_OFFSET_CH)
328 return ad7293_spi_read(st, AD7293_REG_ISENSE0_OFFSET + (ch - 7), offset);
329 else if (ch <= AD7293_VOUT_MAX_OFFSET_CH)
330 return ad7293_spi_read(st, AD7293_REG_UNI_VOUT0_OFFSET + (ch - 11), offset);
331
332 return -EINVAL;
333 }
334
ad7293_set_offset(struct ad7293_state * st,unsigned int ch,u16 offset)335 static int ad7293_set_offset(struct ad7293_state *st, unsigned int ch,
336 u16 offset)
337 {
338 if (ch < AD7293_TSENSE_MIN_OFFSET_CH)
339 return ad7293_spi_write(st, AD7293_REG_VIN0_OFFSET + ch,
340 offset);
341 else if (ch < AD7293_ISENSE_MIN_OFFSET_CH)
342 return ad7293_spi_write(st,
343 AD7293_REG_TSENSE_INT_OFFSET +
344 (ch - AD7293_TSENSE_MIN_OFFSET_CH),
345 offset);
346 else if (ch < AD7293_VOUT_MIN_OFFSET_CH)
347 return ad7293_spi_write(st,
348 AD7293_REG_ISENSE0_OFFSET +
349 (ch - AD7293_ISENSE_MIN_OFFSET_CH),
350 offset);
351 else if (ch <= AD7293_VOUT_MAX_OFFSET_CH)
352 return ad7293_spi_update_bits(st,
353 AD7293_REG_UNI_VOUT0_OFFSET +
354 (ch - AD7293_VOUT_MIN_OFFSET_CH),
355 AD7293_REG_VOUT_OFFSET_MSK,
356 FIELD_PREP(AD7293_REG_VOUT_OFFSET_MSK, offset));
357
358 return -EINVAL;
359 }
360
ad7293_isense_set_scale(struct ad7293_state * st,unsigned int ch,u16 gain)361 static int ad7293_isense_set_scale(struct ad7293_state *st, unsigned int ch,
362 u16 gain)
363 {
364 unsigned int ch_msk = (0xf << (4 * ch));
365
366 return ad7293_spi_update_bits(st, AD7293_REG_ISENSE_GAIN, ch_msk,
367 gain << (4 * ch));
368 }
369
ad7293_isense_get_scale(struct ad7293_state * st,unsigned int ch,u16 * gain)370 static int ad7293_isense_get_scale(struct ad7293_state *st, unsigned int ch,
371 u16 *gain)
372 {
373 int ret;
374
375 ret = ad7293_spi_read(st, AD7293_REG_ISENSE_GAIN, gain);
376 if (ret)
377 return ret;
378
379 *gain = (*gain >> (4 * ch)) & 0xf;
380
381 return ret;
382 }
383
ad7293_dac_write_raw(struct ad7293_state * st,unsigned int ch,u16 raw)384 static int ad7293_dac_write_raw(struct ad7293_state *st, unsigned int ch,
385 u16 raw)
386 {
387 int ret;
388
389 mutex_lock(&st->lock);
390
391 ret = __ad7293_spi_update_bits(st, AD7293_REG_DAC_EN, BIT(ch), BIT(ch));
392 if (ret)
393 goto exit;
394
395 ret = __ad7293_spi_write(st, AD7293_REG_UNI_VOUT0 + ch,
396 FIELD_PREP(AD7293_REG_DATA_RAW_MSK, raw));
397
398 exit:
399 mutex_unlock(&st->lock);
400
401 return ret;
402 }
403
ad7293_ch_read_raw(struct ad7293_state * st,enum ad7293_ch_type type,unsigned int ch,u16 * raw)404 static int ad7293_ch_read_raw(struct ad7293_state *st, enum ad7293_ch_type type,
405 unsigned int ch, u16 *raw)
406 {
407 int ret;
408 unsigned int reg_wr, reg_rd, data_wr;
409
410 switch (type) {
411 case AD7293_ADC_VINX:
412 reg_wr = AD7293_REG_VINX_SEQ;
413 reg_rd = AD7293_REG_VIN0 + ch;
414 data_wr = BIT(ch);
415
416 break;
417 case AD7293_ADC_TSENSE:
418 reg_wr = AD7293_REG_ISENSEX_TSENSEX_SEQ;
419 reg_rd = AD7293_REG_TSENSE_INT + ch;
420 data_wr = BIT(ch);
421
422 break;
423 case AD7293_ADC_ISENSE:
424 reg_wr = AD7293_REG_ISENSEX_TSENSEX_SEQ;
425 reg_rd = AD7293_REG_ISENSE_0 + ch;
426 data_wr = BIT(ch) << 8;
427
428 break;
429 case AD7293_DAC:
430 reg_rd = AD7293_REG_UNI_VOUT0 + ch;
431
432 break;
433 default:
434 return -EINVAL;
435 }
436
437 mutex_lock(&st->lock);
438
439 if (type != AD7293_DAC) {
440 if (type == AD7293_ADC_TSENSE) {
441 ret = __ad7293_spi_write(st, AD7293_REG_TSENSE_BG_EN,
442 BIT(ch));
443 if (ret)
444 goto exit;
445
446 usleep_range(9000, 9900);
447 } else if (type == AD7293_ADC_ISENSE) {
448 ret = __ad7293_spi_write(st, AD7293_REG_ISENSE_BG_EN,
449 BIT(ch));
450 if (ret)
451 goto exit;
452
453 usleep_range(2000, 7000);
454 }
455
456 ret = __ad7293_spi_write(st, reg_wr, data_wr);
457 if (ret)
458 goto exit;
459
460 ret = __ad7293_spi_write(st, AD7293_REG_CONV_CMD, 0x82);
461 if (ret)
462 goto exit;
463 }
464
465 ret = __ad7293_spi_read(st, reg_rd, raw);
466
467 *raw = FIELD_GET(AD7293_REG_DATA_RAW_MSK, *raw);
468
469 exit:
470 mutex_unlock(&st->lock);
471
472 return ret;
473 }
474
ad7293_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)475 static int ad7293_read_raw(struct iio_dev *indio_dev,
476 struct iio_chan_spec const *chan,
477 int *val, int *val2, long info)
478 {
479 struct ad7293_state *st = iio_priv(indio_dev);
480 int ret;
481 u16 data;
482
483 switch (info) {
484 case IIO_CHAN_INFO_RAW:
485 switch (chan->type) {
486 case IIO_VOLTAGE:
487 if (chan->output)
488 ret = ad7293_ch_read_raw(st, AD7293_DAC,
489 chan->channel, &data);
490 else
491 ret = ad7293_ch_read_raw(st, AD7293_ADC_VINX,
492 chan->channel, &data);
493
494 break;
495 case IIO_CURRENT:
496 ret = ad7293_ch_read_raw(st, AD7293_ADC_ISENSE,
497 chan->channel, &data);
498
499 break;
500 case IIO_TEMP:
501 ret = ad7293_ch_read_raw(st, AD7293_ADC_TSENSE,
502 chan->channel, &data);
503
504 break;
505 default:
506 return -EINVAL;
507 }
508
509 if (ret)
510 return ret;
511
512 *val = data;
513
514 return IIO_VAL_INT;
515 case IIO_CHAN_INFO_OFFSET:
516 switch (chan->type) {
517 case IIO_VOLTAGE:
518 if (chan->output) {
519 ret = ad7293_get_offset(st,
520 chan->channel + AD7293_VOUT_MIN_OFFSET_CH,
521 &data);
522
523 data = FIELD_GET(AD7293_REG_VOUT_OFFSET_MSK, data);
524 } else {
525 ret = ad7293_get_offset(st, chan->channel, &data);
526 }
527
528 break;
529 case IIO_CURRENT:
530 ret = ad7293_get_offset(st,
531 chan->channel + AD7293_ISENSE_MIN_OFFSET_CH,
532 &data);
533
534 break;
535 case IIO_TEMP:
536 ret = ad7293_get_offset(st,
537 chan->channel + AD7293_TSENSE_MIN_OFFSET_CH,
538 &data);
539
540 break;
541 default:
542 return -EINVAL;
543 }
544 if (ret)
545 return ret;
546
547 *val = data;
548
549 return IIO_VAL_INT;
550 case IIO_CHAN_INFO_SCALE:
551 switch (chan->type) {
552 case IIO_VOLTAGE:
553 ret = ad7293_adc_get_scale(st, chan->channel, &data);
554 if (ret)
555 return ret;
556
557 *val = data;
558
559 return IIO_VAL_INT;
560 case IIO_CURRENT:
561 ret = ad7293_isense_get_scale(st, chan->channel, &data);
562 if (ret)
563 return ret;
564
565 *val = data;
566
567 return IIO_VAL_INT;
568 case IIO_TEMP:
569 *val = 1;
570 *val2 = 8;
571
572 return IIO_VAL_FRACTIONAL;
573 default:
574 return -EINVAL;
575 }
576 default:
577 return -EINVAL;
578 }
579 }
580
ad7293_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)581 static int ad7293_write_raw(struct iio_dev *indio_dev,
582 struct iio_chan_spec const *chan,
583 int val, int val2, long info)
584 {
585 struct ad7293_state *st = iio_priv(indio_dev);
586
587 switch (info) {
588 case IIO_CHAN_INFO_RAW:
589 switch (chan->type) {
590 case IIO_VOLTAGE:
591 if (!chan->output)
592 return -EINVAL;
593
594 return ad7293_dac_write_raw(st, chan->channel, val);
595 default:
596 return -EINVAL;
597 }
598 case IIO_CHAN_INFO_OFFSET:
599 switch (chan->type) {
600 case IIO_VOLTAGE:
601 if (chan->output)
602 return ad7293_set_offset(st,
603 chan->channel +
604 AD7293_VOUT_MIN_OFFSET_CH,
605 val);
606 else
607 return ad7293_set_offset(st, chan->channel, val);
608 case IIO_CURRENT:
609 return ad7293_set_offset(st,
610 chan->channel +
611 AD7293_ISENSE_MIN_OFFSET_CH,
612 val);
613 case IIO_TEMP:
614 return ad7293_set_offset(st,
615 chan->channel +
616 AD7293_TSENSE_MIN_OFFSET_CH,
617 val);
618 default:
619 return -EINVAL;
620 }
621 case IIO_CHAN_INFO_SCALE:
622 switch (chan->type) {
623 case IIO_VOLTAGE:
624 return ad7293_adc_set_scale(st, chan->channel, val);
625 case IIO_CURRENT:
626 return ad7293_isense_set_scale(st, chan->channel, val);
627 default:
628 return -EINVAL;
629 }
630 default:
631 return -EINVAL;
632 }
633 }
634
ad7293_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int write_val,unsigned int * read_val)635 static int ad7293_reg_access(struct iio_dev *indio_dev,
636 unsigned int reg,
637 unsigned int write_val,
638 unsigned int *read_val)
639 {
640 struct ad7293_state *st = iio_priv(indio_dev);
641 int ret;
642
643 if (read_val) {
644 u16 temp;
645 ret = ad7293_spi_read(st, reg, &temp);
646 *read_val = temp;
647 } else {
648 ret = ad7293_spi_write(st, reg, (u16)write_val);
649 }
650
651 return ret;
652 }
653
ad7293_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long info)654 static int ad7293_read_avail(struct iio_dev *indio_dev,
655 struct iio_chan_spec const *chan,
656 const int **vals, int *type, int *length,
657 long info)
658 {
659 switch (info) {
660 case IIO_CHAN_INFO_OFFSET:
661 *vals = dac_offset_table;
662 *type = IIO_VAL_INT;
663 *length = ARRAY_SIZE(dac_offset_table);
664
665 return IIO_AVAIL_LIST;
666 case IIO_CHAN_INFO_SCALE:
667 *type = IIO_VAL_INT;
668
669 switch (chan->type) {
670 case IIO_VOLTAGE:
671 *vals = adc_range_table;
672 *length = ARRAY_SIZE(adc_range_table);
673 return IIO_AVAIL_LIST;
674 case IIO_CURRENT:
675 *vals = isense_gain_table;
676 *length = ARRAY_SIZE(isense_gain_table);
677 return IIO_AVAIL_LIST;
678 default:
679 return -EINVAL;
680 }
681 default:
682 return -EINVAL;
683 }
684 }
685
686 #define AD7293_CHAN_ADC(_channel) { \
687 .type = IIO_VOLTAGE, \
688 .output = 0, \
689 .indexed = 1, \
690 .channel = _channel, \
691 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
692 BIT(IIO_CHAN_INFO_SCALE) | \
693 BIT(IIO_CHAN_INFO_OFFSET), \
694 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE) \
695 }
696
697 #define AD7293_CHAN_DAC(_channel) { \
698 .type = IIO_VOLTAGE, \
699 .output = 1, \
700 .indexed = 1, \
701 .channel = _channel, \
702 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
703 BIT(IIO_CHAN_INFO_OFFSET), \
704 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_OFFSET) \
705 }
706
707 #define AD7293_CHAN_ISENSE(_channel) { \
708 .type = IIO_CURRENT, \
709 .output = 0, \
710 .indexed = 1, \
711 .channel = _channel, \
712 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
713 BIT(IIO_CHAN_INFO_OFFSET) | \
714 BIT(IIO_CHAN_INFO_SCALE), \
715 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE) \
716 }
717
718 #define AD7293_CHAN_TEMP(_channel) { \
719 .type = IIO_TEMP, \
720 .output = 0, \
721 .indexed = 1, \
722 .channel = _channel, \
723 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
724 BIT(IIO_CHAN_INFO_OFFSET), \
725 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) \
726 }
727
728 static const struct iio_chan_spec ad7293_channels[] = {
729 AD7293_CHAN_ADC(0),
730 AD7293_CHAN_ADC(1),
731 AD7293_CHAN_ADC(2),
732 AD7293_CHAN_ADC(3),
733 AD7293_CHAN_ISENSE(0),
734 AD7293_CHAN_ISENSE(1),
735 AD7293_CHAN_ISENSE(2),
736 AD7293_CHAN_ISENSE(3),
737 AD7293_CHAN_TEMP(0),
738 AD7293_CHAN_TEMP(1),
739 AD7293_CHAN_TEMP(2),
740 AD7293_CHAN_DAC(0),
741 AD7293_CHAN_DAC(1),
742 AD7293_CHAN_DAC(2),
743 AD7293_CHAN_DAC(3),
744 AD7293_CHAN_DAC(4),
745 AD7293_CHAN_DAC(5),
746 AD7293_CHAN_DAC(6),
747 AD7293_CHAN_DAC(7)
748 };
749
ad7293_soft_reset(struct ad7293_state * st)750 static int ad7293_soft_reset(struct ad7293_state *st)
751 {
752 int ret;
753
754 ret = __ad7293_spi_write(st, AD7293_REG_SOFT_RESET, 0x7293);
755 if (ret)
756 return ret;
757
758 return __ad7293_spi_write(st, AD7293_REG_SOFT_RESET, 0x0000);
759 }
760
ad7293_reset(struct ad7293_state * st)761 static int ad7293_reset(struct ad7293_state *st)
762 {
763 if (st->gpio_reset) {
764 gpiod_set_value(st->gpio_reset, 0);
765 usleep_range(100, 1000);
766 gpiod_set_value(st->gpio_reset, 1);
767 usleep_range(100, 1000);
768
769 return 0;
770 }
771
772 /* Perform a software reset */
773 return ad7293_soft_reset(st);
774 }
775
ad7293_properties_parse(struct ad7293_state * st)776 static int ad7293_properties_parse(struct ad7293_state *st)
777 {
778 struct device *dev = &st->spi->dev;
779 int ret;
780
781 ret = devm_regulator_get_enable(dev, "avdd");
782 if (ret)
783 return dev_err_probe(dev, ret, "failed to enable AVDD\n");
784
785 ret = devm_regulator_get_enable(dev, "vdrive");
786 if (ret)
787 return dev_err_probe(dev, ret, "failed to enable VDRIVE\n");
788
789 ret = devm_regulator_get_enable_optional(dev, "vrefin");
790 if (ret < 0 && ret != -ENODEV)
791 return dev_err_probe(dev, ret, "failed to enable VREFIN\n");
792
793 st->vrefin_en = ret != -ENODEV;
794
795 st->gpio_reset = devm_gpiod_get_optional(dev, "reset",
796 GPIOD_OUT_HIGH);
797 if (IS_ERR(st->gpio_reset))
798 return dev_err_probe(dev, PTR_ERR(st->gpio_reset),
799 "failed to get the reset GPIO\n");
800
801 return 0;
802 }
803
ad7293_init(struct ad7293_state * st)804 static int ad7293_init(struct ad7293_state *st)
805 {
806 int ret;
807 u16 chip_id;
808 struct device *dev = &st->spi->dev;
809
810 ret = ad7293_properties_parse(st);
811 if (ret)
812 return ret;
813
814 ret = ad7293_reset(st);
815 if (ret)
816 return ret;
817
818 /* Check Chip ID */
819 ret = __ad7293_spi_read(st, AD7293_REG_DEVICE_ID, &chip_id);
820 if (ret)
821 return ret;
822
823 if (chip_id != AD7293_CHIP_ID)
824 return dev_err_probe(dev, -EINVAL, "Invalid Chip ID.\n");
825
826 if (!st->vrefin_en)
827 return __ad7293_spi_update_bits(st, AD7293_REG_GENERAL,
828 AD7293_GENERAL_ADC_REF_MSK,
829 AD7293_GENERAL_ADC_REF_MSK);
830
831 return 0;
832 }
833
834 static const struct iio_info ad7293_info = {
835 .read_raw = ad7293_read_raw,
836 .write_raw = ad7293_write_raw,
837 .read_avail = &ad7293_read_avail,
838 .debugfs_reg_access = &ad7293_reg_access,
839 };
840
ad7293_probe(struct spi_device * spi)841 static int ad7293_probe(struct spi_device *spi)
842 {
843 struct iio_dev *indio_dev;
844 struct ad7293_state *st;
845 struct device *dev = &spi->dev;
846 int ret;
847
848 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
849 if (!indio_dev)
850 return -ENOMEM;
851
852 st = iio_priv(indio_dev);
853
854 indio_dev->info = &ad7293_info;
855 indio_dev->name = "ad7293";
856 indio_dev->channels = ad7293_channels;
857 indio_dev->num_channels = ARRAY_SIZE(ad7293_channels);
858
859 st->spi = spi;
860 st->page_select = 0;
861
862 mutex_init(&st->lock);
863
864 ret = ad7293_init(st);
865 if (ret)
866 return ret;
867
868 return devm_iio_device_register(dev, indio_dev);
869 }
870
871 static const struct spi_device_id ad7293_id[] = {
872 { "ad7293", 0 },
873 { }
874 };
875 MODULE_DEVICE_TABLE(spi, ad7293_id);
876
877 static const struct of_device_id ad7293_of_match[] = {
878 { .compatible = "adi,ad7293" },
879 { }
880 };
881 MODULE_DEVICE_TABLE(of, ad7293_of_match);
882
883 static struct spi_driver ad7293_driver = {
884 .driver = {
885 .name = "ad7293",
886 .of_match_table = ad7293_of_match,
887 },
888 .probe = ad7293_probe,
889 .id_table = ad7293_id,
890 };
891 module_spi_driver(ad7293_driver);
892
893 MODULE_AUTHOR("Antoniu Miclaus <antoniu.miclaus@analog.com");
894 MODULE_DESCRIPTION("Analog Devices AD7293");
895 MODULE_LICENSE("GPL v2");
896