1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * AD7124 SPI ADC driver
4 *
5 * Copyright 2018 Analog Devices Inc.
6 * Copyright 2025 BayLibre, SAS
7 */
8 #include <linux/bitfield.h>
9 #include <linux/bitops.h>
10 #include <linux/cleanup.h>
11 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
13 #include <linux/debugfs.h>
14 #include <linux/delay.h>
15 #include <linux/device.h>
16 #include <linux/err.h>
17 #include <linux/interrupt.h>
18 #include <linux/kernel.h>
19 #include <linux/kfifo.h>
20 #include <linux/minmax.h>
21 #include <linux/module.h>
22 #include <linux/property.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/spi/spi.h>
25 #include <linux/sprintf.h>
26 #include <linux/units.h>
27
28 #include <linux/iio/iio.h>
29 #include <linux/iio/adc/ad_sigma_delta.h>
30 #include <linux/iio/sysfs.h>
31
32 /* AD7124 registers */
33 #define AD7124_COMMS 0x00
34 #define AD7124_STATUS 0x00
35 #define AD7124_ADC_CONTROL 0x01
36 #define AD7124_DATA 0x02
37 #define AD7124_IO_CONTROL_1 0x03
38 #define AD7124_IO_CONTROL_2 0x04
39 #define AD7124_ID 0x05
40 #define AD7124_ERROR 0x06
41 #define AD7124_ERROR_EN 0x07
42 #define AD7124_MCLK_COUNT 0x08
43 #define AD7124_CHANNEL(x) (0x09 + (x))
44 #define AD7124_CONFIG(x) (0x19 + (x))
45 #define AD7124_FILTER(x) (0x21 + (x))
46 #define AD7124_OFFSET(x) (0x29 + (x))
47 #define AD7124_GAIN(x) (0x31 + (x))
48
49 /* AD7124_STATUS */
50 #define AD7124_STATUS_POR_FLAG BIT(4)
51
52 /* AD7124_ADC_CONTROL */
53 #define AD7124_ADC_CONTROL_CLK_SEL GENMASK(1, 0)
54 #define AD7124_ADC_CONTROL_CLK_SEL_INT 0
55 #define AD7124_ADC_CONTROL_CLK_SEL_INT_OUT 1
56 #define AD7124_ADC_CONTROL_CLK_SEL_EXT 2
57 #define AD7124_ADC_CONTROL_CLK_SEL_EXT_DIV4 3
58 #define AD7124_ADC_CONTROL_MODE GENMASK(5, 2)
59 #define AD7124_ADC_CONTROL_MODE_CONTINUOUS 0
60 #define AD7124_ADC_CONTROL_MODE_SINGLE 1
61 #define AD7124_ADC_CONTROL_MODE_STANDBY 2
62 #define AD7124_ADC_CONTROL_MODE_POWERDOWN 3
63 #define AD7124_ADC_CONTROL_MODE_IDLE 4
64 #define AD7124_ADC_CONTROL_MODE_INT_OFFSET_CALIB 5 /* Internal Zero-Scale Calibration */
65 #define AD7124_ADC_CONTROL_MODE_INT_GAIN_CALIB 6 /* Internal Full-Scale Calibration */
66 #define AD7124_ADC_CONTROL_MODE_SYS_OFFSET_CALIB 7 /* System Zero-Scale Calibration */
67 #define AD7124_ADC_CONTROL_MODE_SYS_GAIN_CALIB 8 /* System Full-Scale Calibration */
68 #define AD7124_ADC_CONTROL_POWER_MODE GENMASK(7, 6)
69 #define AD7124_ADC_CONTROL_POWER_MODE_LOW 0
70 #define AD7124_ADC_CONTROL_POWER_MODE_MID 1
71 #define AD7124_ADC_CONTROL_POWER_MODE_FULL 2
72 #define AD7124_ADC_CONTROL_REF_EN BIT(8)
73 #define AD7124_ADC_CONTROL_DATA_STATUS BIT(10)
74
75 /* AD7124_ID */
76 #define AD7124_ID_SILICON_REVISION GENMASK(3, 0)
77 #define AD7124_ID_DEVICE_ID GENMASK(7, 4)
78 #define AD7124_ID_DEVICE_ID_AD7124_4 0x0
79 #define AD7124_ID_DEVICE_ID_AD7124_8 0x1
80
81 /* AD7124_CHANNEL_X */
82 #define AD7124_CHANNEL_ENABLE BIT(15)
83 #define AD7124_CHANNEL_SETUP GENMASK(14, 12)
84 #define AD7124_CHANNEL_AINP GENMASK(9, 5)
85 #define AD7124_CHANNEL_AINM GENMASK(4, 0)
86 #define AD7124_CHANNEL_AINx_TEMPSENSOR 16
87 #define AD7124_CHANNEL_AINx_AVSS 17
88
89 /* AD7124_CONFIG_X */
90 #define AD7124_CONFIG_BIPOLAR BIT(11)
91 #define AD7124_CONFIG_IN_BUFF GENMASK(6, 5)
92 #define AD7124_CONFIG_AIN_BUFP BIT(6)
93 #define AD7124_CONFIG_AIN_BUFM BIT(5)
94 #define AD7124_CONFIG_REF_SEL GENMASK(4, 3)
95 #define AD7124_CONFIG_PGA GENMASK(2, 0)
96
97 /* AD7124_FILTER_X */
98 #define AD7124_FILTER_FILTER GENMASK(23, 21)
99 #define AD7124_FILTER_FILTER_SINC4 0
100 #define AD7124_FILTER_FILTER_SINC3 2
101 #define AD7124_FILTER_FILTER_SINC4_SINC1 4
102 #define AD7124_FILTER_FILTER_SINC3_SINC1 5
103 #define AD7124_FILTER_FILTER_SINC3_PF 7
104 #define AD7124_FILTER_REJ60 BIT(20)
105 #define AD7124_FILTER_POST_FILTER GENMASK(19, 17)
106 #define AD7124_FILTER_POST_FILTER_47dB 2
107 #define AD7124_FILTER_POST_FILTER_62dB 3
108 #define AD7124_FILTER_POST_FILTER_86dB 5
109 #define AD7124_FILTER_POST_FILTER_92dB 6
110 #define AD7124_FILTER_SINGLE_CYCLE BIT(16)
111 #define AD7124_FILTER_FS GENMASK(10, 0)
112
113 #define AD7124_CFG_SLOT_UNASSIGNED ~0U
114
115 #define AD7124_MAX_CONFIGS 8
116 #define AD7124_MAX_CHANNELS 16
117
118 #define AD7124_INT_CLK_HZ 614400
119
120 /* AD7124 input sources */
121
122 enum ad7124_ref_sel {
123 AD7124_REFIN1,
124 AD7124_REFIN2,
125 AD7124_INT_REF,
126 AD7124_AVDD_REF,
127 };
128
129 enum ad7124_power_mode {
130 AD7124_LOW_POWER,
131 AD7124_MID_POWER,
132 AD7124_FULL_POWER,
133 };
134
135 static const unsigned int ad7124_gain[8] = {
136 1, 2, 4, 8, 16, 32, 64, 128
137 };
138
139 static const unsigned int ad7124_reg_size[] = {
140 1, 2, 3, 3, 2, 1, 3, 3, 1, 2, 2, 2, 2,
141 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
142 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3,
143 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
144 3, 3, 3, 3, 3
145 };
146
147 static const int ad7124_master_clk_freq_hz[3] = {
148 [AD7124_LOW_POWER] = AD7124_INT_CLK_HZ / 8,
149 [AD7124_MID_POWER] = AD7124_INT_CLK_HZ / 4,
150 [AD7124_FULL_POWER] = AD7124_INT_CLK_HZ,
151 };
152
153 static const char * const ad7124_ref_names[] = {
154 [AD7124_REFIN1] = "refin1",
155 [AD7124_REFIN2] = "refin2",
156 [AD7124_INT_REF] = "int",
157 [AD7124_AVDD_REF] = "avdd",
158 };
159
160 struct ad7124_chip_info {
161 const char *name;
162 unsigned int chip_id;
163 unsigned int num_inputs;
164 };
165
166 enum ad7124_filter_type {
167 AD7124_FILTER_TYPE_SINC3,
168 AD7124_FILTER_TYPE_SINC3_PF1,
169 AD7124_FILTER_TYPE_SINC3_PF2,
170 AD7124_FILTER_TYPE_SINC3_PF3,
171 AD7124_FILTER_TYPE_SINC3_PF4,
172 AD7124_FILTER_TYPE_SINC3_REJ60,
173 AD7124_FILTER_TYPE_SINC3_SINC1,
174 AD7124_FILTER_TYPE_SINC4,
175 AD7124_FILTER_TYPE_SINC4_REJ60,
176 AD7124_FILTER_TYPE_SINC4_SINC1,
177 };
178
179 struct ad7124_channel_config {
180 unsigned int cfg_slot;
181 unsigned int requested_odr;
182 unsigned int requested_odr_micro;
183 /*
184 * Following fields are used to compare for equality. If you
185 * make adaptations in it, you most likely also have to adapt
186 * ad7124_config_equal(), too.
187 */
188 struct_group(config_props,
189 enum ad7124_ref_sel refsel;
190 bool bipolar;
191 bool buf_positive;
192 bool buf_negative;
193 unsigned int vref_mv;
194 unsigned int pga_bits;
195 unsigned int odr_sel_bits;
196 enum ad7124_filter_type filter_type;
197 unsigned int calibration_offset;
198 unsigned int calibration_gain;
199 );
200 };
201
202 struct ad7124_channel {
203 struct ad7124_channel_config cfg;
204 unsigned int ain;
205 unsigned int slot;
206 u8 syscalib_mode;
207 };
208
209 struct ad7124_state {
210 const struct ad7124_chip_info *chip_info;
211 struct ad_sigma_delta sd;
212 struct ad7124_channel *channels;
213 struct regulator *vref[4];
214 u32 clk_hz;
215 unsigned int adc_control;
216 unsigned int num_channels;
217 struct mutex cfgs_lock; /* lock for configs access */
218 u8 cfg_slot_use_count[AD7124_MAX_CONFIGS];
219
220 /*
221 * Stores the power-on reset value for the GAIN(x) registers which are
222 * needed for measurements at gain 1 (i.e. CONFIG(x).PGA == 0)
223 */
224 unsigned int gain_default;
225 bool enable_single_cycle;
226 };
227
228 static const struct ad7124_chip_info ad7124_4_chip_info = {
229 .name = "ad7124-4",
230 .chip_id = AD7124_ID_DEVICE_ID_AD7124_4,
231 .num_inputs = 8,
232 };
233
234 static const struct ad7124_chip_info ad7124_8_chip_info = {
235 .name = "ad7124-8",
236 .chip_id = AD7124_ID_DEVICE_ID_AD7124_8,
237 .num_inputs = 16,
238 };
239
ad7124_find_closest_match(const int * array,unsigned int size,int val)240 static int ad7124_find_closest_match(const int *array,
241 unsigned int size, int val)
242 {
243 int i, idx;
244 unsigned int diff_new, diff_old;
245
246 diff_old = U32_MAX;
247 idx = 0;
248
249 for (i = 0; i < size; i++) {
250 diff_new = abs(val - array[i]);
251 if (diff_new < diff_old) {
252 diff_old = diff_new;
253 idx = i;
254 }
255 }
256
257 return idx;
258 }
259
ad7124_spi_write_mask(struct ad7124_state * st,unsigned int addr,unsigned long mask,unsigned int val,unsigned int bytes)260 static int ad7124_spi_write_mask(struct ad7124_state *st,
261 unsigned int addr,
262 unsigned long mask,
263 unsigned int val,
264 unsigned int bytes)
265 {
266 unsigned int readval;
267 int ret;
268
269 ret = ad_sd_read_reg(&st->sd, addr, bytes, &readval);
270 if (ret < 0)
271 return ret;
272
273 readval &= ~mask;
274 readval |= val;
275
276 return ad_sd_write_reg(&st->sd, addr, bytes, readval);
277 }
278
ad7124_set_mode(struct ad_sigma_delta * sd,enum ad_sigma_delta_mode mode)279 static int ad7124_set_mode(struct ad_sigma_delta *sd,
280 enum ad_sigma_delta_mode mode)
281 {
282 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
283
284 st->adc_control &= ~AD7124_ADC_CONTROL_MODE;
285 st->adc_control |= FIELD_PREP(AD7124_ADC_CONTROL_MODE, mode);
286
287 return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
288 }
289
ad7124_get_fclk_hz(struct ad7124_state * st)290 static u32 ad7124_get_fclk_hz(struct ad7124_state *st)
291 {
292 enum ad7124_power_mode power_mode;
293 u32 fclk_hz;
294
295 power_mode = FIELD_GET(AD7124_ADC_CONTROL_POWER_MODE, st->adc_control);
296 fclk_hz = st->clk_hz;
297
298 switch (power_mode) {
299 case AD7124_LOW_POWER:
300 fclk_hz /= 8;
301 break;
302 case AD7124_MID_POWER:
303 fclk_hz /= 4;
304 break;
305 default:
306 break;
307 }
308
309 return fclk_hz;
310 }
311
ad7124_get_fs_factor(struct ad7124_state * st,unsigned int channel)312 static u32 ad7124_get_fs_factor(struct ad7124_state *st, unsigned int channel)
313 {
314 enum ad7124_power_mode power_mode =
315 FIELD_GET(AD7124_ADC_CONTROL_POWER_MODE, st->adc_control);
316 u32 avg = power_mode == AD7124_LOW_POWER ? 8 : 16;
317
318 /*
319 * These are the "zero-latency" factors from the data sheet. For the
320 * sinc1 filters, these aren't documented, but derived by taking the
321 * single-channel formula from the sinc1 section of the data sheet and
322 * multiplying that by the sinc3/4 factor from the corresponding zero-
323 * latency sections.
324 */
325 switch (st->channels[channel].cfg.filter_type) {
326 case AD7124_FILTER_TYPE_SINC4:
327 case AD7124_FILTER_TYPE_SINC4_REJ60:
328 return 4 * 32;
329 case AD7124_FILTER_TYPE_SINC4_SINC1:
330 return 4 * avg * 32;
331 case AD7124_FILTER_TYPE_SINC3_SINC1:
332 return 3 * avg * 32;
333 default:
334 return 3 * 32;
335 }
336 }
337
ad7124_get_fadc_divisor(struct ad7124_state * st,unsigned int channel)338 static u32 ad7124_get_fadc_divisor(struct ad7124_state *st, unsigned int channel)
339 {
340 u32 factor = ad7124_get_fs_factor(st, channel);
341
342 /*
343 * The output data rate (f_ADC) is f_CLK / divisor. We are returning
344 * the divisor.
345 */
346 return st->channels[channel].cfg.odr_sel_bits * factor;
347 }
348
ad7124_set_channel_odr(struct ad7124_state * st,unsigned int channel)349 static void ad7124_set_channel_odr(struct ad7124_state *st, unsigned int channel)
350 {
351 struct ad7124_channel_config *cfg = &st->channels[channel].cfg;
352 unsigned int fclk, factor, divisor, odr_sel_bits;
353
354 fclk = ad7124_get_fclk_hz(st);
355 factor = ad7124_get_fs_factor(st, channel);
356
357 /*
358 * FS[10:0] = fCLK / (fADC x 32 * N) where:
359 * fADC is the output data rate
360 * fCLK is the master clock frequency
361 * N is number of conversions per sample (depends on filter type)
362 * FS[10:0] are the bits in the filter register
363 * FS[10:0] can have a value from 1 to 2047
364 */
365 divisor = cfg->requested_odr * factor +
366 cfg->requested_odr_micro * factor / MICRO;
367 odr_sel_bits = clamp(DIV_ROUND_CLOSEST(fclk, divisor), 1, 2047);
368
369 st->channels[channel].cfg.odr_sel_bits = odr_sel_bits;
370 }
371
ad7124_get_3db_filter_factor(struct ad7124_state * st,unsigned int channel)372 static int ad7124_get_3db_filter_factor(struct ad7124_state *st,
373 unsigned int channel)
374 {
375 struct ad7124_channel_config *cfg = &st->channels[channel].cfg;
376
377 /*
378 * 3dB point is the f_CLK rate times some factor. This functions returns
379 * the factor times 1000.
380 */
381 switch (cfg->filter_type) {
382 case AD7124_FILTER_TYPE_SINC3:
383 case AD7124_FILTER_TYPE_SINC3_REJ60:
384 case AD7124_FILTER_TYPE_SINC3_SINC1:
385 return 272;
386 case AD7124_FILTER_TYPE_SINC4:
387 case AD7124_FILTER_TYPE_SINC4_REJ60:
388 case AD7124_FILTER_TYPE_SINC4_SINC1:
389 return 230;
390 case AD7124_FILTER_TYPE_SINC3_PF1:
391 return 633;
392 case AD7124_FILTER_TYPE_SINC3_PF2:
393 return 605;
394 case AD7124_FILTER_TYPE_SINC3_PF3:
395 return 669;
396 case AD7124_FILTER_TYPE_SINC3_PF4:
397 return 759;
398 default:
399 return -EINVAL;
400 }
401 }
402
403 /* Only called during probe, so dev_err_probe() can be used */
ad7124_init_config_vref(struct ad7124_state * st,struct ad7124_channel_config * cfg)404 static int ad7124_init_config_vref(struct ad7124_state *st, struct ad7124_channel_config *cfg)
405 {
406 struct device *dev = &st->sd.spi->dev;
407 unsigned int refsel = cfg->refsel;
408
409 switch (refsel) {
410 case AD7124_REFIN1:
411 case AD7124_REFIN2:
412 case AD7124_AVDD_REF:
413 if (IS_ERR(st->vref[refsel]))
414 return dev_err_probe(dev, PTR_ERR(st->vref[refsel]),
415 "Error, trying to use external voltage reference without a %s regulator.\n",
416 ad7124_ref_names[refsel]);
417
418 cfg->vref_mv = regulator_get_voltage(st->vref[refsel]);
419 /* Conversion from uV to mV */
420 cfg->vref_mv /= 1000;
421 return 0;
422 case AD7124_INT_REF:
423 cfg->vref_mv = 2500;
424 st->adc_control |= AD7124_ADC_CONTROL_REF_EN;
425 return 0;
426 default:
427 return dev_err_probe(dev, -EINVAL, "Invalid reference %d\n", refsel);
428 }
429 }
430
ad7124_config_equal(struct ad7124_channel_config * a,struct ad7124_channel_config * b)431 static bool ad7124_config_equal(struct ad7124_channel_config *a,
432 struct ad7124_channel_config *b)
433 {
434 return a->refsel == b->refsel &&
435 a->bipolar == b->bipolar &&
436 a->buf_positive == b->buf_positive &&
437 a->buf_negative == b->buf_negative &&
438 a->vref_mv == b->vref_mv &&
439 a->pga_bits == b->pga_bits &&
440 a->odr_sel_bits == b->odr_sel_bits &&
441 a->filter_type == b->filter_type &&
442 a->calibration_offset == b->calibration_offset &&
443 a->calibration_gain == b->calibration_gain;
444 }
445
ad7124_write_config(struct ad7124_state * st,struct ad7124_channel_config * cfg,unsigned int cfg_slot)446 static int ad7124_write_config(struct ad7124_state *st, struct ad7124_channel_config *cfg,
447 unsigned int cfg_slot)
448 {
449 unsigned int val, filter;
450 unsigned int rej60 = 0;
451 unsigned int post = 0;
452 int ret;
453
454 ret = ad_sd_write_reg(&st->sd, AD7124_OFFSET(cfg_slot), 3,
455 cfg->calibration_offset);
456 if (ret)
457 return ret;
458
459 ret = ad_sd_write_reg(&st->sd, AD7124_GAIN(cfg_slot), 3,
460 cfg->calibration_gain);
461 if (ret)
462 return ret;
463
464 val = FIELD_PREP(AD7124_CONFIG_BIPOLAR, cfg->bipolar) |
465 FIELD_PREP(AD7124_CONFIG_REF_SEL, cfg->refsel) |
466 (cfg->buf_positive ? AD7124_CONFIG_AIN_BUFP : 0) |
467 (cfg->buf_negative ? AD7124_CONFIG_AIN_BUFM : 0) |
468 FIELD_PREP(AD7124_CONFIG_PGA, cfg->pga_bits);
469
470 ret = ad_sd_write_reg(&st->sd, AD7124_CONFIG(cfg_slot), 2, val);
471 if (ret < 0)
472 return ret;
473
474 switch (cfg->filter_type) {
475 case AD7124_FILTER_TYPE_SINC3:
476 filter = AD7124_FILTER_FILTER_SINC3;
477 break;
478 case AD7124_FILTER_TYPE_SINC3_PF1:
479 filter = AD7124_FILTER_FILTER_SINC3_PF;
480 post = AD7124_FILTER_POST_FILTER_47dB;
481 break;
482 case AD7124_FILTER_TYPE_SINC3_PF2:
483 filter = AD7124_FILTER_FILTER_SINC3_PF;
484 post = AD7124_FILTER_POST_FILTER_62dB;
485 break;
486 case AD7124_FILTER_TYPE_SINC3_PF3:
487 filter = AD7124_FILTER_FILTER_SINC3_PF;
488 post = AD7124_FILTER_POST_FILTER_86dB;
489 break;
490 case AD7124_FILTER_TYPE_SINC3_PF4:
491 filter = AD7124_FILTER_FILTER_SINC3_PF;
492 post = AD7124_FILTER_POST_FILTER_92dB;
493 break;
494 case AD7124_FILTER_TYPE_SINC3_REJ60:
495 filter = AD7124_FILTER_FILTER_SINC3;
496 rej60 = 1;
497 break;
498 case AD7124_FILTER_TYPE_SINC3_SINC1:
499 filter = AD7124_FILTER_FILTER_SINC3_SINC1;
500 break;
501 case AD7124_FILTER_TYPE_SINC4:
502 filter = AD7124_FILTER_FILTER_SINC4;
503 break;
504 case AD7124_FILTER_TYPE_SINC4_REJ60:
505 filter = AD7124_FILTER_FILTER_SINC4;
506 rej60 = 1;
507 break;
508 case AD7124_FILTER_TYPE_SINC4_SINC1:
509 filter = AD7124_FILTER_FILTER_SINC4_SINC1;
510 break;
511 default:
512 return -EINVAL;
513 }
514
515 /*
516 * NB: AD7124_FILTER_SINGLE_CYCLE is always set so that we get the same
517 * sampling frequency even when only one channel is enabled in a
518 * buffered read. If it was not set, the N in ad7124_set_channel_odr()
519 * would be 1 and we would get a faster sampling frequency than what
520 * was requested. It may only be disabled through debugfs for testing
521 * purposes.
522 */
523 return ad_sd_write_reg(&st->sd, AD7124_FILTER(cfg_slot), 3,
524 FIELD_PREP(AD7124_FILTER_FILTER, filter) |
525 FIELD_PREP(AD7124_FILTER_REJ60, rej60) |
526 FIELD_PREP(AD7124_FILTER_POST_FILTER, post) |
527 FIELD_PREP(AD7124_FILTER_SINGLE_CYCLE,
528 st->enable_single_cycle) |
529 FIELD_PREP(AD7124_FILTER_FS, cfg->odr_sel_bits));
530 }
531
532 /**
533 * ad7124_request_config_slot() - Request a config slot for a given config
534 * @st: Driver instance
535 * @channel: Channel to request a slot for
536 *
537 * Tries to find a matching config already in use, otherwise finds a free
538 * slot. If this function returns successfully, the use count for the slot is
539 * increased and the slot number is stored in cfg->cfg_slot.
540 *
541 * The slot must be released again with ad7124_release_config_slot() when no
542 * longer needed.
543 *
544 * Returns: 0 if a slot was successfully assigned, -EUSERS if no slot is
545 * available or other error if SPI communication fails.
546 */
ad7124_request_config_slot(struct ad7124_state * st,u8 channel)547 static int ad7124_request_config_slot(struct ad7124_state *st, u8 channel)
548 {
549 unsigned int other, slot;
550 int last_used_slot = -1;
551
552 /* Find another channel with a matching config, if any. */
553 for (other = 0; other < st->num_channels; other++) {
554 if (other == channel)
555 continue;
556
557 if (st->channels[other].cfg.cfg_slot == AD7124_CFG_SLOT_UNASSIGNED)
558 continue;
559
560 last_used_slot = max_t(int, last_used_slot,
561 st->channels[other].cfg.cfg_slot);
562
563 if (!ad7124_config_equal(&st->channels[other].cfg,
564 &st->channels[channel].cfg))
565 continue;
566
567 /* Found a match, re-use that slot. */
568 slot = st->channels[other].cfg.cfg_slot;
569 st->cfg_slot_use_count[slot]++;
570 st->channels[channel].cfg.cfg_slot = slot;
571
572 return 0;
573 }
574
575 /* No match, use next free slot. */
576 slot = last_used_slot + 1;
577 if (slot >= AD7124_MAX_CONFIGS)
578 return -EUSERS;
579
580 st->cfg_slot_use_count[slot]++;
581 st->channels[channel].cfg.cfg_slot = slot;
582
583 return ad7124_write_config(st, &st->channels[channel].cfg, slot);
584 }
585
ad7124_release_config_slot(struct ad7124_state * st,u8 channel)586 static void ad7124_release_config_slot(struct ad7124_state *st, u8 channel)
587 {
588 unsigned int slot;
589
590 /*
591 * All of these early return conditions can happen at probe when all
592 * channels are disabled. Otherwise, they should not happen normally.
593 */
594 if (channel >= st->num_channels)
595 return;
596
597 slot = st->channels[channel].cfg.cfg_slot;
598
599 if (slot == AD7124_CFG_SLOT_UNASSIGNED ||
600 st->cfg_slot_use_count[slot] == 0)
601 return;
602
603 st->cfg_slot_use_count[slot]--;
604 st->channels[channel].cfg.cfg_slot = AD7124_CFG_SLOT_UNASSIGNED;
605 }
606
ad7124_prepare_read(struct ad7124_state * st,int address)607 static int ad7124_prepare_read(struct ad7124_state *st, int address)
608 {
609 struct ad7124_channel_config *cfg = &st->channels[address].cfg;
610 int ret;
611
612 ret = ad7124_request_config_slot(st, address);
613 if (ret)
614 return ret;
615
616 /* point channel to the config slot and enable */
617 return ad_sd_write_reg(&st->sd, AD7124_CHANNEL(address), 2,
618 st->channels[address].ain |
619 FIELD_PREP(AD7124_CHANNEL_SETUP, cfg->cfg_slot) |
620 AD7124_CHANNEL_ENABLE);
621 }
622
ad7124_set_channel(struct ad_sigma_delta * sd,unsigned int channel)623 static int ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
624 {
625 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
626 int ret;
627
628 mutex_lock(&st->cfgs_lock);
629 ret = ad7124_prepare_read(st, channel);
630 mutex_unlock(&st->cfgs_lock);
631
632 return ret;
633 }
634
ad7124_append_status(struct ad_sigma_delta * sd,bool append)635 static int ad7124_append_status(struct ad_sigma_delta *sd, bool append)
636 {
637 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
638 unsigned int adc_control = st->adc_control;
639 int ret;
640
641 if (append)
642 adc_control |= AD7124_ADC_CONTROL_DATA_STATUS;
643 else
644 adc_control &= ~AD7124_ADC_CONTROL_DATA_STATUS;
645
646 ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, adc_control);
647 if (ret < 0)
648 return ret;
649
650 st->adc_control = adc_control;
651
652 return 0;
653 }
654
ad7124_disable_one(struct ad_sigma_delta * sd,unsigned int chan)655 static int ad7124_disable_one(struct ad_sigma_delta *sd, unsigned int chan)
656 {
657 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
658
659 ad7124_release_config_slot(st, chan);
660
661 /* The relevant thing here is that AD7124_CHANNEL_ENABLE is cleared. */
662 return ad_sd_write_reg(&st->sd, AD7124_CHANNEL(chan), 2, 0);
663 }
664
ad7124_disable_all(struct ad_sigma_delta * sd)665 static int ad7124_disable_all(struct ad_sigma_delta *sd)
666 {
667 int ret;
668 int i;
669
670 for (i = 0; i < AD7124_MAX_CHANNELS; i++) {
671 ret = ad7124_disable_one(sd, i);
672 if (ret < 0)
673 return ret;
674 }
675
676 return 0;
677 }
678
679 static const struct ad_sigma_delta_info ad7124_sigma_delta_info = {
680 .set_channel = ad7124_set_channel,
681 .append_status = ad7124_append_status,
682 .disable_all = ad7124_disable_all,
683 .disable_one = ad7124_disable_one,
684 .set_mode = ad7124_set_mode,
685 .has_registers = true,
686 .addr_shift = 0,
687 .read_mask = BIT(6),
688 .status_ch_mask = GENMASK(3, 0),
689 .data_reg = AD7124_DATA,
690 .num_slots = 8,
691 .irq_flags = IRQF_TRIGGER_FALLING,
692 .num_resetclks = 64,
693 };
694
695 static const int ad7124_voltage_scales[][2] = {
696 { 0, 1164 },
697 { 0, 2328 },
698 { 0, 4656 },
699 { 0, 9313 },
700 { 0, 18626 },
701 { 0, 37252 },
702 { 0, 74505 },
703 { 0, 149011 },
704 { 0, 298023 },
705 };
706
ad7124_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long info)707 static int ad7124_read_avail(struct iio_dev *indio_dev,
708 struct iio_chan_spec const *chan,
709 const int **vals, int *type, int *length, long info)
710 {
711 switch (info) {
712 case IIO_CHAN_INFO_SCALE:
713 *vals = (const int *)ad7124_voltage_scales;
714 *type = IIO_VAL_INT_PLUS_NANO;
715 *length = ARRAY_SIZE(ad7124_voltage_scales) * 2;
716 return IIO_AVAIL_LIST;
717 default:
718 return -EINVAL;
719 }
720 }
721
ad7124_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)722 static int ad7124_read_raw(struct iio_dev *indio_dev,
723 struct iio_chan_spec const *chan,
724 int *val, int *val2, long info)
725 {
726 struct ad7124_state *st = iio_priv(indio_dev);
727 int idx, ret;
728
729 switch (info) {
730 case IIO_CHAN_INFO_RAW:
731 ret = ad_sigma_delta_single_conversion(indio_dev, chan, val);
732 if (ret < 0)
733 return ret;
734
735 return IIO_VAL_INT;
736 case IIO_CHAN_INFO_SCALE:
737 switch (chan->type) {
738 case IIO_VOLTAGE:
739 mutex_lock(&st->cfgs_lock);
740
741 idx = st->channels[chan->address].cfg.pga_bits;
742 *val = st->channels[chan->address].cfg.vref_mv;
743 if (st->channels[chan->address].cfg.bipolar)
744 *val2 = chan->scan_type.realbits - 1 + idx;
745 else
746 *val2 = chan->scan_type.realbits + idx;
747
748 mutex_unlock(&st->cfgs_lock);
749 return IIO_VAL_FRACTIONAL_LOG2;
750
751 case IIO_TEMP:
752 /*
753 * According to the data sheet
754 * Temperature (°C)
755 * = ((Conversion − 0x800000)/13584) − 272.5
756 * = (Conversion − 0x800000 - 13584 * 272.5) / 13584
757 * = (Conversion − 12090248) / 13584
758 * So scale with 1000/13584 to yield °mC. Reduce by 8 to
759 * 125/1698.
760 */
761 *val = 125;
762 *val2 = 1698;
763 return IIO_VAL_FRACTIONAL;
764
765 default:
766 return -EINVAL;
767 }
768
769 case IIO_CHAN_INFO_OFFSET:
770 switch (chan->type) {
771 case IIO_VOLTAGE:
772 mutex_lock(&st->cfgs_lock);
773 if (st->channels[chan->address].cfg.bipolar)
774 *val = -(1 << (chan->scan_type.realbits - 1));
775 else
776 *val = 0;
777
778 mutex_unlock(&st->cfgs_lock);
779 return IIO_VAL_INT;
780
781 case IIO_TEMP:
782 /* see calculation above */
783 *val = -12090248;
784 return IIO_VAL_INT;
785
786 default:
787 return -EINVAL;
788 }
789
790 case IIO_CHAN_INFO_SAMP_FREQ: {
791 struct ad7124_channel_config *cfg = &st->channels[chan->address].cfg;
792
793 guard(mutex)(&st->cfgs_lock);
794
795 switch (cfg->filter_type) {
796 case AD7124_FILTER_TYPE_SINC3:
797 case AD7124_FILTER_TYPE_SINC3_REJ60:
798 case AD7124_FILTER_TYPE_SINC3_SINC1:
799 case AD7124_FILTER_TYPE_SINC4:
800 case AD7124_FILTER_TYPE_SINC4_REJ60:
801 case AD7124_FILTER_TYPE_SINC4_SINC1:
802 *val = ad7124_get_fclk_hz(st);
803 *val2 = ad7124_get_fadc_divisor(st, chan->address);
804 return IIO_VAL_FRACTIONAL;
805 /*
806 * Post filters force the chip to a fixed rate. These are the
807 * single-channel rates from the data sheet divided by 3 for
808 * the multi-channel case (data sheet doesn't explicitly state
809 * this but confirmed through testing).
810 */
811 case AD7124_FILTER_TYPE_SINC3_PF1:
812 *val = 300;
813 *val2 = 33;
814 return IIO_VAL_FRACTIONAL;
815 case AD7124_FILTER_TYPE_SINC3_PF2:
816 *val = 25;
817 *val2 = 3;
818 return IIO_VAL_FRACTIONAL;
819 case AD7124_FILTER_TYPE_SINC3_PF3:
820 *val = 20;
821 *val2 = 3;
822 return IIO_VAL_FRACTIONAL;
823 case AD7124_FILTER_TYPE_SINC3_PF4:
824 *val = 50;
825 *val2 = 9;
826 return IIO_VAL_FRACTIONAL;
827 default:
828 return -EINVAL;
829 }
830 }
831 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: {
832 guard(mutex)(&st->cfgs_lock);
833
834 ret = ad7124_get_3db_filter_factor(st, chan->address);
835 if (ret < 0)
836 return ret;
837
838 /* 3dB point is the f_CLK rate times a fractional value */
839 *val = ret * ad7124_get_fclk_hz(st);
840 *val2 = MILLI * ad7124_get_fadc_divisor(st, chan->address);
841 return IIO_VAL_FRACTIONAL;
842 }
843 default:
844 return -EINVAL;
845 }
846 }
847
ad7124_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)848 static int ad7124_write_raw(struct iio_dev *indio_dev,
849 struct iio_chan_spec const *chan,
850 int val, int val2, long info)
851 {
852 struct ad7124_state *st = iio_priv(indio_dev);
853 struct ad7124_channel_config *cfg = &st->channels[chan->address].cfg;
854 unsigned int res, gain, full_scale, vref;
855
856 guard(mutex)(&st->cfgs_lock);
857
858 switch (info) {
859 case IIO_CHAN_INFO_SAMP_FREQ:
860 if (val2 < 0 || val < 0 || (val2 == 0 && val == 0))
861 return -EINVAL;
862
863 cfg->requested_odr = val;
864 cfg->requested_odr_micro = val2;
865 ad7124_set_channel_odr(st, chan->address);
866
867 return 0;
868 case IIO_CHAN_INFO_SCALE:
869 if (val != 0)
870 return -EINVAL;
871
872 if (st->channels[chan->address].cfg.bipolar)
873 full_scale = 1 << (chan->scan_type.realbits - 1);
874 else
875 full_scale = 1 << chan->scan_type.realbits;
876
877 vref = st->channels[chan->address].cfg.vref_mv * 1000000LL;
878 res = DIV_ROUND_CLOSEST(vref, full_scale);
879 gain = DIV_ROUND_CLOSEST(res, val2);
880 res = ad7124_find_closest_match(ad7124_gain, ARRAY_SIZE(ad7124_gain), gain);
881
882 st->channels[chan->address].cfg.pga_bits = res;
883 return 0;
884 default:
885 return -EINVAL;
886 }
887 }
888
ad7124_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)889 static int ad7124_reg_access(struct iio_dev *indio_dev,
890 unsigned int reg,
891 unsigned int writeval,
892 unsigned int *readval)
893 {
894 struct ad7124_state *st = iio_priv(indio_dev);
895 int ret;
896
897 if (reg >= ARRAY_SIZE(ad7124_reg_size))
898 return -EINVAL;
899
900 if (readval)
901 ret = ad_sd_read_reg(&st->sd, reg, ad7124_reg_size[reg],
902 readval);
903 else
904 ret = ad_sd_write_reg(&st->sd, reg, ad7124_reg_size[reg],
905 writeval);
906
907 return ret;
908 }
909
ad7124_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * scan_mask)910 static int ad7124_update_scan_mode(struct iio_dev *indio_dev,
911 const unsigned long *scan_mask)
912 {
913 struct ad7124_state *st = iio_priv(indio_dev);
914 bool bit_set;
915 int ret;
916 int i;
917
918 guard(mutex)(&st->cfgs_lock);
919
920 for (i = 0; i < st->num_channels; i++) {
921 bit_set = test_bit(i, scan_mask);
922 if (bit_set)
923 ret = ad7124_prepare_read(st, i);
924 else
925 ret = ad7124_spi_write_mask(st, AD7124_CHANNEL(i), AD7124_CHANNEL_ENABLE,
926 0, 2);
927 if (ret < 0)
928 return ret;
929 }
930
931 return 0;
932 }
933
934 static const struct iio_info ad7124_info = {
935 .read_avail = ad7124_read_avail,
936 .read_raw = ad7124_read_raw,
937 .write_raw = ad7124_write_raw,
938 .debugfs_reg_access = &ad7124_reg_access,
939 .validate_trigger = ad_sd_validate_trigger,
940 .update_scan_mode = ad7124_update_scan_mode,
941 };
942
943 /* Only called during probe, so dev_err_probe() can be used */
ad7124_soft_reset(struct ad7124_state * st)944 static int ad7124_soft_reset(struct ad7124_state *st)
945 {
946 struct device *dev = &st->sd.spi->dev;
947 unsigned int readval, timeout;
948 int ret;
949
950 ret = ad_sd_reset(&st->sd);
951 if (ret < 0)
952 return ret;
953
954 fsleep(200);
955 timeout = 100;
956 do {
957 ret = ad_sd_read_reg(&st->sd, AD7124_STATUS, 1, &readval);
958 if (ret < 0)
959 return dev_err_probe(dev, ret, "Error reading status register\n");
960
961 if (!(readval & AD7124_STATUS_POR_FLAG))
962 break;
963
964 /* The AD7124 requires typically 2ms to power up and settle */
965 usleep_range(100, 2000);
966 } while (--timeout);
967
968 if (readval & AD7124_STATUS_POR_FLAG)
969 return dev_err_probe(dev, -EIO, "Soft reset failed\n");
970
971 ret = ad_sd_read_reg(&st->sd, AD7124_GAIN(0), 3, &st->gain_default);
972 if (ret < 0)
973 return dev_err_probe(dev, ret, "Error reading gain register\n");
974
975 dev_dbg(dev, "Reset value of GAIN register is 0x%x\n", st->gain_default);
976
977 return 0;
978 }
979
ad7124_check_chip_id(struct ad7124_state * st)980 static int ad7124_check_chip_id(struct ad7124_state *st)
981 {
982 struct device *dev = &st->sd.spi->dev;
983 unsigned int readval, chip_id, silicon_rev;
984 int ret;
985
986 ret = ad_sd_read_reg(&st->sd, AD7124_ID, 1, &readval);
987 if (ret < 0)
988 return dev_err_probe(dev, ret, "Failure to read ID register\n");
989
990 chip_id = FIELD_GET(AD7124_ID_DEVICE_ID, readval);
991 silicon_rev = FIELD_GET(AD7124_ID_SILICON_REVISION, readval);
992
993 if (chip_id != st->chip_info->chip_id)
994 return dev_err_probe(dev, -ENODEV,
995 "Chip ID mismatch: expected %u, got %u\n",
996 st->chip_info->chip_id, chip_id);
997
998 if (silicon_rev == 0)
999 return dev_err_probe(dev, -ENODEV,
1000 "Silicon revision empty. Chip may not be present\n");
1001
1002 return 0;
1003 }
1004
1005 enum {
1006 AD7124_SYSCALIB_ZERO_SCALE,
1007 AD7124_SYSCALIB_FULL_SCALE,
1008 };
1009
ad7124_syscalib_locked(struct ad7124_state * st,const struct iio_chan_spec * chan)1010 static int ad7124_syscalib_locked(struct ad7124_state *st, const struct iio_chan_spec *chan)
1011 {
1012 struct device *dev = &st->sd.spi->dev;
1013 struct ad7124_channel *ch = &st->channels[chan->address];
1014 int ret;
1015
1016 if (ch->syscalib_mode == AD7124_SYSCALIB_ZERO_SCALE) {
1017 ch->cfg.calibration_offset = 0x800000;
1018
1019 ret = ad_sd_calibrate(&st->sd, AD7124_ADC_CONTROL_MODE_SYS_OFFSET_CALIB,
1020 chan->address);
1021 if (ret < 0)
1022 return ret;
1023
1024 /*
1025 * Making the assumption that a single conversion will always
1026 * use configuration slot 0 for the OFFSET/GAIN registers.
1027 */
1028 ret = ad_sd_read_reg(&st->sd, AD7124_OFFSET(0), 3,
1029 &ch->cfg.calibration_offset);
1030 if (ret < 0)
1031 return ret;
1032
1033 dev_dbg(dev, "offset for channel %lu after zero-scale calibration: 0x%x\n",
1034 chan->address, ch->cfg.calibration_offset);
1035 } else {
1036 ch->cfg.calibration_gain = st->gain_default;
1037
1038 ret = ad_sd_calibrate(&st->sd, AD7124_ADC_CONTROL_MODE_SYS_GAIN_CALIB,
1039 chan->address);
1040 if (ret < 0)
1041 return ret;
1042
1043 ret = ad_sd_read_reg(&st->sd, AD7124_GAIN(0), 3,
1044 &ch->cfg.calibration_gain);
1045 if (ret < 0)
1046 return ret;
1047
1048 dev_dbg(dev, "gain for channel %lu after full-scale calibration: 0x%x\n",
1049 chan->address, ch->cfg.calibration_gain);
1050 }
1051
1052 return 0;
1053 }
1054
ad7124_write_syscalib(struct iio_dev * indio_dev,uintptr_t private,const struct iio_chan_spec * chan,const char * buf,size_t len)1055 static ssize_t ad7124_write_syscalib(struct iio_dev *indio_dev,
1056 uintptr_t private,
1057 const struct iio_chan_spec *chan,
1058 const char *buf, size_t len)
1059 {
1060 struct ad7124_state *st = iio_priv(indio_dev);
1061 bool sys_calib;
1062 int ret;
1063
1064 ret = kstrtobool(buf, &sys_calib);
1065 if (ret)
1066 return ret;
1067
1068 if (!sys_calib)
1069 return len;
1070
1071 if (!iio_device_claim_direct(indio_dev))
1072 return -EBUSY;
1073
1074 ret = ad7124_syscalib_locked(st, chan);
1075
1076 iio_device_release_direct(indio_dev);
1077
1078 return ret ?: len;
1079 }
1080
1081 static const char * const ad7124_syscalib_modes[] = {
1082 [AD7124_SYSCALIB_ZERO_SCALE] = "zero_scale",
1083 [AD7124_SYSCALIB_FULL_SCALE] = "full_scale",
1084 };
1085
ad7124_set_syscalib_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,unsigned int mode)1086 static int ad7124_set_syscalib_mode(struct iio_dev *indio_dev,
1087 const struct iio_chan_spec *chan,
1088 unsigned int mode)
1089 {
1090 struct ad7124_state *st = iio_priv(indio_dev);
1091
1092 st->channels[chan->address].syscalib_mode = mode;
1093
1094 return 0;
1095 }
1096
ad7124_get_syscalib_mode(struct iio_dev * indio_dev,const struct iio_chan_spec * chan)1097 static int ad7124_get_syscalib_mode(struct iio_dev *indio_dev,
1098 const struct iio_chan_spec *chan)
1099 {
1100 struct ad7124_state *st = iio_priv(indio_dev);
1101
1102 return st->channels[chan->address].syscalib_mode;
1103 }
1104
1105 static const struct iio_enum ad7124_syscalib_mode_enum = {
1106 .items = ad7124_syscalib_modes,
1107 .num_items = ARRAY_SIZE(ad7124_syscalib_modes),
1108 .set = ad7124_set_syscalib_mode,
1109 .get = ad7124_get_syscalib_mode
1110 };
1111
1112 static const char * const ad7124_filter_types[] = {
1113 [AD7124_FILTER_TYPE_SINC3] = "sinc3",
1114 [AD7124_FILTER_TYPE_SINC3_PF1] = "sinc3+pf1",
1115 [AD7124_FILTER_TYPE_SINC3_PF2] = "sinc3+pf2",
1116 [AD7124_FILTER_TYPE_SINC3_PF3] = "sinc3+pf3",
1117 [AD7124_FILTER_TYPE_SINC3_PF4] = "sinc3+pf4",
1118 [AD7124_FILTER_TYPE_SINC3_REJ60] = "sinc3+rej60",
1119 [AD7124_FILTER_TYPE_SINC3_SINC1] = "sinc3+sinc1",
1120 [AD7124_FILTER_TYPE_SINC4] = "sinc4",
1121 [AD7124_FILTER_TYPE_SINC4_REJ60] = "sinc4+rej60",
1122 [AD7124_FILTER_TYPE_SINC4_SINC1] = "sinc4+sinc1",
1123 };
1124
ad7124_set_filter_type_attr(struct iio_dev * dev,const struct iio_chan_spec * chan,unsigned int value)1125 static int ad7124_set_filter_type_attr(struct iio_dev *dev,
1126 const struct iio_chan_spec *chan,
1127 unsigned int value)
1128 {
1129 struct ad7124_state *st = iio_priv(dev);
1130 struct ad7124_channel_config *cfg = &st->channels[chan->address].cfg;
1131
1132 guard(mutex)(&st->cfgs_lock);
1133
1134 cfg->filter_type = value;
1135 ad7124_set_channel_odr(st, chan->address);
1136
1137 return 0;
1138 }
1139
ad7124_get_filter_type_attr(struct iio_dev * dev,const struct iio_chan_spec * chan)1140 static int ad7124_get_filter_type_attr(struct iio_dev *dev,
1141 const struct iio_chan_spec *chan)
1142 {
1143 struct ad7124_state *st = iio_priv(dev);
1144
1145 guard(mutex)(&st->cfgs_lock);
1146
1147 return st->channels[chan->address].cfg.filter_type;
1148 }
1149
1150 static const struct iio_enum ad7124_filter_type_enum = {
1151 .items = ad7124_filter_types,
1152 .num_items = ARRAY_SIZE(ad7124_filter_types),
1153 .set = ad7124_set_filter_type_attr,
1154 .get = ad7124_get_filter_type_attr,
1155 };
1156
1157 static const struct iio_chan_spec_ext_info ad7124_calibsys_ext_info[] = {
1158 {
1159 .name = "sys_calibration",
1160 .write = ad7124_write_syscalib,
1161 .shared = IIO_SEPARATE,
1162 },
1163 IIO_ENUM("sys_calibration_mode", IIO_SEPARATE,
1164 &ad7124_syscalib_mode_enum),
1165 IIO_ENUM_AVAILABLE("sys_calibration_mode", IIO_SHARED_BY_TYPE,
1166 &ad7124_syscalib_mode_enum),
1167 IIO_ENUM("filter_type", IIO_SEPARATE, &ad7124_filter_type_enum),
1168 IIO_ENUM_AVAILABLE("filter_type", IIO_SHARED_BY_TYPE,
1169 &ad7124_filter_type_enum),
1170 { }
1171 };
1172
1173 static const struct iio_chan_spec ad7124_channel_template = {
1174 .type = IIO_VOLTAGE,
1175 .indexed = 1,
1176 .differential = 1,
1177 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1178 BIT(IIO_CHAN_INFO_SCALE) |
1179 BIT(IIO_CHAN_INFO_OFFSET) |
1180 BIT(IIO_CHAN_INFO_SAMP_FREQ) |
1181 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),
1182 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE),
1183 .scan_type = {
1184 .sign = 'u',
1185 .realbits = 24,
1186 .storagebits = 32,
1187 .endianness = IIO_BE,
1188 },
1189 .ext_info = ad7124_calibsys_ext_info,
1190 };
1191
1192 /*
1193 * Input specifiers 8 - 15 are explicitly reserved for ad7124-4
1194 * while they are fine for ad7124-8. Values above 31 don't fit
1195 * into the register field and so are invalid for sure.
1196 */
ad7124_valid_input_select(unsigned int ain,const struct ad7124_chip_info * info)1197 static bool ad7124_valid_input_select(unsigned int ain, const struct ad7124_chip_info *info)
1198 {
1199 if (ain >= info->num_inputs && ain < 16)
1200 return false;
1201
1202 return ain <= FIELD_MAX(AD7124_CHANNEL_AINM);
1203 }
1204
ad7124_parse_channel_config(struct iio_dev * indio_dev,struct device * dev)1205 static int ad7124_parse_channel_config(struct iio_dev *indio_dev,
1206 struct device *dev)
1207 {
1208 struct ad7124_state *st = iio_priv(indio_dev);
1209 struct ad7124_channel_config *cfg;
1210 struct ad7124_channel *channels;
1211 struct iio_chan_spec *chan;
1212 unsigned int ain[2], channel = 0, tmp;
1213 unsigned int num_channels;
1214 int ret;
1215
1216 num_channels = device_get_child_node_count(dev);
1217
1218 /*
1219 * The driver assigns each logical channel defined in the device tree
1220 * statically one channel register. So only accept 16 such logical
1221 * channels to not treat CONFIG_0 (i.e. the register following
1222 * CHANNEL_15) as an additional channel register. The driver could be
1223 * improved to lift this limitation.
1224 */
1225 if (num_channels > AD7124_MAX_CHANNELS)
1226 return dev_err_probe(dev, -EINVAL, "Too many channels defined\n");
1227
1228 /* Add one for temperature */
1229 st->num_channels = min(num_channels + 1, AD7124_MAX_CHANNELS);
1230
1231 chan = devm_kcalloc(dev, st->num_channels,
1232 sizeof(*chan), GFP_KERNEL);
1233 if (!chan)
1234 return -ENOMEM;
1235
1236 channels = devm_kcalloc(dev, st->num_channels, sizeof(*channels),
1237 GFP_KERNEL);
1238 if (!channels)
1239 return -ENOMEM;
1240
1241 indio_dev->channels = chan;
1242 indio_dev->num_channels = st->num_channels;
1243 st->channels = channels;
1244
1245 device_for_each_child_node_scoped(dev, child) {
1246 ret = fwnode_property_read_u32(child, "reg", &channel);
1247 if (ret)
1248 return dev_err_probe(dev, ret,
1249 "Failed to parse reg property of %pfwP\n", child);
1250
1251 if (channel >= num_channels)
1252 return dev_err_probe(dev, -EINVAL,
1253 "Channel index >= number of channels in %pfwP\n", child);
1254
1255 ret = fwnode_property_read_u32_array(child, "diff-channels",
1256 ain, 2);
1257 if (ret)
1258 return dev_err_probe(dev, ret,
1259 "Failed to parse diff-channels property of %pfwP\n", child);
1260
1261 if (!ad7124_valid_input_select(ain[0], st->chip_info) ||
1262 !ad7124_valid_input_select(ain[1], st->chip_info))
1263 return dev_err_probe(dev, -EINVAL,
1264 "diff-channels property of %pfwP contains invalid data\n", child);
1265
1266 st->channels[channel].ain = FIELD_PREP(AD7124_CHANNEL_AINP, ain[0]) |
1267 FIELD_PREP(AD7124_CHANNEL_AINM, ain[1]);
1268
1269 cfg = &st->channels[channel].cfg;
1270 cfg->bipolar = fwnode_property_read_bool(child, "bipolar");
1271
1272 ret = fwnode_property_read_u32(child, "adi,reference-select", &tmp);
1273 if (ret)
1274 cfg->refsel = AD7124_INT_REF;
1275 else
1276 cfg->refsel = tmp;
1277
1278 cfg->buf_positive =
1279 fwnode_property_read_bool(child, "adi,buffered-positive");
1280 cfg->buf_negative =
1281 fwnode_property_read_bool(child, "adi,buffered-negative");
1282
1283 chan[channel] = ad7124_channel_template;
1284 chan[channel].address = channel;
1285 chan[channel].scan_index = channel;
1286 chan[channel].channel = ain[0];
1287 chan[channel].channel2 = ain[1];
1288 }
1289
1290 if (num_channels < AD7124_MAX_CHANNELS) {
1291 st->channels[num_channels] = (struct ad7124_channel) {
1292 .ain = FIELD_PREP(AD7124_CHANNEL_AINP, AD7124_CHANNEL_AINx_TEMPSENSOR) |
1293 FIELD_PREP(AD7124_CHANNEL_AINM, AD7124_CHANNEL_AINx_AVSS),
1294 .cfg = {
1295 .bipolar = true,
1296 },
1297 };
1298
1299 chan[num_channels] = (struct iio_chan_spec) {
1300 .type = IIO_TEMP,
1301 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1302 BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_OFFSET) |
1303 BIT(IIO_CHAN_INFO_SAMP_FREQ),
1304 .scan_type = {
1305 /*
1306 * You might find it strange that a bipolar
1307 * measurement yields an unsigned value, but
1308 * this matches the device's manual.
1309 */
1310 .sign = 'u',
1311 .realbits = 24,
1312 .storagebits = 32,
1313 .endianness = IIO_BE,
1314 },
1315 .address = num_channels,
1316 .scan_index = num_channels,
1317 .ext_info = ad7124_calibsys_ext_info,
1318 };
1319 }
1320
1321 return 0;
1322 }
1323
ad7124_setup(struct ad7124_state * st)1324 static int ad7124_setup(struct ad7124_state *st)
1325 {
1326 struct device *dev = &st->sd.spi->dev;
1327 unsigned int power_mode, clk_sel;
1328 struct clk *mclk;
1329 int i, ret;
1330
1331 /*
1332 * Always use full power mode for max performance. If needed, the driver
1333 * could be adapted to use a dynamic power mode based on the requested
1334 * output data rate.
1335 */
1336 power_mode = AD7124_ADC_CONTROL_POWER_MODE_FULL;
1337
1338 /*
1339 * This "mclk" business is needed for backwards compatibility with old
1340 * devicetrees that specified a fake clock named "mclk" to select the
1341 * power mode.
1342 */
1343 mclk = devm_clk_get_optional_enabled(dev, "mclk");
1344 if (IS_ERR(mclk))
1345 return dev_err_probe(dev, PTR_ERR(mclk), "Failed to get mclk\n");
1346
1347 if (mclk) {
1348 unsigned long mclk_hz;
1349
1350 mclk_hz = clk_get_rate(mclk);
1351 if (!mclk_hz)
1352 return dev_err_probe(dev, -EINVAL,
1353 "Failed to get mclk rate\n");
1354
1355 /*
1356 * This logic is a bit backwards, which is why it is only here
1357 * for backwards compatibility. The driver should be able to set
1358 * the power mode as it sees fit and the f_clk/mclk rate should
1359 * be dynamic accordingly. But here, we are selecting a fixed
1360 * power mode based on the given "mclk" rate.
1361 */
1362 power_mode = ad7124_find_closest_match(ad7124_master_clk_freq_hz,
1363 ARRAY_SIZE(ad7124_master_clk_freq_hz), mclk_hz);
1364
1365 if (mclk_hz != ad7124_master_clk_freq_hz[power_mode]) {
1366 ret = clk_set_rate(mclk, mclk_hz);
1367 if (ret)
1368 return dev_err_probe(dev, ret,
1369 "Failed to set mclk rate\n");
1370 }
1371
1372 clk_sel = AD7124_ADC_CONTROL_CLK_SEL_INT;
1373 st->clk_hz = AD7124_INT_CLK_HZ;
1374 } else if (!device_property_present(dev, "clocks") &&
1375 device_property_present(dev, "#clock-cells")) {
1376 #ifdef CONFIG_COMMON_CLK
1377 struct clk_hw *clk_hw;
1378
1379 const char *name __free(kfree) = kasprintf(GFP_KERNEL, "%pfwP-clk",
1380 dev_fwnode(dev));
1381 if (!name)
1382 return -ENOMEM;
1383
1384 clk_hw = devm_clk_hw_register_fixed_rate(dev, name, NULL, 0,
1385 AD7124_INT_CLK_HZ);
1386 if (IS_ERR(clk_hw))
1387 return dev_err_probe(dev, PTR_ERR(clk_hw),
1388 "Failed to register clock provider\n");
1389
1390 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
1391 clk_hw);
1392 if (ret)
1393 return dev_err_probe(dev, ret,
1394 "Failed to add clock provider\n");
1395 #endif
1396
1397 /*
1398 * Treat the clock as always on. This way we don't have to deal
1399 * with someone trying to enable/disable the clock while we are
1400 * reading samples.
1401 */
1402 clk_sel = AD7124_ADC_CONTROL_CLK_SEL_INT_OUT;
1403 st->clk_hz = AD7124_INT_CLK_HZ;
1404 } else {
1405 struct clk *clk;
1406
1407 clk = devm_clk_get_optional_enabled(dev, NULL);
1408 if (IS_ERR(clk))
1409 return dev_err_probe(dev, PTR_ERR(clk),
1410 "Failed to get external clock\n");
1411
1412 if (clk) {
1413 unsigned long clk_hz;
1414
1415 clk_hz = clk_get_rate(clk);
1416 if (!clk_hz)
1417 return dev_err_probe(dev, -EINVAL,
1418 "Failed to get external clock rate\n");
1419
1420 /*
1421 * The external clock may be 4x the nominal clock rate,
1422 * in which case the ADC needs to be configured to
1423 * divide it by 4. Using MEGA is a bit arbitrary, but
1424 * the expected clock rates are either 614.4 kHz or
1425 * 2.4576 MHz, so this should work.
1426 */
1427 if (clk_hz > (1 * HZ_PER_MHZ)) {
1428 clk_sel = AD7124_ADC_CONTROL_CLK_SEL_EXT_DIV4;
1429 st->clk_hz = clk_hz / 4;
1430 } else {
1431 clk_sel = AD7124_ADC_CONTROL_CLK_SEL_EXT;
1432 st->clk_hz = clk_hz;
1433 }
1434 } else {
1435 clk_sel = AD7124_ADC_CONTROL_CLK_SEL_INT;
1436 st->clk_hz = AD7124_INT_CLK_HZ;
1437 }
1438 }
1439
1440 st->adc_control &= ~AD7124_ADC_CONTROL_CLK_SEL;
1441 st->adc_control |= FIELD_PREP(AD7124_ADC_CONTROL_CLK_SEL, clk_sel);
1442
1443 st->adc_control &= ~AD7124_ADC_CONTROL_POWER_MODE;
1444 st->adc_control |= FIELD_PREP(AD7124_ADC_CONTROL_POWER_MODE, power_mode);
1445
1446 st->adc_control &= ~AD7124_ADC_CONTROL_MODE;
1447 st->adc_control |= FIELD_PREP(AD7124_ADC_CONTROL_MODE, AD_SD_MODE_IDLE);
1448
1449 ret = devm_mutex_init(dev, &st->cfgs_lock);
1450 if (ret)
1451 return ret;
1452
1453 for (i = 0; i < st->num_channels; i++) {
1454 struct ad7124_channel_config *cfg = &st->channels[i].cfg;
1455
1456 ret = ad7124_init_config_vref(st, cfg);
1457 if (ret < 0)
1458 return ret;
1459
1460 cfg->cfg_slot = AD7124_CFG_SLOT_UNASSIGNED;
1461
1462 /* Default filter type on the ADC after reset. */
1463 cfg->filter_type = AD7124_FILTER_TYPE_SINC4;
1464
1465 /*
1466 * 9.38 SPS is the minimum output data rate supported
1467 * regardless of the selected power mode. Round it up to 10 and
1468 * set all channels to this default value.
1469 */
1470 cfg->requested_odr = 10;
1471 ad7124_set_channel_odr(st, i);
1472 }
1473
1474 ad7124_disable_all(&st->sd);
1475
1476 ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
1477 if (ret < 0)
1478 return dev_err_probe(dev, ret, "Failed to setup CONTROL register\n");
1479
1480 return ret;
1481 }
1482
__ad7124_calibrate_all(struct ad7124_state * st,struct iio_dev * indio_dev)1483 static int __ad7124_calibrate_all(struct ad7124_state *st, struct iio_dev *indio_dev)
1484 {
1485 struct device *dev = &st->sd.spi->dev;
1486 int ret, i;
1487
1488 for (i = 0; i < st->num_channels; i++) {
1489 /*
1490 * For calibration the OFFSET register should hold its reset default
1491 * value. For the GAIN register there is no such requirement but
1492 * for gain 1 it should hold the reset default value, too. So to
1493 * simplify matters use the reset default value for both.
1494 */
1495 st->channels[i].cfg.calibration_offset = 0x800000;
1496 st->channels[i].cfg.calibration_gain = st->gain_default;
1497
1498 /*
1499 * Only the main voltage input channels are important enough
1500 * to be automatically calibrated here. For everything else,
1501 * just use the default values set above.
1502 */
1503 if (indio_dev->channels[i].type != IIO_VOLTAGE)
1504 continue;
1505
1506 /*
1507 * Full-scale calibration isn't supported at gain 1, so skip in
1508 * that case. Note that untypically full-scale calibration has
1509 * to happen before zero-scale calibration. This only applies to
1510 * the internal calibration. For system calibration it's as
1511 * usual: first zero-scale then full-scale calibration.
1512 */
1513 if (st->channels[i].cfg.pga_bits > 0) {
1514 ret = ad_sd_calibrate(&st->sd, AD7124_ADC_CONTROL_MODE_INT_GAIN_CALIB, i);
1515 if (ret < 0)
1516 return ret;
1517
1518 /*
1519 * read out the resulting value of GAIN
1520 * after full-scale calibration because the next
1521 * ad_sd_calibrate() call overwrites this via
1522 * ad_sigma_delta_set_channel() -> ad7124_set_channel()
1523 * -> ad7124_prepare_read().
1524 */
1525 ret = ad_sd_read_reg(&st->sd, AD7124_GAIN(0), 3,
1526 &st->channels[i].cfg.calibration_gain);
1527 if (ret < 0)
1528 return ret;
1529 }
1530
1531 ret = ad_sd_calibrate(&st->sd, AD7124_ADC_CONTROL_MODE_INT_OFFSET_CALIB, i);
1532 if (ret < 0)
1533 return ret;
1534
1535 /*
1536 * Making the assumption that a single conversion will always
1537 * use configuration slot 0 for the OFFSET/GAIN registers.
1538 */
1539 ret = ad_sd_read_reg(&st->sd, AD7124_OFFSET(0), 3,
1540 &st->channels[i].cfg.calibration_offset);
1541 if (ret < 0)
1542 return ret;
1543
1544 dev_dbg(dev, "offset and gain for channel %d = 0x%x + 0x%x\n", i,
1545 st->channels[i].cfg.calibration_offset,
1546 st->channels[i].cfg.calibration_gain);
1547 }
1548
1549 return 0;
1550 }
1551
ad7124_calibrate_all(struct ad7124_state * st,struct iio_dev * indio_dev)1552 static int ad7124_calibrate_all(struct ad7124_state *st, struct iio_dev *indio_dev)
1553 {
1554 int ret;
1555 unsigned int adc_control = st->adc_control;
1556
1557 /*
1558 * Calibration isn't supported at full power, so speed down a bit.
1559 * Setting .adc_control is enough here because the control register is
1560 * written as part of ad_sd_calibrate() -> ad_sigma_delta_set_mode().
1561 * The resulting calibration is then also valid for high-speed, so just
1562 * restore adc_control afterwards.
1563 */
1564 if (FIELD_GET(AD7124_ADC_CONTROL_POWER_MODE, adc_control) >= AD7124_FULL_POWER) {
1565 st->adc_control &= ~AD7124_ADC_CONTROL_POWER_MODE;
1566 st->adc_control |= FIELD_PREP(AD7124_ADC_CONTROL_POWER_MODE, AD7124_MID_POWER);
1567 }
1568
1569 ret = __ad7124_calibrate_all(st, indio_dev);
1570
1571 st->adc_control = adc_control;
1572
1573 return ret;
1574 }
1575
ad7124_reg_disable(void * r)1576 static void ad7124_reg_disable(void *r)
1577 {
1578 regulator_disable(r);
1579 }
1580
ad7124_debugfs_init(struct iio_dev * indio_dev)1581 static void ad7124_debugfs_init(struct iio_dev *indio_dev)
1582 {
1583 struct dentry *dentry = iio_get_debugfs_dentry(indio_dev);
1584 struct ad7124_state *st = iio_priv(indio_dev);
1585
1586 if (!IS_ENABLED(CONFIG_DEBUG_FS))
1587 return;
1588
1589 debugfs_create_bool("enable_single_cycle", 0644, dentry,
1590 &st->enable_single_cycle);
1591 }
1592
ad7124_probe(struct spi_device * spi)1593 static int ad7124_probe(struct spi_device *spi)
1594 {
1595 const struct ad7124_chip_info *info;
1596 struct device *dev = &spi->dev;
1597 struct ad7124_state *st;
1598 struct iio_dev *indio_dev;
1599 int i, ret;
1600
1601 info = spi_get_device_match_data(spi);
1602 if (!info)
1603 return dev_err_probe(dev, -ENODEV, "Failed to get match data\n");
1604
1605 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
1606 if (!indio_dev)
1607 return -ENOMEM;
1608
1609 st = iio_priv(indio_dev);
1610
1611 st->chip_info = info;
1612
1613 /* Only disabled for debug/testing purposes. */
1614 st->enable_single_cycle = true;
1615
1616 indio_dev->name = st->chip_info->name;
1617 indio_dev->modes = INDIO_DIRECT_MODE;
1618 indio_dev->info = &ad7124_info;
1619
1620 ret = ad_sd_init(&st->sd, indio_dev, spi, &ad7124_sigma_delta_info);
1621 if (ret < 0)
1622 return ret;
1623
1624 ret = ad7124_parse_channel_config(indio_dev, &spi->dev);
1625 if (ret < 0)
1626 return ret;
1627
1628 for (i = 0; i < ARRAY_SIZE(st->vref); i++) {
1629 if (i == AD7124_INT_REF)
1630 continue;
1631
1632 st->vref[i] = devm_regulator_get_optional(&spi->dev,
1633 ad7124_ref_names[i]);
1634 if (PTR_ERR(st->vref[i]) == -ENODEV)
1635 continue;
1636 else if (IS_ERR(st->vref[i]))
1637 return PTR_ERR(st->vref[i]);
1638
1639 ret = regulator_enable(st->vref[i]);
1640 if (ret)
1641 return dev_err_probe(dev, ret, "Failed to enable regulator #%d\n", i);
1642
1643 ret = devm_add_action_or_reset(&spi->dev, ad7124_reg_disable,
1644 st->vref[i]);
1645 if (ret)
1646 return ret;
1647 }
1648
1649 ret = ad7124_soft_reset(st);
1650 if (ret < 0)
1651 return ret;
1652
1653 ret = ad7124_check_chip_id(st);
1654 if (ret)
1655 return ret;
1656
1657 ret = ad7124_setup(st);
1658 if (ret < 0)
1659 return ret;
1660
1661 ret = devm_ad_sd_setup_buffer_and_trigger(&spi->dev, indio_dev);
1662 if (ret < 0)
1663 return dev_err_probe(dev, ret, "Failed to setup triggers\n");
1664
1665 ret = ad7124_calibrate_all(st, indio_dev);
1666 if (ret)
1667 return ret;
1668
1669 ret = devm_iio_device_register(&spi->dev, indio_dev);
1670 if (ret < 0)
1671 return dev_err_probe(dev, ret, "Failed to register iio device\n");
1672
1673 ad7124_debugfs_init(indio_dev);
1674
1675 return 0;
1676 }
1677
1678 static const struct of_device_id ad7124_of_match[] = {
1679 { .compatible = "adi,ad7124-4", .data = &ad7124_4_chip_info },
1680 { .compatible = "adi,ad7124-8", .data = &ad7124_8_chip_info },
1681 { }
1682 };
1683 MODULE_DEVICE_TABLE(of, ad7124_of_match);
1684
1685 static const struct spi_device_id ad71124_ids[] = {
1686 { .name = "ad7124-4", .driver_data = (kernel_ulong_t)&ad7124_4_chip_info },
1687 { .name = "ad7124-8", .driver_data = (kernel_ulong_t)&ad7124_8_chip_info },
1688 { }
1689 };
1690 MODULE_DEVICE_TABLE(spi, ad71124_ids);
1691
1692 static struct spi_driver ad71124_driver = {
1693 .driver = {
1694 .name = "ad7124",
1695 .of_match_table = ad7124_of_match,
1696 },
1697 .probe = ad7124_probe,
1698 .id_table = ad71124_ids,
1699 };
1700 module_spi_driver(ad71124_driver);
1701
1702 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");
1703 MODULE_DESCRIPTION("Analog Devices AD7124 SPI driver");
1704 MODULE_LICENSE("GPL");
1705 MODULE_IMPORT_NS("IIO_AD_SIGMA_DELTA");
1706