1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Analog Devices AD4080 SPI ADC driver
4 *
5 * Copyright 2025 Analog Devices Inc.
6 */
7
8 #include <linux/array_size.h>
9 #include <linux/bitfield.h>
10 #include <linux/bits.h>
11 #include <linux/clk.h>
12 #include <linux/device.h>
13 #include <linux/err.h>
14 #include <linux/iio/backend.h>
15 #include <linux/iio/iio.h>
16 #include <linux/module.h>
17 #include <linux/mutex.h>
18 #include <linux/property.h>
19 #include <linux/regmap.h>
20 #include <linux/regulator/consumer.h>
21 #include <linux/spi/spi.h>
22 #include <linux/types.h>
23 #include <linux/unaligned.h>
24 #include <linux/units.h>
25
26 /* Register Definition */
27 #define AD4080_REG_INTERFACE_CONFIG_A 0x00
28 #define AD4080_REG_INTERFACE_CONFIG_B 0x01
29 #define AD4080_REG_DEVICE_CONFIG 0x02
30 #define AD4080_REG_CHIP_TYPE 0x03
31 #define AD4080_REG_PRODUCT_ID_L 0x04
32 #define AD4080_REG_PRODUCT_ID_H 0x05
33 #define AD4080_REG_CHIP_GRADE 0x06
34 #define AD4080_REG_SCRATCH_PAD 0x0A
35 #define AD4080_REG_SPI_REVISION 0x0B
36 #define AD4080_REG_VENDOR_L 0x0C
37 #define AD4080_REG_VENDOR_H 0x0D
38 #define AD4080_REG_STREAM_MODE 0x0E
39 #define AD4080_REG_TRANSFER_CONFIG 0x0F
40 #define AD4080_REG_INTERFACE_CONFIG_C 0x10
41 #define AD4080_REG_INTERFACE_STATUS_A 0x11
42 #define AD4080_REG_DEVICE_STATUS 0x14
43 #define AD4080_REG_ADC_DATA_INTF_CONFIG_A 0x15
44 #define AD4080_REG_ADC_DATA_INTF_CONFIG_B 0x16
45 #define AD4080_REG_ADC_DATA_INTF_CONFIG_C 0x17
46 #define AD4080_REG_PWR_CTRL 0x18
47 #define AD4080_REG_GPIO_CONFIG_A 0x19
48 #define AD4080_REG_GPIO_CONFIG_B 0x1A
49 #define AD4080_REG_GPIO_CONFIG_C 0x1B
50 #define AD4080_REG_GENERAL_CONFIG 0x1C
51 #define AD4080_REG_FIFO_WATERMARK_LSB 0x1D
52 #define AD4080_REG_FIFO_WATERMARK_MSB 0x1E
53 #define AD4080_REG_EVENT_HYSTERESIS_LSB 0x1F
54 #define AD4080_REG_EVENT_HYSTERESIS_MSB 0x20
55 #define AD4080_REG_EVENT_DETECTION_HI_LSB 0x21
56 #define AD4080_REG_EVENT_DETECTION_HI_MSB 0x22
57 #define AD4080_REG_EVENT_DETECTION_LO_LSB 0x23
58 #define AD4080_REG_EVENT_DETECTION_LO_MSB 0x24
59 #define AD4080_REG_OFFSET_LSB 0x25
60 #define AD4080_REG_OFFSET_MSB 0x26
61 #define AD4080_REG_GAIN_LSB 0x27
62 #define AD4080_REG_GAIN_MSB 0x28
63 #define AD4080_REG_FILTER_CONFIG 0x29
64
65 /* AD4080_REG_INTERFACE_CONFIG_A Bit Definition */
66 #define AD4080_INTERFACE_CONFIG_A_SW_RESET (BIT(7) | BIT(0))
67 #define AD4080_INTERFACE_CONFIG_A_ADDR_ASC BIT(5)
68 #define AD4080_INTERFACE_CONFIG_A_SDO_ENABLE BIT(4)
69
70 /* AD4080_REG_INTERFACE_CONFIG_B Bit Definition */
71 #define AD4080_INTERFACE_CONFIG_B_SINGLE_INST BIT(7)
72 #define AD4080_INTERFACE_CONFIG_B_SHORT_INST BIT(3)
73
74 /* AD4080_REG_DEVICE_CONFIG Bit Definition */
75 #define AD4080_DEVICE_CONFIG_OPERATING_MODES_MSK GENMASK(1, 0)
76
77 /* AD4080_REG_TRANSFER_CONFIG Bit Definition */
78 #define AD4080_TRANSFER_CONFIG_KEEP_STREAM_LENGTH_VAL BIT(2)
79
80 /* AD4080_REG_INTERFACE_CONFIG_C Bit Definition */
81 #define AD4080_INTERFACE_CONFIG_C_STRICT_REG_ACCESS BIT(5)
82
83 /* AD4080_REG_ADC_DATA_INTF_CONFIG_A Bit Definition */
84 #define AD4080_ADC_DATA_INTF_CONFIG_A_RESERVED_CONFIG_A BIT(6)
85 #define AD4080_ADC_DATA_INTF_CONFIG_A_INTF_CHK_EN BIT(4)
86 #define AD4080_ADC_DATA_INTF_CONFIG_A_SPI_LVDS_LANES BIT(2)
87 #define AD4080_ADC_DATA_INTF_CONFIG_A_DATA_INTF_MODE BIT(0)
88
89 /* AD4080_REG_ADC_DATA_INTF_CONFIG_B Bit Definition */
90 #define AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_CLK_CNT_MSK GENMASK(7, 4)
91 #define AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_SELF_CLK_MODE BIT(3)
92 #define AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_EN BIT(0)
93
94 /* AD4080_REG_ADC_DATA_INTF_CONFIG_C Bit Definition */
95 #define AD4080_ADC_DATA_INTF_CONFIG_C_LVDS_VOD_MSK GENMASK(6, 4)
96
97 /* AD4080_REG_PWR_CTRL Bit Definition */
98 #define AD4080_PWR_CTRL_ANA_DIG_LDO_PD BIT(1)
99 #define AD4080_PWR_CTRL_INTF_LDO_PD BIT(0)
100
101 /* AD4080_REG_GPIO_CONFIG_A Bit Definition */
102 #define AD4080_GPIO_CONFIG_A_GPO_1_EN BIT(1)
103 #define AD4080_GPIO_CONFIG_A_GPO_0_EN BIT(0)
104
105 /* AD4080_REG_GPIO_CONFIG_B Bit Definition */
106 #define AD4080_GPIO_CONFIG_B_GPIO_1_SEL_MSK GENMASK(7, 4)
107 #define AD4080_GPIO_CONFIG_B_GPIO_0_SEL_MSK GENMASK(3, 0)
108 #define AD4080_GPIO_CONFIG_B_GPIO_SPI_SDO 0
109 #define AD4080_GPIO_CONFIG_B_GPIO_FIFO_FULL 1
110 #define AD4080_GPIO_CONFIG_B_GPIO_FIFO_READ_DONE 2
111 #define AD4080_GPIO_CONFIG_B_GPIO_FILTER_RES_RDY 3
112 #define AD4080_GPIO_CONFIG_B_GPIO_H_THRESH 4
113 #define AD4080_GPIO_CONFIG_B_GPIO_L_THRESH 5
114 #define AD4080_GPIO_CONFIG_B_GPIO_STATUS_ALERT 6
115 #define AD4080_GPIO_CONFIG_B_GPIO_GPIO_DATA 7
116 #define AD4080_GPIO_CONFIG_B_GPIO_FILTER_SYNC 8
117 #define AD4080_GPIO_CONFIG_B_GPIO_EXTERNAL_EVENT 9
118
119 /* AD4080_REG_FIFO_CONFIG Bit Definition */
120 #define AD4080_FIFO_CONFIG_FIFO_MODE_MSK GENMASK(1, 0)
121
122 /* AD4080_REG_FILTER_CONFIG Bit Definition */
123 #define AD4080_FILTER_CONFIG_SINC_DEC_RATE_MSK GENMASK(6, 3)
124 #define AD4080_FILTER_CONFIG_FILTER_SEL_MSK GENMASK(1, 0)
125
126 /* Miscellaneous Definitions */
127 #define AD4080_SPI_READ BIT(7)
128 #define AD4080_CHIP_ID 0x0050
129 #define AD4081_CHIP_ID 0x0051
130 #define AD4082_CHIP_ID 0x0052
131 #define AD4083_CHIP_ID 0x0053
132 #define AD4084_CHIP_ID 0x0054
133 #define AD4085_CHIP_ID 0x0055
134 #define AD4086_CHIP_ID 0x0056
135 #define AD4087_CHIP_ID 0x0057
136 #define AD4088_CHIP_ID 0x0058
137 #define AD4880_CHIP_ID 0x0059
138 #define AD4883_CHIP_ID 0x005B
139 #define AD4884_CHIP_ID 0x005C
140
141 #define AD4080_MAX_CHANNELS 2
142
143 #define AD4080_LVDS_CNV_CLK_CNT_MAX 7
144
145 #define AD4080_MAX_SAMP_FREQ 40000000
146 #define AD4080_MIN_SAMP_FREQ 1250000
147
148 enum ad4080_filter_type {
149 FILTER_NONE,
150 SINC_1,
151 SINC_5,
152 SINC_5_COMP
153 };
154
155 static const unsigned int ad4080_scale_table[][2] = {
156 { 6000, 0 },
157 };
158
159 static const char *const ad4080_filter_type_iio_enum[] = {
160 [FILTER_NONE] = "none",
161 [SINC_1] = "sinc1",
162 [SINC_5] = "sinc5",
163 [SINC_5_COMP] = "sinc5+pf1",
164 };
165
166 static const int ad4080_dec_rate_avail[] = {
167 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024,
168 };
169
170 static const int ad4080_dec_rate_none[] = { 1 };
171
172 static const char * const ad4080_power_supplies[] = {
173 "vdd33", "vdd11", "vddldo", "iovdd", "vrefin",
174 };
175
176 struct ad4080_chip_info {
177 const char *name;
178 unsigned int product_id;
179 int num_scales;
180 const unsigned int (*scale_table)[2];
181 const struct iio_chan_spec *channels;
182 unsigned int num_channels;
183 unsigned int lvds_cnv_clk_cnt_max;
184 };
185
186 struct ad4080_state {
187 struct spi_device *spi[AD4080_MAX_CHANNELS];
188 struct regmap *regmap[AD4080_MAX_CHANNELS];
189 struct iio_backend *back[AD4080_MAX_CHANNELS];
190 const struct ad4080_chip_info *info;
191 /*
192 * Synchronize access to members the of driver state, and ensure
193 * atomicity of consecutive regmap operations.
194 */
195 struct mutex lock;
196 unsigned int num_lanes;
197 unsigned long clk_rate;
198 enum ad4080_filter_type filter_type[AD4080_MAX_CHANNELS];
199 bool lvds_cnv_en;
200 };
201
202 static const struct regmap_config ad4080_regmap_config = {
203 .reg_bits = 16,
204 .val_bits = 8,
205 .read_flag_mask = BIT(7),
206 .max_register = 0x29,
207 };
208
ad4080_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)209 static int ad4080_reg_access(struct iio_dev *indio_dev, unsigned int reg,
210 unsigned int writeval, unsigned int *readval)
211 {
212 struct ad4080_state *st = iio_priv(indio_dev);
213
214 if (readval)
215 return regmap_read(st->regmap[0], reg, readval);
216
217 return regmap_write(st->regmap[0], reg, writeval);
218 }
219
ad4080_get_scale(struct ad4080_state * st,int * val,int * val2)220 static int ad4080_get_scale(struct ad4080_state *st, int *val, int *val2)
221 {
222 unsigned int tmp;
223
224 tmp = (st->info->scale_table[0][0] * 1000000ULL) >>
225 st->info->channels[0].scan_type.realbits;
226 *val = tmp / 1000000;
227 *val2 = tmp % 1000000;
228
229 return IIO_VAL_INT_PLUS_NANO;
230 }
231
ad4080_get_dec_rate(struct iio_dev * dev,const struct iio_chan_spec * chan)232 static unsigned int ad4080_get_dec_rate(struct iio_dev *dev,
233 const struct iio_chan_spec *chan)
234 {
235 struct ad4080_state *st = iio_priv(dev);
236 int ret;
237 unsigned int data;
238 unsigned int ch = chan->channel;
239
240 ret = regmap_read(st->regmap[ch], AD4080_REG_FILTER_CONFIG, &data);
241 if (ret)
242 return ret;
243
244 return 1 << (FIELD_GET(AD4080_FILTER_CONFIG_SINC_DEC_RATE_MSK, data) + 1);
245 }
246
ad4080_set_dec_rate(struct iio_dev * dev,const struct iio_chan_spec * chan,unsigned int mode)247 static int ad4080_set_dec_rate(struct iio_dev *dev,
248 const struct iio_chan_spec *chan,
249 unsigned int mode)
250 {
251 struct ad4080_state *st = iio_priv(dev);
252 unsigned int ch = chan->channel;
253
254 guard(mutex)(&st->lock);
255
256 if ((st->filter_type[ch] >= SINC_5 && mode >= 512) || mode < 2)
257 return -EINVAL;
258
259 return regmap_update_bits(st->regmap[ch], AD4080_REG_FILTER_CONFIG,
260 AD4080_FILTER_CONFIG_SINC_DEC_RATE_MSK,
261 FIELD_PREP(AD4080_FILTER_CONFIG_SINC_DEC_RATE_MSK,
262 (ilog2(mode) - 1)));
263 }
264
ad4080_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)265 static int ad4080_read_raw(struct iio_dev *indio_dev,
266 struct iio_chan_spec const *chan,
267 int *val, int *val2, long m)
268 {
269 struct ad4080_state *st = iio_priv(indio_dev);
270 int dec_rate;
271
272 switch (m) {
273 case IIO_CHAN_INFO_SCALE:
274 return ad4080_get_scale(st, val, val2);
275 case IIO_CHAN_INFO_SAMP_FREQ:
276 dec_rate = ad4080_get_dec_rate(indio_dev, chan);
277 if (dec_rate < 0)
278 return dec_rate;
279 if (st->filter_type[chan->channel] == SINC_5_COMP)
280 dec_rate *= 2;
281 if (st->filter_type[chan->channel])
282 *val = DIV_ROUND_CLOSEST(st->clk_rate, dec_rate);
283 else
284 *val = st->clk_rate;
285 return IIO_VAL_INT;
286 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
287 if (st->filter_type[chan->channel] == FILTER_NONE) {
288 *val = 1;
289 } else {
290 *val = ad4080_get_dec_rate(indio_dev, chan);
291 if (*val < 0)
292 return *val;
293 }
294 return IIO_VAL_INT;
295 default:
296 return -EINVAL;
297 }
298 }
299
ad4080_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)300 static int ad4080_write_raw(struct iio_dev *indio_dev,
301 struct iio_chan_spec const *chan,
302 int val, int val2, long mask)
303 {
304 struct ad4080_state *st = iio_priv(indio_dev);
305
306 switch (mask) {
307 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
308 if (st->filter_type[chan->channel] == FILTER_NONE && val > 1)
309 return -EINVAL;
310
311 return ad4080_set_dec_rate(indio_dev, chan, val);
312 default:
313 return -EINVAL;
314 }
315 }
316
ad4080_lvds_sync_write(struct ad4080_state * st,unsigned int ch)317 static int ad4080_lvds_sync_write(struct ad4080_state *st, unsigned int ch)
318 {
319 struct device *dev = regmap_get_device(st->regmap[ch]);
320 int ret;
321
322 ret = regmap_set_bits(st->regmap[ch], AD4080_REG_ADC_DATA_INTF_CONFIG_A,
323 AD4080_ADC_DATA_INTF_CONFIG_A_INTF_CHK_EN);
324 if (ret)
325 return ret;
326
327 ret = iio_backend_interface_data_align(st->back[ch], 10000);
328 if (ret)
329 return dev_err_probe(dev, ret,
330 "Data alignment process failed\n");
331
332 dev_dbg(dev, "Success: Pattern correct and Locked!\n");
333 return regmap_clear_bits(st->regmap[ch], AD4080_REG_ADC_DATA_INTF_CONFIG_A,
334 AD4080_ADC_DATA_INTF_CONFIG_A_INTF_CHK_EN);
335 }
336
ad4080_get_filter_type(struct iio_dev * dev,const struct iio_chan_spec * chan)337 static int ad4080_get_filter_type(struct iio_dev *dev,
338 const struct iio_chan_spec *chan)
339 {
340 struct ad4080_state *st = iio_priv(dev);
341 unsigned int data;
342 unsigned int ch = chan->channel;
343 int ret;
344
345 ret = regmap_read(st->regmap[ch], AD4080_REG_FILTER_CONFIG, &data);
346 if (ret)
347 return ret;
348
349 return FIELD_GET(AD4080_FILTER_CONFIG_FILTER_SEL_MSK, data);
350 }
351
ad4080_set_filter_type(struct iio_dev * dev,const struct iio_chan_spec * chan,unsigned int mode)352 static int ad4080_set_filter_type(struct iio_dev *dev,
353 const struct iio_chan_spec *chan,
354 unsigned int mode)
355 {
356 struct ad4080_state *st = iio_priv(dev);
357 unsigned int ch = chan->channel;
358 int dec_rate;
359 int ret;
360
361 guard(mutex)(&st->lock);
362
363 dec_rate = ad4080_get_dec_rate(dev, chan);
364 if (dec_rate < 0)
365 return dec_rate;
366
367 if (mode >= SINC_5 && dec_rate >= 512)
368 return -EINVAL;
369
370 ret = iio_backend_filter_type_set(st->back[ch], mode);
371 if (ret)
372 return ret;
373
374 ret = regmap_update_bits(st->regmap[ch], AD4080_REG_FILTER_CONFIG,
375 AD4080_FILTER_CONFIG_FILTER_SEL_MSK,
376 FIELD_PREP(AD4080_FILTER_CONFIG_FILTER_SEL_MSK,
377 mode));
378 if (ret)
379 return ret;
380
381 st->filter_type[ch] = mode;
382
383 return 0;
384 }
385
ad4080_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long mask)386 static int ad4080_read_avail(struct iio_dev *indio_dev,
387 struct iio_chan_spec const *chan,
388 const int **vals, int *type, int *length,
389 long mask)
390 {
391 struct ad4080_state *st = iio_priv(indio_dev);
392
393 switch (mask) {
394 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
395 switch (st->filter_type[chan->channel]) {
396 case FILTER_NONE:
397 *vals = ad4080_dec_rate_none;
398 *length = ARRAY_SIZE(ad4080_dec_rate_none);
399 break;
400 default:
401 *vals = ad4080_dec_rate_avail;
402 *length = st->filter_type[chan->channel] >= SINC_5 ?
403 (ARRAY_SIZE(ad4080_dec_rate_avail) - 2) :
404 ARRAY_SIZE(ad4080_dec_rate_avail);
405 break;
406 }
407 *type = IIO_VAL_INT;
408 return IIO_AVAIL_LIST;
409 default:
410 return -EINVAL;
411 }
412 }
413
ad4880_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * scan_mask)414 static int ad4880_update_scan_mode(struct iio_dev *indio_dev,
415 const unsigned long *scan_mask)
416 {
417 struct ad4080_state *st = iio_priv(indio_dev);
418 int ret;
419
420 for (unsigned int ch = 0; ch < st->info->num_channels; ch++) {
421 /*
422 * Each backend has a single channel (channel 0 from the
423 * backend's perspective), so always use channel index 0.
424 */
425 if (test_bit(ch, scan_mask))
426 ret = iio_backend_chan_enable(st->back[ch], 0);
427 else
428 ret = iio_backend_chan_disable(st->back[ch], 0);
429 if (ret)
430 return ret;
431 }
432
433 return 0;
434 }
435
436 static const struct iio_info ad4080_iio_info = {
437 .debugfs_reg_access = ad4080_reg_access,
438 .read_raw = ad4080_read_raw,
439 .write_raw = ad4080_write_raw,
440 .read_avail = ad4080_read_avail,
441 };
442
443 /*
444 * AD4880 needs update_scan_mode to enable/disable individual backend channels.
445 * Single-channel devices don't need this as their backends may not implement
446 * chan_enable/chan_disable operations.
447 */
448 static const struct iio_info ad4880_iio_info = {
449 .debugfs_reg_access = ad4080_reg_access,
450 .read_raw = ad4080_read_raw,
451 .write_raw = ad4080_write_raw,
452 .read_avail = ad4080_read_avail,
453 .update_scan_mode = ad4880_update_scan_mode,
454 };
455
456 static const struct iio_enum ad4080_filter_type_enum = {
457 .items = ad4080_filter_type_iio_enum,
458 .num_items = ARRAY_SIZE(ad4080_filter_type_iio_enum),
459 .set = ad4080_set_filter_type,
460 .get = ad4080_get_filter_type,
461 };
462
463 static struct iio_chan_spec_ext_info ad4080_ext_info[] = {
464 IIO_ENUM("filter_type", IIO_SHARED_BY_ALL, &ad4080_filter_type_enum),
465 IIO_ENUM_AVAILABLE("filter_type", IIO_SHARED_BY_ALL,
466 &ad4080_filter_type_enum),
467 { }
468 };
469
470 /*
471 * AD4880 needs per-channel filter configuration since each channel has
472 * its own independent ADC with separate SPI interface.
473 */
474 static struct iio_chan_spec_ext_info ad4880_ext_info[] = {
475 IIO_ENUM("filter_type", IIO_SEPARATE, &ad4080_filter_type_enum),
476 IIO_ENUM_AVAILABLE("filter_type", IIO_SEPARATE,
477 &ad4080_filter_type_enum),
478 { }
479 };
480
481 #define AD4080_CHANNEL_DEFINE(bits, storage, idx) { \
482 .type = IIO_VOLTAGE, \
483 .indexed = 1, \
484 .channel = (idx), \
485 .info_mask_separate = BIT(IIO_CHAN_INFO_SCALE), \
486 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
487 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
488 .info_mask_shared_by_all_available = \
489 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
490 .ext_info = ad4080_ext_info, \
491 .scan_index = (idx), \
492 .scan_type = { \
493 .sign = 's', \
494 .realbits = (bits), \
495 .storagebits = (storage), \
496 }, \
497 }
498
499 /*
500 * AD4880 has per-channel attributes (filter_type, oversampling_ratio,
501 * sampling_frequency) since each channel has its own independent ADC
502 * with separate SPI configuration interface.
503 */
504 #define AD4880_CHANNEL_DEFINE(bits, storage, idx) { \
505 .type = IIO_VOLTAGE, \
506 .indexed = 1, \
507 .channel = (idx), \
508 .info_mask_separate = BIT(IIO_CHAN_INFO_SCALE) | \
509 BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
510 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
511 .info_mask_separate_available = \
512 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
513 .ext_info = ad4880_ext_info, \
514 .scan_index = (idx), \
515 .scan_type = { \
516 .sign = 's', \
517 .realbits = (bits), \
518 .storagebits = (storage), \
519 }, \
520 }
521
522 static const struct iio_chan_spec ad4080_channel = AD4080_CHANNEL_DEFINE(20, 32, 0);
523
524 static const struct iio_chan_spec ad4081_channel = AD4080_CHANNEL_DEFINE(20, 32, 0);
525
526 static const struct iio_chan_spec ad4082_channel = AD4080_CHANNEL_DEFINE(20, 32, 0);
527
528 static const struct iio_chan_spec ad4083_channel = AD4080_CHANNEL_DEFINE(16, 16, 0);
529
530 static const struct iio_chan_spec ad4084_channel = AD4080_CHANNEL_DEFINE(16, 16, 0);
531
532 static const struct iio_chan_spec ad4085_channel = AD4080_CHANNEL_DEFINE(16, 16, 0);
533
534 static const struct iio_chan_spec ad4086_channel = AD4080_CHANNEL_DEFINE(14, 16, 0);
535
536 static const struct iio_chan_spec ad4087_channel = AD4080_CHANNEL_DEFINE(14, 16, 0);
537
538 static const struct iio_chan_spec ad4088_channel = AD4080_CHANNEL_DEFINE(14, 16, 0);
539
540 static const struct iio_chan_spec ad4880_channels[] = {
541 AD4880_CHANNEL_DEFINE(20, 32, 0),
542 AD4880_CHANNEL_DEFINE(20, 32, 1),
543 };
544
545 static const struct iio_chan_spec ad4883_channels[] = {
546 AD4880_CHANNEL_DEFINE(16, 16, 0),
547 AD4880_CHANNEL_DEFINE(16, 16, 1),
548 };
549
550 static const struct iio_chan_spec ad4884_channels[] = {
551 AD4880_CHANNEL_DEFINE(16, 16, 0),
552 AD4880_CHANNEL_DEFINE(16, 16, 1),
553 };
554
555 static const struct ad4080_chip_info ad4080_chip_info = {
556 .name = "ad4080",
557 .product_id = AD4080_CHIP_ID,
558 .scale_table = ad4080_scale_table,
559 .num_scales = ARRAY_SIZE(ad4080_scale_table),
560 .num_channels = 1,
561 .channels = &ad4080_channel,
562 .lvds_cnv_clk_cnt_max = AD4080_LVDS_CNV_CLK_CNT_MAX,
563 };
564
565 static const struct ad4080_chip_info ad4081_chip_info = {
566 .name = "ad4081",
567 .product_id = AD4081_CHIP_ID,
568 .scale_table = ad4080_scale_table,
569 .num_scales = ARRAY_SIZE(ad4080_scale_table),
570 .num_channels = 1,
571 .channels = &ad4081_channel,
572 .lvds_cnv_clk_cnt_max = 2,
573 };
574
575 static const struct ad4080_chip_info ad4082_chip_info = {
576 .name = "ad4082",
577 .product_id = AD4082_CHIP_ID,
578 .scale_table = ad4080_scale_table,
579 .num_scales = ARRAY_SIZE(ad4080_scale_table),
580 .num_channels = 1,
581 .channels = &ad4082_channel,
582 .lvds_cnv_clk_cnt_max = 8,
583 };
584
585 static const struct ad4080_chip_info ad4083_chip_info = {
586 .name = "ad4083",
587 .product_id = AD4083_CHIP_ID,
588 .scale_table = ad4080_scale_table,
589 .num_scales = ARRAY_SIZE(ad4080_scale_table),
590 .num_channels = 1,
591 .channels = &ad4083_channel,
592 .lvds_cnv_clk_cnt_max = 5,
593 };
594
595 static const struct ad4080_chip_info ad4084_chip_info = {
596 .name = "ad4084",
597 .product_id = AD4084_CHIP_ID,
598 .scale_table = ad4080_scale_table,
599 .num_scales = ARRAY_SIZE(ad4080_scale_table),
600 .num_channels = 1,
601 .channels = &ad4084_channel,
602 .lvds_cnv_clk_cnt_max = 2,
603 };
604
605 static const struct ad4080_chip_info ad4085_chip_info = {
606 .name = "ad4085",
607 .product_id = AD4085_CHIP_ID,
608 .scale_table = ad4080_scale_table,
609 .num_scales = ARRAY_SIZE(ad4080_scale_table),
610 .num_channels = 1,
611 .channels = &ad4085_channel,
612 .lvds_cnv_clk_cnt_max = 8,
613 };
614
615 static const struct ad4080_chip_info ad4086_chip_info = {
616 .name = "ad4086",
617 .product_id = AD4086_CHIP_ID,
618 .scale_table = ad4080_scale_table,
619 .num_scales = ARRAY_SIZE(ad4080_scale_table),
620 .num_channels = 1,
621 .channels = &ad4086_channel,
622 .lvds_cnv_clk_cnt_max = 4,
623 };
624
625 static const struct ad4080_chip_info ad4087_chip_info = {
626 .name = "ad4087",
627 .product_id = AD4087_CHIP_ID,
628 .scale_table = ad4080_scale_table,
629 .num_scales = ARRAY_SIZE(ad4080_scale_table),
630 .num_channels = 1,
631 .channels = &ad4087_channel,
632 .lvds_cnv_clk_cnt_max = 1,
633 };
634
635 static const struct ad4080_chip_info ad4088_chip_info = {
636 .name = "ad4088",
637 .product_id = AD4088_CHIP_ID,
638 .scale_table = ad4080_scale_table,
639 .num_scales = ARRAY_SIZE(ad4080_scale_table),
640 .num_channels = 1,
641 .channels = &ad4088_channel,
642 .lvds_cnv_clk_cnt_max = 8,
643 };
644
645 static const struct ad4080_chip_info ad4880_chip_info = {
646 .name = "ad4880",
647 .product_id = AD4880_CHIP_ID,
648 .scale_table = ad4080_scale_table,
649 .num_scales = ARRAY_SIZE(ad4080_scale_table),
650 .num_channels = 2,
651 .channels = ad4880_channels,
652 .lvds_cnv_clk_cnt_max = AD4080_LVDS_CNV_CLK_CNT_MAX,
653 };
654
655 static const struct ad4080_chip_info ad4883_chip_info = {
656 .name = "ad4883",
657 .product_id = AD4883_CHIP_ID,
658 .scale_table = ad4080_scale_table,
659 .num_scales = ARRAY_SIZE(ad4080_scale_table),
660 .num_channels = 2,
661 .channels = ad4883_channels,
662 .lvds_cnv_clk_cnt_max = 5,
663 };
664
665 static const struct ad4080_chip_info ad4884_chip_info = {
666 .name = "ad4884",
667 .product_id = AD4884_CHIP_ID,
668 .scale_table = ad4080_scale_table,
669 .num_scales = ARRAY_SIZE(ad4080_scale_table),
670 .num_channels = 2,
671 .channels = ad4884_channels,
672 .lvds_cnv_clk_cnt_max = 2,
673 };
674
ad4080_setup_channel(struct ad4080_state * st,unsigned int ch)675 static int ad4080_setup_channel(struct ad4080_state *st, unsigned int ch)
676 {
677 struct device *dev = regmap_get_device(st->regmap[ch]);
678 __le16 id_le;
679 u16 id;
680 int ret;
681
682 ret = regmap_write(st->regmap[ch], AD4080_REG_INTERFACE_CONFIG_A,
683 AD4080_INTERFACE_CONFIG_A_SW_RESET);
684 if (ret)
685 return ret;
686
687 ret = regmap_write(st->regmap[ch], AD4080_REG_INTERFACE_CONFIG_A,
688 AD4080_INTERFACE_CONFIG_A_SDO_ENABLE);
689 if (ret)
690 return ret;
691
692 ret = regmap_bulk_read(st->regmap[ch], AD4080_REG_PRODUCT_ID_L, &id_le,
693 sizeof(id_le));
694 if (ret)
695 return ret;
696
697 id = le16_to_cpu(id_le);
698 if (id != st->info->product_id)
699 dev_info(dev, "Unrecognized CHIP_ID 0x%X\n", id);
700
701 ret = regmap_set_bits(st->regmap[ch], AD4080_REG_GPIO_CONFIG_A,
702 AD4080_GPIO_CONFIG_A_GPO_1_EN);
703 if (ret)
704 return ret;
705
706 ret = regmap_write(st->regmap[ch], AD4080_REG_GPIO_CONFIG_B,
707 FIELD_PREP(AD4080_GPIO_CONFIG_B_GPIO_1_SEL_MSK,
708 AD4080_GPIO_CONFIG_B_GPIO_FILTER_RES_RDY));
709 if (ret)
710 return ret;
711
712 ret = iio_backend_num_lanes_set(st->back[ch], st->num_lanes);
713 if (ret)
714 return ret;
715
716 ret = iio_backend_data_size_set(st->back[ch],
717 st->info->channels[0].scan_type.realbits);
718 if (ret)
719 return ret;
720
721 if (!st->lvds_cnv_en)
722 return 0;
723
724 /* Set maximum LVDS Data Transfer Latency */
725 ret = regmap_update_bits(st->regmap[ch],
726 AD4080_REG_ADC_DATA_INTF_CONFIG_B,
727 AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_CLK_CNT_MSK,
728 FIELD_PREP(AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_CLK_CNT_MSK,
729 st->info->lvds_cnv_clk_cnt_max));
730 if (ret)
731 return ret;
732
733 if (st->num_lanes > 1) {
734 ret = regmap_set_bits(st->regmap[ch], AD4080_REG_ADC_DATA_INTF_CONFIG_A,
735 AD4080_ADC_DATA_INTF_CONFIG_A_SPI_LVDS_LANES);
736 if (ret)
737 return ret;
738 }
739
740 ret = regmap_set_bits(st->regmap[ch],
741 AD4080_REG_ADC_DATA_INTF_CONFIG_B,
742 AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_EN);
743 if (ret)
744 return ret;
745
746 return ad4080_lvds_sync_write(st, ch);
747 }
748
ad4080_setup(struct iio_dev * indio_dev)749 static int ad4080_setup(struct iio_dev *indio_dev)
750 {
751 struct ad4080_state *st = iio_priv(indio_dev);
752 int ret;
753
754 for (unsigned int ch = 0; ch < st->info->num_channels; ch++) {
755 ret = ad4080_setup_channel(st, ch);
756 if (ret)
757 return ret;
758 }
759
760 return 0;
761 }
762
ad4080_properties_parse(struct ad4080_state * st,struct device * dev)763 static int ad4080_properties_parse(struct ad4080_state *st,
764 struct device *dev)
765 {
766
767 st->lvds_cnv_en = device_property_read_bool(dev, "adi,lvds-cnv-enable");
768
769 st->num_lanes = 1;
770 device_property_read_u32(dev, "adi,num-lanes", &st->num_lanes);
771 if (!st->num_lanes || st->num_lanes > 2)
772 return dev_err_probe(dev, -EINVAL,
773 "Invalid 'adi,num-lanes' value: %u",
774 st->num_lanes);
775
776 return 0;
777 }
778
ad4080_probe(struct spi_device * spi)779 static int ad4080_probe(struct spi_device *spi)
780 {
781 struct iio_dev *indio_dev;
782 struct device *dev = &spi->dev;
783 struct ad4080_state *st;
784 struct clk *clk;
785 int ret;
786
787 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
788 if (!indio_dev)
789 return -ENOMEM;
790
791 st = iio_priv(indio_dev);
792
793 ret = devm_regulator_bulk_get_enable(dev,
794 ARRAY_SIZE(ad4080_power_supplies),
795 ad4080_power_supplies);
796 if (ret)
797 return dev_err_probe(dev, ret,
798 "failed to get and enable supplies\n");
799
800 /* Setup primary SPI device (channel 0) */
801 st->spi[0] = spi;
802 st->regmap[0] = devm_regmap_init_spi(spi, &ad4080_regmap_config);
803 if (IS_ERR(st->regmap[0]))
804 return PTR_ERR(st->regmap[0]);
805
806 st->info = spi_get_device_match_data(spi);
807 if (!st->info)
808 return -ENODEV;
809
810 /* Setup ancillary SPI devices for additional channels */
811 for (unsigned int ch = 1; ch < st->info->num_channels; ch++) {
812 st->spi[ch] = devm_spi_new_ancillary_device(spi, spi_get_chipselect(spi, ch));
813 if (IS_ERR(st->spi[ch]))
814 return dev_err_probe(dev, PTR_ERR(st->spi[ch]),
815 "failed to register ancillary device\n");
816
817 st->regmap[ch] = devm_regmap_init_spi(st->spi[ch], &ad4080_regmap_config);
818 if (IS_ERR(st->regmap[ch]))
819 return PTR_ERR(st->regmap[ch]);
820 }
821
822 ret = devm_mutex_init(dev, &st->lock);
823 if (ret)
824 return ret;
825
826 indio_dev->name = st->info->name;
827 indio_dev->channels = st->info->channels;
828 indio_dev->num_channels = st->info->num_channels;
829 indio_dev->info = st->info->num_channels > 1 ?
830 &ad4880_iio_info : &ad4080_iio_info;
831
832 ret = ad4080_properties_parse(st, dev);
833 if (ret)
834 return ret;
835
836 clk = devm_clk_get_enabled(&spi->dev, "cnv");
837 if (IS_ERR(clk))
838 return PTR_ERR(clk);
839
840 st->clk_rate = clk_get_rate(clk);
841
842 /* Get backends for all channels */
843 for (unsigned int ch = 0; ch < st->info->num_channels; ch++) {
844 st->back[ch] = devm_iio_backend_get_by_index(dev, ch);
845 if (IS_ERR(st->back[ch]))
846 return PTR_ERR(st->back[ch]);
847
848 ret = devm_iio_backend_enable(dev, st->back[ch]);
849 if (ret)
850 return ret;
851 }
852
853 /*
854 * Request buffer from the first backend only. For multi-channel
855 * devices (e.g., AD4880), the FPGA uses two axi_ad408x IP instances
856 * (one per ADC channel) whose outputs are combined by a packer block
857 * that interleaves all channel data into a single DMA stream routed
858 * through the first backend's clock domain.
859 */
860 ret = devm_iio_backend_request_buffer(dev, st->back[0], indio_dev);
861 if (ret)
862 return ret;
863
864 ret = ad4080_setup(indio_dev);
865 if (ret)
866 return ret;
867
868 return devm_iio_device_register(&spi->dev, indio_dev);
869 }
870
871 static const struct spi_device_id ad4080_id[] = {
872 { .name = "ad4080", .driver_data = (kernel_ulong_t)&ad4080_chip_info },
873 { .name = "ad4081", .driver_data = (kernel_ulong_t)&ad4081_chip_info },
874 { .name = "ad4082", .driver_data = (kernel_ulong_t)&ad4082_chip_info },
875 { .name = "ad4083", .driver_data = (kernel_ulong_t)&ad4083_chip_info },
876 { .name = "ad4084", .driver_data = (kernel_ulong_t)&ad4084_chip_info },
877 { .name = "ad4085", .driver_data = (kernel_ulong_t)&ad4085_chip_info },
878 { .name = "ad4086", .driver_data = (kernel_ulong_t)&ad4086_chip_info },
879 { .name = "ad4087", .driver_data = (kernel_ulong_t)&ad4087_chip_info },
880 { .name = "ad4088", .driver_data = (kernel_ulong_t)&ad4088_chip_info },
881 { .name = "ad4880", .driver_data = (kernel_ulong_t)&ad4880_chip_info },
882 { .name = "ad4883", .driver_data = (kernel_ulong_t)&ad4883_chip_info },
883 { .name = "ad4884", .driver_data = (kernel_ulong_t)&ad4884_chip_info },
884 { }
885 };
886 MODULE_DEVICE_TABLE(spi, ad4080_id);
887
888 static const struct of_device_id ad4080_of_match[] = {
889 { .compatible = "adi,ad4080", &ad4080_chip_info },
890 { .compatible = "adi,ad4081", &ad4081_chip_info },
891 { .compatible = "adi,ad4082", &ad4082_chip_info },
892 { .compatible = "adi,ad4083", &ad4083_chip_info },
893 { .compatible = "adi,ad4084", &ad4084_chip_info },
894 { .compatible = "adi,ad4085", &ad4085_chip_info },
895 { .compatible = "adi,ad4086", &ad4086_chip_info },
896 { .compatible = "adi,ad4087", &ad4087_chip_info },
897 { .compatible = "adi,ad4088", &ad4088_chip_info },
898 { .compatible = "adi,ad4880", &ad4880_chip_info },
899 { .compatible = "adi,ad4883", &ad4883_chip_info },
900 { .compatible = "adi,ad4884", &ad4884_chip_info },
901 { }
902 };
903 MODULE_DEVICE_TABLE(of, ad4080_of_match);
904
905 static struct spi_driver ad4080_driver = {
906 .driver = {
907 .name = "ad4080",
908 .of_match_table = ad4080_of_match,
909 },
910 .probe = ad4080_probe,
911 .id_table = ad4080_id,
912 };
913 module_spi_driver(ad4080_driver);
914
915 MODULE_AUTHOR("Antoniu Miclaus <antoniu.miclaus@analog.com");
916 MODULE_DESCRIPTION("Analog Devices AD4080");
917 MODULE_LICENSE("GPL");
918 MODULE_IMPORT_NS("IIO_BACKEND");
919