1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) STMicroelectronics 2009
4 * Copyright (C) ST-Ericsson SA 2010
5 *
6 * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
7 *
8 * PRCMU f/w APIs
9 */
10 #ifndef __MFD_DB8500_PRCMU_H
11 #define __MFD_DB8500_PRCMU_H
12
13 #include <linux/interrupt.h>
14 #include <linux/bitops.h>
15 #include <linux/err.h>
16
17 #include <dt-bindings/mfd/dbx500-prcmu.h> /* For clock identifiers */
18
19 /*
20 * Registers
21 */
22 #define DB8500_PRCM_LINE_VALUE 0x170
23 #define DB8500_PRCM_LINE_VALUE_HSI_CAWAKE0 BIT(3)
24
25 #define DB8500_PRCM_DSI_SW_RESET 0x324
26 #define DB8500_PRCM_DSI_SW_RESET_DSI0_SW_RESETN BIT(0)
27 #define DB8500_PRCM_DSI_SW_RESET_DSI1_SW_RESETN BIT(1)
28 #define DB8500_PRCM_DSI_SW_RESET_DSI2_SW_RESETN BIT(2)
29
30 /* Offset for the firmware version within the TCPM */
31 #define DB8500_PRCMU_FW_VERSION_OFFSET 0xA4
32
33 #define DB8500_PRCMU_LEGACY_OFFSET 0xDD4
34
35 /*
36 * CLKOUT sources
37 */
38 #define PRCMU_CLKSRC_CLK38M 0x00
39 #define PRCMU_CLKSRC_ACLK 0x01
40 #define PRCMU_CLKSRC_SYSCLK 0x02
41 #define PRCMU_CLKSRC_LCDCLK 0x03
42 #define PRCMU_CLKSRC_SDMMCCLK 0x04
43 #define PRCMU_CLKSRC_TVCLK 0x05
44 #define PRCMU_CLKSRC_TIMCLK 0x06
45 #define PRCMU_CLKSRC_CLK009 0x07
46 /* These are only valid for CLKOUT1: */
47 #define PRCMU_CLKSRC_SIAMMDSPCLK 0x40
48 #define PRCMU_CLKSRC_I2CCLK 0x41
49 #define PRCMU_CLKSRC_MSP02CLK 0x42
50 #define PRCMU_CLKSRC_ARMPLL_OBSCLK 0x43
51 #define PRCMU_CLKSRC_HSIRXCLK 0x44
52 #define PRCMU_CLKSRC_HSITXCLK 0x45
53 #define PRCMU_CLKSRC_ARMCLKFIX 0x46
54 #define PRCMU_CLKSRC_HDMICLK 0x47
55
56 /*
57 * Definitions for controlling ESRAM0 in deep sleep.
58 */
59 #define ESRAM0_DEEP_SLEEP_STATE_OFF 1
60 #define ESRAM0_DEEP_SLEEP_STATE_RET 2
61
62 /* This portion previously known as <mach/prcmu-fw-defs_v1.h> */
63
64 /**
65 * enum state - ON/OFF state definition
66 * @OFF: State is ON
67 * @ON: State is OFF
68 *
69 */
70 enum state {
71 OFF = 0x0,
72 ON = 0x1,
73 };
74
75 /**
76 * enum ret_state - general purpose On/Off/Retention states
77 *
78 */
79 enum ret_state {
80 OFFST = 0,
81 ONST = 1,
82 RETST = 2
83 };
84
85 /**
86 * enum clk_arm - ARM Cortex A9 clock schemes
87 * @A9_OFF:
88 * @A9_BOOT:
89 * @A9_OPPT1:
90 * @A9_OPPT2:
91 * @A9_EXTCLK:
92 */
93 enum clk_arm {
94 A9_OFF,
95 A9_BOOT,
96 A9_OPPT1,
97 A9_OPPT2,
98 A9_EXTCLK
99 };
100
101 /**
102 * enum clk_gen - GEN#0/GEN#1 clock schemes
103 * @GEN_OFF:
104 * @GEN_BOOT:
105 * @GEN_OPPT1:
106 */
107 enum clk_gen {
108 GEN_OFF,
109 GEN_BOOT,
110 GEN_OPPT1,
111 };
112
113 /* some information between arm and xp70 */
114
115 /**
116 * enum romcode_write - Romcode message written by A9 AND read by XP70
117 * @RDY_2_DS: Value set when ApDeepSleep state can be executed by XP70
118 * @RDY_2_XP70_RST: Value set when 0x0F has been successfully polled by the
119 * romcode. The xp70 will go into self-reset
120 */
121 enum romcode_write {
122 RDY_2_DS = 0x09,
123 RDY_2_XP70_RST = 0x10
124 };
125
126 /**
127 * enum romcode_read - Romcode message written by XP70 and read by A9
128 * @INIT: Init value when romcode field is not used
129 * @FS_2_DS: Value set when power state is going from ApExecute to
130 * ApDeepSleep
131 * @END_DS: Value set when ApDeepSleep power state is reached coming from
132 * ApExecute state
133 * @DS_TO_FS: Value set when power state is going from ApDeepSleep to
134 * ApExecute
135 * @END_FS: Value set when ApExecute power state is reached coming from
136 * ApDeepSleep state
137 * @SWR: Value set when power state is going to ApReset
138 * @END_SWR: Value set when the xp70 finished executing ApReset actions and
139 * waits for romcode acknowledgment to go to self-reset
140 */
141 enum romcode_read {
142 INIT = 0x00,
143 FS_2_DS = 0x0A,
144 END_DS = 0x0B,
145 DS_TO_FS = 0x0C,
146 END_FS = 0x0D,
147 SWR = 0x0E,
148 END_SWR = 0x0F
149 };
150
151 /**
152 * enum ap_pwrst - current power states defined in PRCMU firmware
153 * @NO_PWRST: Current power state init
154 * @AP_BOOT: Current power state is apBoot
155 * @AP_EXECUTE: Current power state is apExecute
156 * @AP_DEEP_SLEEP: Current power state is apDeepSleep
157 * @AP_SLEEP: Current power state is apSleep
158 * @AP_IDLE: Current power state is apIdle
159 * @AP_RESET: Current power state is apReset
160 */
161 enum ap_pwrst {
162 NO_PWRST = 0x00,
163 AP_BOOT = 0x01,
164 AP_EXECUTE = 0x02,
165 AP_DEEP_SLEEP = 0x03,
166 AP_SLEEP = 0x04,
167 AP_IDLE = 0x05,
168 AP_RESET = 0x06
169 };
170
171 /**
172 * enum ap_pwrst_trans - Transition states defined in PRCMU firmware
173 * @NO_TRANSITION: No power state transition
174 * @APEXECUTE_TO_APSLEEP: Power state transition from ApExecute to ApSleep
175 * @APIDLE_TO_APSLEEP: Power state transition from ApIdle to ApSleep
176 * @APBOOT_TO_APEXECUTE: Power state transition from ApBoot to ApExecute
177 * @APEXECUTE_TO_APDEEPSLEEP: Power state transition from ApExecute to
178 * ApDeepSleep
179 * @APEXECUTE_TO_APIDLE: Power state transition from ApExecute to ApIdle
180 */
181 enum ap_pwrst_trans {
182 PRCMU_AP_NO_CHANGE = 0x00,
183 APEXECUTE_TO_APSLEEP = 0x01,
184 APIDLE_TO_APSLEEP = 0x02, /* To be removed */
185 PRCMU_AP_SLEEP = 0x01,
186 APBOOT_TO_APEXECUTE = 0x03,
187 APEXECUTE_TO_APDEEPSLEEP = 0x04, /* To be removed */
188 PRCMU_AP_DEEP_SLEEP = 0x04,
189 APEXECUTE_TO_APIDLE = 0x05, /* To be removed */
190 PRCMU_AP_IDLE = 0x05,
191 PRCMU_AP_DEEP_IDLE = 0x07,
192 };
193
194 /**
195 * enum hw_acc_state - State definition for hardware accelerator
196 * @HW_NO_CHANGE: The hardware accelerator state must remain unchanged
197 * @HW_OFF: The hardware accelerator must be switched off
198 * @HW_OFF_RAMRET: The hardware accelerator must be switched off with its
199 * internal RAM in retention
200 * @HW_ON: The hwa hardware accelerator hwa must be switched on
201 *
202 * NOTE! Deprecated, to be removed when all users switched over to use the
203 * regulator API.
204 */
205 enum hw_acc_state {
206 HW_NO_CHANGE = 0x00,
207 HW_OFF = 0x01,
208 HW_OFF_RAMRET = 0x02,
209 HW_ON = 0x04
210 };
211
212 /**
213 * enum mbox_2_arm_stat - Status messages definition for mbox_arm
214 * @BOOT_TO_EXECUTEOK: The apBoot to apExecute state transition has been
215 * completed
216 * @DEEPSLEEPOK: The apExecute to apDeepSleep state transition has been
217 * completed
218 * @SLEEPOK: The apExecute to apSleep state transition has been completed
219 * @IDLEOK: The apExecute to apIdle state transition has been completed
220 * @SOFTRESETOK: The A9 watchdog/ SoftReset state has been completed
221 * @SOFTRESETGO : The A9 watchdog/SoftReset state is on going
222 * @BOOT_TO_EXECUTE: The apBoot to apExecute state transition is on going
223 * @EXECUTE_TO_DEEPSLEEP: The apExecute to apDeepSleep state transition is on
224 * going
225 * @DEEPSLEEP_TO_EXECUTE: The apDeepSleep to apExecute state transition is on
226 * going
227 * @DEEPSLEEP_TO_EXECUTEOK: The apDeepSleep to apExecute state transition has
228 * been completed
229 * @EXECUTE_TO_SLEEP: The apExecute to apSleep state transition is on going
230 * @SLEEP_TO_EXECUTE: The apSleep to apExecute state transition is on going
231 * @SLEEP_TO_EXECUTEOK: The apSleep to apExecute state transition has been
232 * completed
233 * @EXECUTE_TO_IDLE: The apExecute to apIdle state transition is on going
234 * @IDLE_TO_EXECUTE: The apIdle to apExecute state transition is on going
235 * @IDLE_TO_EXECUTEOK: The apIdle to apExecute state transition has been
236 * completed
237 * @INIT_STATUS: Status init
238 */
239 enum ap_pwrsttr_status {
240 BOOT_TO_EXECUTEOK = 0xFF,
241 DEEPSLEEPOK = 0xFE,
242 SLEEPOK = 0xFD,
243 IDLEOK = 0xFC,
244 SOFTRESETOK = 0xFB,
245 SOFTRESETGO = 0xFA,
246 BOOT_TO_EXECUTE = 0xF9,
247 EXECUTE_TO_DEEPSLEEP = 0xF8,
248 DEEPSLEEP_TO_EXECUTE = 0xF7,
249 DEEPSLEEP_TO_EXECUTEOK = 0xF6,
250 EXECUTE_TO_SLEEP = 0xF5,
251 SLEEP_TO_EXECUTE = 0xF4,
252 SLEEP_TO_EXECUTEOK = 0xF3,
253 EXECUTE_TO_IDLE = 0xF2,
254 IDLE_TO_EXECUTE = 0xF1,
255 IDLE_TO_EXECUTEOK = 0xF0,
256 RDYTODS_RETURNTOEXE = 0xEF,
257 NORDYTODS_RETURNTOEXE = 0xEE,
258 EXETOSLEEP_RETURNTOEXE = 0xED,
259 EXETOIDLE_RETURNTOEXE = 0xEC,
260 INIT_STATUS = 0xEB,
261
262 /*error messages */
263 INITERROR = 0x00,
264 PLLARMLOCKP_ER = 0x01,
265 PLLDDRLOCKP_ER = 0x02,
266 PLLSOCLOCKP_ER = 0x03,
267 PLLSOCK1LOCKP_ER = 0x04,
268 ARMWFI_ER = 0x05,
269 SYSCLKOK_ER = 0x06,
270 I2C_NACK_DATA_ER = 0x07,
271 BOOT_ER = 0x08,
272 I2C_STATUS_ALWAYS_1 = 0x0A,
273 I2C_NACK_REG_ADDR_ER = 0x0B,
274 I2C_NACK_DATA0123_ER = 0x1B,
275 I2C_NACK_ADDR_ER = 0x1F,
276 CURAPPWRSTISNOT_BOOT = 0x20,
277 CURAPPWRSTISNOT_EXECUTE = 0x21,
278 CURAPPWRSTISNOT_SLEEPMODE = 0x22,
279 CURAPPWRSTISNOT_CORRECTFORIT10 = 0x23,
280 FIFO4500WUISNOT_WUPEVENT = 0x24,
281 PLL32KLOCKP_ER = 0x29,
282 DDRDEEPSLEEPOK_ER = 0x2A,
283 ROMCODEREADY_ER = 0x50,
284 WUPBEFOREDS = 0x51,
285 DDRCONFIG_ER = 0x52,
286 WUPBEFORESLEEP = 0x53,
287 WUPBEFOREIDLE = 0x54
288 }; /* earlier called as mbox_2_arm_stat */
289
290 /**
291 * enum dvfs_stat - DVFS status messages definition
292 * @DVFS_GO: A state transition DVFS is on going
293 * @DVFS_ARM100OPPOK: The state transition DVFS has been completed for 100OPP
294 * @DVFS_ARM50OPPOK: The state transition DVFS has been completed for 50OPP
295 * @DVFS_ARMEXTCLKOK: The state transition DVFS has been completed for EXTCLK
296 * @DVFS_NOCHGTCLKOK: The state transition DVFS has been completed for
297 * NOCHGCLK
298 * @DVFS_INITSTATUS: Value init
299 */
300 enum dvfs_stat {
301 DVFS_GO = 0xFF,
302 DVFS_ARM100OPPOK = 0xFE,
303 DVFS_ARM50OPPOK = 0xFD,
304 DVFS_ARMEXTCLKOK = 0xFC,
305 DVFS_NOCHGTCLKOK = 0xFB,
306 DVFS_INITSTATUS = 0x00
307 };
308
309 /**
310 * enum sva_mmdsp_stat - SVA MMDSP status messages
311 * @SVA_MMDSP_GO: SVAMMDSP interrupt has happened
312 * @SVA_MMDSP_INIT: Status init
313 */
314 enum sva_mmdsp_stat {
315 SVA_MMDSP_GO = 0xFF,
316 SVA_MMDSP_INIT = 0x00
317 };
318
319 /**
320 * enum sia_mmdsp_stat - SIA MMDSP status messages
321 * @SIA_MMDSP_GO: SIAMMDSP interrupt has happened
322 * @SIA_MMDSP_INIT: Status init
323 */
324 enum sia_mmdsp_stat {
325 SIA_MMDSP_GO = 0xFF,
326 SIA_MMDSP_INIT = 0x00
327 };
328
329 /**
330 * enum mbox_to_arm_err - Error messages definition
331 * @INIT_ERR: Init value
332 * @PLLARMLOCKP_ERR: PLLARM has not been correctly locked in given time
333 * @PLLDDRLOCKP_ERR: PLLDDR has not been correctly locked in the given time
334 * @PLLSOC0LOCKP_ERR: PLLSOC0 has not been correctly locked in the given time
335 * @PLLSOC1LOCKP_ERR: PLLSOC1 has not been correctly locked in the given time
336 * @ARMWFI_ERR: The ARM WFI has not been correctly executed in the given time
337 * @SYSCLKOK_ERR: The SYSCLK is not available in the given time
338 * @BOOT_ERR: Romcode has not validated the XP70 self reset in the given time
339 * @ROMCODESAVECONTEXT: The Romcode didn.t correctly save it secure context
340 * @VARMHIGHSPEEDVALTO_ERR: The ARM high speed supply value transfered
341 * through I2C has not been correctly executed in the given time
342 * @VARMHIGHSPEEDACCESS_ERR: The command value of VarmHighSpeedVal transfered
343 * through I2C has not been correctly executed in the given time
344 * @VARMLOWSPEEDVALTO_ERR:The ARM low speed supply value transfered through
345 * I2C has not been correctly executed in the given time
346 * @VARMLOWSPEEDACCESS_ERR: The command value of VarmLowSpeedVal transfered
347 * through I2C has not been correctly executed in the given time
348 * @VARMRETENTIONVALTO_ERR: The ARM retention supply value transfered through
349 * I2C has not been correctly executed in the given time
350 * @VARMRETENTIONACCESS_ERR: The command value of VarmRetentionVal transfered
351 * through I2C has not been correctly executed in the given time
352 * @VAPEHIGHSPEEDVALTO_ERR: The APE highspeed supply value transfered through
353 * I2C has not been correctly executed in the given time
354 * @VSAFEHPVALTO_ERR: The SAFE high power supply value transfered through I2C
355 * has not been correctly executed in the given time
356 * @VMODSEL1VALTO_ERR: The MODEM sel1 supply value transfered through I2C has
357 * not been correctly executed in the given time
358 * @VMODSEL2VALTO_ERR: The MODEM sel2 supply value transfered through I2C has
359 * not been correctly executed in the given time
360 * @VARMOFFACCESS_ERR: The command value of Varm ON/OFF transfered through
361 * I2C has not been correctly executed in the given time
362 * @VAPEOFFACCESS_ERR: The command value of Vape ON/OFF transfered through
363 * I2C has not been correctly executed in the given time
364 * @VARMRETACCES_ERR: The command value of Varm retention ON/OFF transfered
365 * through I2C has not been correctly executed in the given time
366 * @CURAPPWRSTISNOTBOOT:Generated when Arm want to do power state transition
367 * ApBoot to ApExecute but the power current state is not Apboot
368 * @CURAPPWRSTISNOTEXECUTE: Generated when Arm want to do power state
369 * transition from ApExecute to others power state but the
370 * power current state is not ApExecute
371 * @CURAPPWRSTISNOTSLEEPMODE: Generated when wake up events are transmitted
372 * but the power current state is not ApDeepSleep/ApSleep/ApIdle
373 * @CURAPPWRSTISNOTCORRECTDBG: Generated when wake up events are transmitted
374 * but the power current state is not correct
375 * @ARMREGU1VALTO_ERR:The ArmRegu1 value transferred through I2C has not
376 * been correctly executed in the given time
377 * @ARMREGU2VALTO_ERR: The ArmRegu2 value transferred through I2C has not
378 * been correctly executed in the given time
379 * @VAPEREGUVALTO_ERR: The VApeRegu value transfered through I2C has not
380 * been correctly executed in the given time
381 * @VSMPS3REGUVALTO_ERR: The VSmps3Regu value transfered through I2C has not
382 * been correctly executed in the given time
383 * @VMODREGUVALTO_ERR: The VModemRegu value transfered through I2C has not
384 * been correctly executed in the given time
385 */
386 enum mbox_to_arm_err {
387 INIT_ERR = 0x00,
388 PLLARMLOCKP_ERR = 0x01,
389 PLLDDRLOCKP_ERR = 0x02,
390 PLLSOC0LOCKP_ERR = 0x03,
391 PLLSOC1LOCKP_ERR = 0x04,
392 ARMWFI_ERR = 0x05,
393 SYSCLKOK_ERR = 0x06,
394 BOOT_ERR = 0x07,
395 ROMCODESAVECONTEXT = 0x08,
396 VARMHIGHSPEEDVALTO_ERR = 0x10,
397 VARMHIGHSPEEDACCESS_ERR = 0x11,
398 VARMLOWSPEEDVALTO_ERR = 0x12,
399 VARMLOWSPEEDACCESS_ERR = 0x13,
400 VARMRETENTIONVALTO_ERR = 0x14,
401 VARMRETENTIONACCESS_ERR = 0x15,
402 VAPEHIGHSPEEDVALTO_ERR = 0x16,
403 VSAFEHPVALTO_ERR = 0x17,
404 VMODSEL1VALTO_ERR = 0x18,
405 VMODSEL2VALTO_ERR = 0x19,
406 VARMOFFACCESS_ERR = 0x1A,
407 VAPEOFFACCESS_ERR = 0x1B,
408 VARMRETACCES_ERR = 0x1C,
409 CURAPPWRSTISNOTBOOT = 0x20,
410 CURAPPWRSTISNOTEXECUTE = 0x21,
411 CURAPPWRSTISNOTSLEEPMODE = 0x22,
412 CURAPPWRSTISNOTCORRECTDBG = 0x23,
413 ARMREGU1VALTO_ERR = 0x24,
414 ARMREGU2VALTO_ERR = 0x25,
415 VAPEREGUVALTO_ERR = 0x26,
416 VSMPS3REGUVALTO_ERR = 0x27,
417 VMODREGUVALTO_ERR = 0x28
418 };
419
420 enum hw_acc {
421 SVAMMDSP = 0,
422 SVAPIPE = 1,
423 SIAMMDSP = 2,
424 SIAPIPE = 3,
425 SGA = 4,
426 B2R2MCDE = 5,
427 ESRAM12 = 6,
428 ESRAM34 = 7,
429 };
430
431 enum cs_pwrmgt {
432 PWRDNCS0 = 0,
433 WKUPCS0 = 1,
434 PWRDNCS1 = 2,
435 WKUPCS1 = 3
436 };
437
438 /* Defs related to autonomous power management */
439
440 /**
441 * enum sia_sva_pwr_policy - Power policy
442 * @NO_CHGT: No change
443 * @DSPOFF_HWPOFF:
444 * @DSPOFFRAMRET_HWPOFF:
445 * @DSPCLKOFF_HWPOFF:
446 * @DSPCLKOFF_HWPCLKOFF:
447 *
448 */
449 enum sia_sva_pwr_policy {
450 NO_CHGT = 0x0,
451 DSPOFF_HWPOFF = 0x1,
452 DSPOFFRAMRET_HWPOFF = 0x2,
453 DSPCLKOFF_HWPOFF = 0x3,
454 DSPCLKOFF_HWPCLKOFF = 0x4,
455 };
456
457 /**
458 * enum auto_enable - Auto Power enable
459 * @AUTO_OFF:
460 * @AUTO_ON:
461 *
462 */
463 enum auto_enable {
464 AUTO_OFF = 0x0,
465 AUTO_ON = 0x1,
466 };
467
468 /* End of file previously known as prcmu-fw-defs_v1.h */
469
470 /**
471 * enum prcmu_power_status - results from set_power_state
472 * @PRCMU_SLEEP_OK: Sleep went ok
473 * @PRCMU_DEEP_SLEEP_OK: DeepSleep went ok
474 * @PRCMU_IDLE_OK: Idle went ok
475 * @PRCMU_DEEPIDLE_OK: DeepIdle went ok
476 * @PRCMU_PRCMU2ARMPENDINGIT_ER: Pending interrupt detected
477 * @PRCMU_ARMPENDINGIT_ER: Pending interrupt detected
478 *
479 */
480 enum prcmu_power_status {
481 PRCMU_SLEEP_OK = 0xf3,
482 PRCMU_DEEP_SLEEP_OK = 0xf6,
483 PRCMU_IDLE_OK = 0xf0,
484 PRCMU_DEEPIDLE_OK = 0xe3,
485 PRCMU_PRCMU2ARMPENDINGIT_ER = 0x91,
486 PRCMU_ARMPENDINGIT_ER = 0x93,
487 };
488
489 /* PRCMU Wakeup defines */
490 enum prcmu_wakeup_index {
491 PRCMU_WAKEUP_INDEX_RTC,
492 PRCMU_WAKEUP_INDEX_RTT0,
493 PRCMU_WAKEUP_INDEX_RTT1,
494 PRCMU_WAKEUP_INDEX_HSI0,
495 PRCMU_WAKEUP_INDEX_HSI1,
496 PRCMU_WAKEUP_INDEX_USB,
497 PRCMU_WAKEUP_INDEX_ABB,
498 PRCMU_WAKEUP_INDEX_ABB_FIFO,
499 PRCMU_WAKEUP_INDEX_ARM,
500 PRCMU_WAKEUP_INDEX_CD_IRQ,
501 NUM_PRCMU_WAKEUP_INDICES
502 };
503
504 #define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name))
505
506 /**
507 * enum prcmu_wdog_id - PRCMU watchdog IDs
508 * @PRCMU_WDOG_ALL: use all timers
509 * @PRCMU_WDOG_CPU1: use first CPU timer only
510 * @PRCMU_WDOG_CPU2: use second CPU timer conly
511 */
512 enum prcmu_wdog_id {
513 PRCMU_WDOG_ALL = 0x00,
514 PRCMU_WDOG_CPU1 = 0x01,
515 PRCMU_WDOG_CPU2 = 0x02,
516 };
517
518 /**
519 * enum ape_opp - APE OPP states definition
520 * @APE_OPP_INIT:
521 * @APE_NO_CHANGE: The APE operating point is unchanged
522 * @APE_100_OPP: The new APE operating point is ape100opp
523 * @APE_50_OPP: 50%
524 * @APE_50_PARTLY_25_OPP: 50%, except some clocks at 25%.
525 */
526 enum ape_opp {
527 APE_OPP_INIT = 0x00,
528 APE_NO_CHANGE = 0x01,
529 APE_100_OPP = 0x02,
530 APE_50_OPP = 0x03,
531 APE_50_PARTLY_25_OPP = 0xFF,
532 };
533
534 /**
535 * enum arm_opp - ARM OPP states definition
536 * @ARM_OPP_INIT:
537 * @ARM_NO_CHANGE: The ARM operating point is unchanged
538 * @ARM_100_OPP: The new ARM operating point is arm100opp
539 * @ARM_50_OPP: The new ARM operating point is arm50opp
540 * @ARM_MAX_OPP: Operating point is "max" (more than 100)
541 * @ARM_MAX_FREQ100OPP: Set max opp if available, else 100
542 * @ARM_EXTCLK: The new ARM operating point is armExtClk
543 */
544 enum arm_opp {
545 ARM_OPP_INIT = 0x00,
546 ARM_NO_CHANGE = 0x01,
547 ARM_100_OPP = 0x02,
548 ARM_50_OPP = 0x03,
549 ARM_MAX_OPP = 0x04,
550 ARM_MAX_FREQ100OPP = 0x05,
551 ARM_EXTCLK = 0x07
552 };
553
554 /**
555 * enum ddr_opp - DDR OPP states definition
556 * @DDR_100_OPP: The new DDR operating point is ddr100opp
557 * @DDR_50_OPP: The new DDR operating point is ddr50opp
558 * @DDR_25_OPP: The new DDR operating point is ddr25opp
559 */
560 enum ddr_opp {
561 DDR_100_OPP = 0x00,
562 DDR_50_OPP = 0x01,
563 DDR_25_OPP = 0x02,
564 };
565
566 /**
567 * enum ddr_pwrst - DDR power states definition
568 * @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged
569 * @DDR_PWR_STATE_ON:
570 * @DDR_PWR_STATE_OFFLOWLAT:
571 * @DDR_PWR_STATE_OFFHIGHLAT:
572 */
573 enum ddr_pwrst {
574 DDR_PWR_STATE_UNCHANGED = 0x00,
575 DDR_PWR_STATE_ON = 0x01,
576 DDR_PWR_STATE_OFFLOWLAT = 0x02,
577 DDR_PWR_STATE_OFFHIGHLAT = 0x03
578 };
579
580 /*
581 * Definitions for autonomous power management configuration.
582 */
583
584 /* EPOD (power domain) IDs */
585
586 /*
587 * DB8500 EPODs
588 * - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP
589 * - EPOD_ID_SVAPIPE: power domain for SVA pipe
590 * - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP
591 * - EPOD_ID_SIAPIPE: power domain for SIA pipe
592 * - EPOD_ID_SGA: power domain for SGA
593 * - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE
594 * - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2
595 * - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4
596 * - NUM_EPOD_ID: number of power domains
597 *
598 * TODO: These should be prefixed.
599 */
600 #define EPOD_ID_SVAMMDSP 0
601 #define EPOD_ID_SVAPIPE 1
602 #define EPOD_ID_SIAMMDSP 2
603 #define EPOD_ID_SIAPIPE 3
604 #define EPOD_ID_SGA 4
605 #define EPOD_ID_B2R2_MCDE 5
606 #define EPOD_ID_ESRAM12 6
607 #define EPOD_ID_ESRAM34 7
608 #define NUM_EPOD_ID 8
609
610 /*
611 * state definition for EPOD (power domain)
612 * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged
613 * - EPOD_STATE_OFF: The EPOD is switched off
614 * - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in
615 * retention
616 * - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off
617 * - EPOD_STATE_ON: Same as above, but with clock enabled
618 */
619 #define EPOD_STATE_NO_CHANGE 0x00
620 #define EPOD_STATE_OFF 0x01
621 #define EPOD_STATE_RAMRET 0x02
622 #define EPOD_STATE_ON_CLK_OFF 0x03
623 #define EPOD_STATE_ON 0x04
624
625 #define PRCMU_FW_PROJECT_U8500 2
626 #define PRCMU_FW_PROJECT_U8400 3
627 #define PRCMU_FW_PROJECT_U9500 4 /* Customer specific */
628 #define PRCMU_FW_PROJECT_U8500_MBB 5
629 #define PRCMU_FW_PROJECT_U8500_C1 6
630 #define PRCMU_FW_PROJECT_U8500_C2 7
631 #define PRCMU_FW_PROJECT_U8500_C3 8
632 #define PRCMU_FW_PROJECT_U8500_C4 9
633 #define PRCMU_FW_PROJECT_U9500_MBL 10
634 #define PRCMU_FW_PROJECT_U8500_SSG1 11 /* Samsung specific */
635 #define PRCMU_FW_PROJECT_U8500_MBL2 12 /* Customer specific */
636 #define PRCMU_FW_PROJECT_U8520 13
637 #define PRCMU_FW_PROJECT_U8420 14
638 #define PRCMU_FW_PROJECT_U8500_SSG2 15 /* Samsung specific */
639 #define PRCMU_FW_PROJECT_U8420_SYSCLK 17
640 #define PRCMU_FW_PROJECT_A9420 20
641 /* [32..63] 9540 and derivatives */
642 #define PRCMU_FW_PROJECT_U9540 32
643 /* [64..95] 8540 and derivatives */
644 #define PRCMU_FW_PROJECT_L8540 64
645 /* [96..126] 8580 and derivatives */
646 #define PRCMU_FW_PROJECT_L8580 96
647
648 #define PRCMU_FW_PROJECT_NAME_LEN 20
649
650 /* PRCMU QoS APE OPP class */
651 #define PRCMU_QOS_APE_OPP 1
652 #define PRCMU_QOS_DDR_OPP 2
653 #define PRCMU_QOS_ARM_OPP 3
654 #define PRCMU_QOS_DEFAULT_VALUE -1
655
656 #define PRCMU_AUTO_PM_OFF 0
657 #define PRCMU_AUTO_PM_ON 1
658
659 #define PRCMU_AUTO_PM_POWER_ON_HSEM BIT(0)
660 #define PRCMU_AUTO_PM_POWER_ON_ABB_FIFO_IT BIT(1)
661
662 enum prcmu_auto_pm_policy {
663 PRCMU_AUTO_PM_POLICY_NO_CHANGE,
664 PRCMU_AUTO_PM_POLICY_DSP_OFF_HWP_OFF,
665 PRCMU_AUTO_PM_POLICY_DSP_OFF_RAMRET_HWP_OFF,
666 PRCMU_AUTO_PM_POLICY_DSP_CLK_OFF_HWP_OFF,
667 PRCMU_AUTO_PM_POLICY_DSP_CLK_OFF_HWP_CLK_OFF,
668 };
669
670 struct prcmu_fw_version {
671 u32 project; /* Notice, project shifted with 8 on ux540 */
672 u8 api_version;
673 u8 func_version;
674 u8 errata;
675 char project_name[PRCMU_FW_PROJECT_NAME_LEN];
676 };
677
678 /**
679 * struct prcmu_auto_pm_config - Autonomous power management configuration.
680 * @sia_auto_pm_enable: SIA autonomous pm enable. (PRCMU_AUTO_PM_{OFF,ON})
681 * @sia_power_on: SIA power ON enable. (PRCMU_AUTO_PM_POWER_ON_* bitmask)
682 * @sia_policy: SIA power policy. (enum prcmu_auto_pm_policy)
683 * @sva_auto_pm_enable: SVA autonomous pm enable. (PRCMU_AUTO_PM_{OFF,ON})
684 * @sva_power_on: SVA power ON enable. (PRCMU_AUTO_PM_POWER_ON_* bitmask)
685 * @sva_policy: SVA power policy. (enum prcmu_auto_pm_policy)
686 */
687 struct prcmu_auto_pm_config {
688 u8 sia_auto_pm_enable;
689 u8 sia_power_on;
690 u8 sia_policy;
691 u8 sva_auto_pm_enable;
692 u8 sva_power_on;
693 u8 sva_policy;
694 };
695
696 #ifdef CONFIG_MFD_DB8500_PRCMU
697
698 void db8500_prcmu_early_init(void);
699 int prcmu_set_rc_a2p(enum romcode_write);
700 enum romcode_read prcmu_get_rc_p2a(void);
701 enum ap_pwrst prcmu_get_xp70_current_state(void);
702 bool prcmu_has_arm_maxopp(void);
703 struct prcmu_fw_version *prcmu_get_fw_version(void);
704 int prcmu_release_usb_wakeup_state(void);
705 void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
706 struct prcmu_auto_pm_config *idle);
707 bool prcmu_is_auto_pm_enabled(void);
708
709 int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
710 unsigned long prcmu_clock_rate(u8 clock);
711 long prcmu_round_clock_rate(u8 clock, unsigned long rate);
712 int prcmu_set_clock_rate(u8 clock, unsigned long rate);
713 int prcmu_set_clock_divider(u8 clock, u8 divider);
714 int db8500_prcmu_config_hotdog(u8 threshold);
715 int db8500_prcmu_config_hotmon(u8 low, u8 high);
716 int db8500_prcmu_start_temp_sense(u16 cycles32k);
717 int db8500_prcmu_stop_temp_sense(void);
718 int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
719 int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
720 int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value,
721 u8 *mask, u8 size);
722
723 int prcmu_ac_wake_req(void);
724 void prcmu_ac_sleep_req(void);
725 void db8500_prcmu_modem_reset(void);
726
727 int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off);
728 int db8500_prcmu_enable_a9wdog(u8 id);
729 int db8500_prcmu_disable_a9wdog(u8 id);
730 int db8500_prcmu_kick_a9wdog(u8 id);
731 int db8500_prcmu_load_a9wdog(u8 id, u32 val);
732
733 void db8500_prcmu_system_reset(u16 reset_code);
734 int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll);
735 u8 db8500_prcmu_get_power_state_result(void);
736 void db8500_prcmu_enable_wakeups(u32 wakeups);
737 int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state);
738 int db8500_prcmu_request_clock(u8 clock, bool enable);
739 void db8500_prcmu_config_abb_event_readout(u32 abb_events);
740 void db8500_prcmu_get_abb_event_buffer(void __iomem **buf);
741 int db8500_prcmu_config_esram0_deep_sleep(u8 state);
742 u16 db8500_prcmu_get_reset_code(void);
743 bool db8500_prcmu_is_ac_wake_requested(void);
744 int db8500_prcmu_set_arm_opp(u8 opp);
745 int db8500_prcmu_get_arm_opp(void);
746 int db8500_prcmu_set_ape_opp(u8 opp);
747 int db8500_prcmu_get_ape_opp(void);
748 int db8500_prcmu_request_ape_opp_100_voltage(bool enable);
749 int db8500_prcmu_get_ddr_opp(void);
750
751 u32 db8500_prcmu_read(unsigned int reg);
752 void db8500_prcmu_write(unsigned int reg, u32 value);
753 void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value);
754
755 #else /* !CONFIG_MFD_DB8500_PRCMU */
756
db8500_prcmu_early_init(void)757 static inline void db8500_prcmu_early_init(void) {}
758
prcmu_set_rc_a2p(enum romcode_write code)759 static inline int prcmu_set_rc_a2p(enum romcode_write code)
760 {
761 return 0;
762 }
763
prcmu_get_rc_p2a(void)764 static inline enum romcode_read prcmu_get_rc_p2a(void)
765 {
766 return INIT;
767 }
768
prcmu_get_xp70_current_state(void)769 static inline enum ap_pwrst prcmu_get_xp70_current_state(void)
770 {
771 return AP_EXECUTE;
772 }
773
prcmu_has_arm_maxopp(void)774 static inline bool prcmu_has_arm_maxopp(void)
775 {
776 return false;
777 }
778
prcmu_get_fw_version(void)779 static inline struct prcmu_fw_version *prcmu_get_fw_version(void)
780 {
781 return NULL;
782 }
783
db8500_prcmu_set_ape_opp(u8 opp)784 static inline int db8500_prcmu_set_ape_opp(u8 opp)
785 {
786 return 0;
787 }
788
db8500_prcmu_get_ape_opp(void)789 static inline int db8500_prcmu_get_ape_opp(void)
790 {
791 return APE_100_OPP;
792 }
793
db8500_prcmu_request_ape_opp_100_voltage(bool enable)794 static inline int db8500_prcmu_request_ape_opp_100_voltage(bool enable)
795 {
796 return 0;
797 }
798
prcmu_release_usb_wakeup_state(void)799 static inline int prcmu_release_usb_wakeup_state(void)
800 {
801 return 0;
802 }
803
db8500_prcmu_get_ddr_opp(void)804 static inline int db8500_prcmu_get_ddr_opp(void)
805 {
806 return DDR_100_OPP;
807 }
808
prcmu_configure_auto_pm(struct prcmu_auto_pm_config * sleep,struct prcmu_auto_pm_config * idle)809 static inline void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
810 struct prcmu_auto_pm_config *idle)
811 {
812 }
813
prcmu_is_auto_pm_enabled(void)814 static inline bool prcmu_is_auto_pm_enabled(void)
815 {
816 return false;
817 }
818
prcmu_config_clkout(u8 clkout,u8 source,u8 div)819 static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
820 {
821 return 0;
822 }
823
prcmu_clock_rate(u8 clock)824 static inline unsigned long prcmu_clock_rate(u8 clock)
825 {
826 return 0;
827 }
828
prcmu_round_clock_rate(u8 clock,unsigned long rate)829 static inline long prcmu_round_clock_rate(u8 clock, unsigned long rate)
830 {
831 return 0;
832 }
833
prcmu_set_clock_rate(u8 clock,unsigned long rate)834 static inline int prcmu_set_clock_rate(u8 clock, unsigned long rate)
835 {
836 return 0;
837 }
838
prcmu_set_clock_divider(u8 clock,u8 divider)839 static inline int prcmu_set_clock_divider(u8 clock, u8 divider)
840 {
841 return 0;
842 }
843
db8500_prcmu_config_hotdog(u8 threshold)844 static inline int db8500_prcmu_config_hotdog(u8 threshold)
845 {
846 return 0;
847 }
848
db8500_prcmu_config_hotmon(u8 low,u8 high)849 static inline int db8500_prcmu_config_hotmon(u8 low, u8 high)
850 {
851 return 0;
852 }
853
db8500_prcmu_start_temp_sense(u16 cycles32k)854 static inline int db8500_prcmu_start_temp_sense(u16 cycles32k)
855 {
856 return 0;
857 }
858
db8500_prcmu_stop_temp_sense(void)859 static inline int db8500_prcmu_stop_temp_sense(void)
860 {
861 return 0;
862 }
863
prcmu_abb_read(u8 slave,u8 reg,u8 * value,u8 size)864 static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
865 {
866 return -EINVAL;
867 }
868
prcmu_abb_write(u8 slave,u8 reg,u8 * value,u8 size)869 static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
870 {
871 return -EINVAL;
872 }
873
prcmu_abb_write_masked(u8 slave,u8 reg,u8 * value,u8 * mask,u8 size)874 static inline int prcmu_abb_write_masked(u8 slave, u8 reg,
875 u8 *value, u8 *mask, u8 size)
876 {
877 return -EINVAL;
878 }
879
prcmu_ac_wake_req(void)880 static inline int prcmu_ac_wake_req(void)
881 {
882 return 0;
883 }
884
prcmu_ac_sleep_req(void)885 static inline void prcmu_ac_sleep_req(void) {}
886
db8500_prcmu_modem_reset(void)887 static inline void db8500_prcmu_modem_reset(void) {}
888
db8500_prcmu_system_reset(u16 reset_code)889 static inline void db8500_prcmu_system_reset(u16 reset_code) {}
890
db8500_prcmu_set_power_state(u8 state,bool keep_ulp_clk,bool keep_ap_pll)891 static inline int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk,
892 bool keep_ap_pll)
893 {
894 return 0;
895 }
896
db8500_prcmu_get_power_state_result(void)897 static inline u8 db8500_prcmu_get_power_state_result(void)
898 {
899 return 0;
900 }
901
db8500_prcmu_enable_wakeups(u32 wakeups)902 static inline void db8500_prcmu_enable_wakeups(u32 wakeups) {}
903
db8500_prcmu_set_epod(u16 epod_id,u8 epod_state)904 static inline int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
905 {
906 return 0;
907 }
908
db8500_prcmu_request_clock(u8 clock,bool enable)909 static inline int db8500_prcmu_request_clock(u8 clock, bool enable)
910 {
911 return 0;
912 }
913
db8500_prcmu_config_esram0_deep_sleep(u8 state)914 static inline int db8500_prcmu_config_esram0_deep_sleep(u8 state)
915 {
916 return 0;
917 }
918
db8500_prcmu_config_abb_event_readout(u32 abb_events)919 static inline void db8500_prcmu_config_abb_event_readout(u32 abb_events) {}
920
db8500_prcmu_get_abb_event_buffer(void __iomem ** buf)921 static inline void db8500_prcmu_get_abb_event_buffer(void __iomem **buf) {}
922
db8500_prcmu_get_reset_code(void)923 static inline u16 db8500_prcmu_get_reset_code(void)
924 {
925 return 0;
926 }
927
db8500_prcmu_config_a9wdog(u8 num,bool sleep_auto_off)928 static inline int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
929 {
930 return 0;
931 }
932
db8500_prcmu_enable_a9wdog(u8 id)933 static inline int db8500_prcmu_enable_a9wdog(u8 id)
934 {
935 return 0;
936 }
937
db8500_prcmu_disable_a9wdog(u8 id)938 static inline int db8500_prcmu_disable_a9wdog(u8 id)
939 {
940 return 0;
941 }
942
db8500_prcmu_kick_a9wdog(u8 id)943 static inline int db8500_prcmu_kick_a9wdog(u8 id)
944 {
945 return 0;
946 }
947
db8500_prcmu_load_a9wdog(u8 id,u32 val)948 static inline int db8500_prcmu_load_a9wdog(u8 id, u32 val)
949 {
950 return 0;
951 }
952
db8500_prcmu_is_ac_wake_requested(void)953 static inline bool db8500_prcmu_is_ac_wake_requested(void)
954 {
955 return false;
956 }
957
db8500_prcmu_set_arm_opp(u8 opp)958 static inline int db8500_prcmu_set_arm_opp(u8 opp)
959 {
960 return 0;
961 }
962
db8500_prcmu_get_arm_opp(void)963 static inline int db8500_prcmu_get_arm_opp(void)
964 {
965 return 0;
966 }
967
db8500_prcmu_read(unsigned int reg)968 static inline u32 db8500_prcmu_read(unsigned int reg)
969 {
970 return 0;
971 }
972
db8500_prcmu_write(unsigned int reg,u32 value)973 static inline void db8500_prcmu_write(unsigned int reg, u32 value) {}
974
db8500_prcmu_write_masked(unsigned int reg,u32 mask,u32 value)975 static inline void db8500_prcmu_write_masked(unsigned int reg, u32 mask,
976 u32 value) {}
977
978 #endif /* !CONFIG_MFD_DB8500_PRCMU */
979
prcmu_qos_add_requirement(int prcmu_qos_class,char * name,s32 value)980 static inline int prcmu_qos_add_requirement(int prcmu_qos_class,
981 char *name, s32 value)
982 {
983 return 0;
984 }
985
prcmu_qos_update_requirement(int prcmu_qos_class,char * name,s32 new_value)986 static inline int prcmu_qos_update_requirement(int prcmu_qos_class,
987 char *name, s32 new_value)
988 {
989 return 0;
990 }
991
prcmu_qos_remove_requirement(int prcmu_qos_class,char * name)992 static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name)
993 {
994 }
995
996 #endif /* __MFD_DB8500_PRCMU_H */
997