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/linux/arch/riscv/net/
H A Dbpf_jit.h241 static inline u32 rv_r_insn(u8 funct7, u8 rs2, u8 rs1, u8 funct3, u8 rd, in rv_r_insn() argument
245 (rd << 7) | opcode; in rv_r_insn()
248 static inline u32 rv_i_insn(u16 imm11_0, u8 rs1, u8 funct3, u8 rd, u8 opcode) in rv_i_insn() argument
250 return (imm11_0 << 20) | (rs1 << 15) | (funct3 << 12) | (rd << 7) | in rv_i_insn()
271 static inline u32 rv_u_insn(u32 imm31_12, u8 rd, u8 opcode) in rv_u_insn() argument
273 return (imm31_12 << 12) | (rd << 7) | opcode; in rv_u_insn()
276 static inline u32 rv_j_insn(u32 imm20_1, u8 rd, u8 opcode) in rv_j_insn() argument
283 return (imm << 12) | (rd << 7) | opcode; in rv_j_insn()
287 u8 funct3, u8 rd, u8 opcode) in rv_amo_insn() argument
291 return rv_r_insn(funct7, rs2, rs1, funct3, rd, opcode); in rv_amo_insn()
[all …]
H A Dbpf_jit_comp32.c111 static void emit_imm(const s8 rd, s32 imm, struct rv_jit_context *ctx) in emit_imm() argument
117 emit(rv_lui(rd, upper), ctx); in emit_imm()
118 emit(rv_addi(rd, rd, lower), ctx); in emit_imm()
120 emit(rv_addi(rd, RV_REG_ZERO, lower), ctx); in emit_imm()
124 static void emit_imm32(const s8 *rd, s32 imm, struct rv_jit_context *ctx) in emit_imm32() argument
127 emit_imm(lo(rd), imm, ctx); in emit_imm32()
131 emit(rv_addi(hi(rd), RV_REG_ZERO, 0), ctx); in emit_imm32()
133 emit(rv_addi(hi(rd), RV_REG_ZERO, -1), ctx); in emit_imm32()
136 static void emit_imm64(const s8 *rd, s32 imm_hi, s32 imm_lo, in emit_imm64() argument
139 emit_imm(lo(rd), imm_lo, ctx); in emit_imm64()
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H A Dbpf_jit_comp64.c153 static void emit_sextw_alt(u8 *rd, u8 ra, struct rv_jit_context *ctx) in emit_sextw_alt() argument
155 emit_sextw(ra, *rd, ctx); in emit_sextw_alt()
156 *rd = ra; in emit_sextw_alt()
159 static void emit_zextw_alt(u8 *rd, u8 ra, struct rv_jit_context *ctx) in emit_zextw_alt() argument
161 emit_zextw(ra, *rd, ctx); in emit_zextw_alt()
162 *rd = ra; in emit_zextw_alt()
166 static int emit_addr(u8 rd, u64 addr, bool extra_pass, struct rv_jit_context *ctx) in emit_addr() argument
182 emit(rv_auipc(rd, upper), ctx); in emit_addr()
183 emit(rv_addi(rd, rd, lower), ctx); in emit_addr()
188 static void emit_imm(u8 rd, s64 val, struct rv_jit_context *ctx) in emit_imm() argument
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/linux/arch/arm/net/
H A Dbpf_jit_32.h165 #define _AL3_R(op, rd, rn, rm) ((op ## _R) | (rd) << 12 | (rn) << 16 | (rm)) argument
167 #define _AL3_I(op, rd, rn, imm) ((op ## _I) | (rd) << 12 | (rn) << 16 | (imm)) argument
171 #define ARM_ADD_R(rd, rn, rm) _AL3_R(ARM_INST_ADD, rd, rn, rm) argument
172 #define ARM_ADDS_R(rd, rn, rm) _AL3_R(ARM_INST_ADDS, rd, rn, rm) argument
173 #define ARM_ADD_I(rd, rn, imm) _AL3_I(ARM_INST_ADD, rd, rn, imm) argument
174 #define ARM_ADDS_I(rd, rn, imm) _AL3_I(ARM_INST_ADDS, rd, rn, imm) argument
175 #define ARM_ADC_R(rd, rn, rm) _AL3_R(ARM_INST_ADC, rd, rn, rm) argument
176 #define ARM_ADC_I(rd, rn, imm) _AL3_I(ARM_INST_ADC, rd, rn, imm) argument
178 #define ARM_AND_R(rd, rn, rm) _AL3_R(ARM_INST_AND, rd, rn, rm) argument
179 #define ARM_ANDS_R(rd, rn, rm) _AL3_R(ARM_INST_ANDS, rd, rn, rm) argument
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H A Dbpf_jit_32.c469 static inline void emit_mov_i_no8m(const u8 rd, u32 val, struct jit_ctx *ctx) in emit_mov_i_no8m() argument
472 emit(ARM_LDR_I(rd, ARM_PC, imm_offset(val, ctx)), ctx); in emit_mov_i_no8m()
474 emit(ARM_MOVW(rd, val & 0xffff), ctx); in emit_mov_i_no8m()
476 emit(ARM_MOVT(rd, val >> 16), ctx); in emit_mov_i_no8m()
480 static inline void emit_mov_i(const u8 rd, u32 val, struct jit_ctx *ctx) in emit_mov_i() argument
485 emit(ARM_MOV_I(rd, imm12), ctx); in emit_mov_i()
487 emit_mov_i_no8m(rd, val, ctx); in emit_mov_i()
520 static inline void emit_udivmod(u8 rd, u8 rm, u8 rn, struct jit_ctx *ctx, u8 op, u8 sign) in emit_udivmod() argument
529 emit(sign ? ARM_SDIV(rd, rm, rn) : ARM_UDIV(rd, rm, rn), ctx); in emit_udivmod()
532 emit(ARM_MLS(rd, rn, ARM_IP, rm), ctx); in emit_udivmod()
[all …]
/linux/arch/arm/include/debug/
H A Dsamsung.S12 .macro fifo_level_s5pv210 rd, rx
13 ldr \rd, [\rx, # S3C2410_UFSTAT]
14 ARM_BE8(rev \rd, \rd)
15 and \rd, \rd, #S5PV210_UFSTAT_TXMASK
18 .macro fifo_full_s5pv210 rd, rx
19 ldr \rd, [\rx, # S3C2410_UFSTAT]
20 ARM_BE8(rev \rd, \rd)
21 tst \rd, #S5PV210_UFSTAT_TXFULL
27 .macro fifo_level_s3c2440 rd, rx
28 ldr \rd, [\rx, # S3C2410_UFSTAT]
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H A D8250.S15 .macro store, rd, rx:vararg
16 ARM_BE8(rev \rd, \rd)
17 str \rd, \rx
18 ARM_BE8(rev \rd, \rd)
21 .macro load, rd, rx:vararg
22 ldr \rd, \rx
23 ARM_BE8(rev \rd, \rd)
26 .macro store, rd, rx:vararg
27 strb \rd, \rx
30 .macro load, rd, rx:vararg
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H A Dmsm.S14 .macro senduart, rd, rx
15 ARM_BE8(rev \rd, \rd )
17 str \rd, [\rx, #0x70]
20 .macro waituartcts,rd,rx
23 .macro waituarttxrdy, rd, rx
25 ldr \rd, [\rx, #0x08]
26 ARM_BE8(rev \rd, \rd )
27 tst \rd, #0x08
30 1001: ldr \rd, [\rx, #0x14]
31 ARM_BE8(rev \rd, \rd )
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H A Dicedcc.S15 .macro senduart, rd, rx
16 mcr p14, 0, \rd, c0, c5, 0
19 .macro busyuart, rd, rx
26 .macro waituartcts, rd, rx
29 .macro waituarttxrdy, rd, rx
30 mov \rd, #0x2000000
32 subs \rd, \rd, #1
42 .macro senduart, rd, rx
43 mcr p14, 0, \rd, c8, c0, 0
46 .macro busyuart, rd, rx
[all …]
H A Dpl01x.S18 .macro senduart,rd,rx
19 strb \rd, [\rx, #UART01x_DR]
22 .macro waituartcts,rd,rx
25 .macro waituarttxrdy,rd,rx
26 1001: ldr \rd, [\rx, #UART01x_FR]
27 ARM_BE8( rev \rd, \rd )
28 tst \rd, #UART01x_FR_TXFF
32 .macro busyuart,rd,rx
33 1001: ldr \rd, [\rx, #UART01x_FR]
34 ARM_BE8( rev \rd, \rd )
[all …]
H A Drenesas-scif.S36 .macro waituartcts,rd,rx
39 .macro waituarttxrdy, rd, rx
40 1001: ldrh \rd, [\rx, #FSR]
41 tst \rd, #TDFE
45 .macro senduart, rd, rx
46 strb \rd, [\rx, #FTDR]
47 ldrh \rd, [\rx, #FSR]
48 bic \rd, \rd, #TEND
49 strh \rd, [\rx, #FSR]
52 .macro busyuart, rd, rx
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H A Dzynq.S32 .macro senduart,rd,rx
33 strb \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA
36 .macro waituartcts,rd,rx
39 .macro waituarttxrdy,rd,rx
40 1001: ldr \rd, [\rx, #UART_SR_OFFSET]
41 ARM_BE8( rev \rd, \rd )
42 tst \rd, #UART_SR_TXEMPTY
46 .macro busyuart,rd,rx
47 1002: ldr \rd, [\rx, #UART_SR_OFFSET] @ get status register
48 ARM_BE8( rev \rd, \rd )
[all …]
/linux/kernel/time/
H A Dsched_clock.c85 struct clock_read_data *rd; in sched_clock_noinstr() local
91 rd = cd.read_data + (seq & 1); in sched_clock_noinstr()
93 cyc = (rd->read_sched_clock() - rd->epoch_cyc) & in sched_clock_noinstr()
94 rd->sched_clock_mask; in sched_clock_noinstr()
95 res = rd->epoch_ns + cyc_to_ns(cyc, rd->mult, rd->shift); in sched_clock_noinstr()
120 static void update_clock_read_data(struct clock_read_data *rd) in update_clock_read_data() argument
123 cd.read_data[1] = *rd; in update_clock_read_data()
129 cd.read_data[0] = *rd; in update_clock_read_data()
142 struct clock_read_data rd; in update_sched_clock() local
144 rd = cd.read_data[0]; in update_sched_clock()
[all …]
/linux/net/sunrpc/xprtrdma/
H A Dib_client.c60 struct rpcrdma_device *rd = rpcrdma_get_client_data(device); in rpcrdma_rn_register() local
62 if (!rd || test_bit(RPCRDMA_RD_F_REMOVING, &rd->rd_flags)) in rpcrdma_rn_register()
65 if (xa_alloc(&rd->rd_xa, &rn->rn_index, rn, xa_limit_32b, GFP_KERNEL) < 0) in rpcrdma_rn_register()
67 kref_get(&rd->rd_kref); in rpcrdma_rn_register()
75 struct rpcrdma_device *rd = container_of(kref, struct rpcrdma_device, in rpcrdma_rn_release() local
78 trace_rpcrdma_client_completion(rd->rd_device); in rpcrdma_rn_release()
79 complete(&rd->rd_done); in rpcrdma_rn_release()
90 struct rpcrdma_device *rd = rpcrdma_get_client_data(device); in rpcrdma_rn_unregister() local
92 if (!rd) in rpcrdma_rn_unregister()
96 xa_erase(&rd->rd_xa, rn->rn_index); in rpcrdma_rn_unregister()
[all …]
/linux/fs/jffs2/
H A Dwrite.c206 struct jffs2_raw_dirent *rd, const unsigned char *name, in jffs2_write_dirent() argument
218 je32_to_cpu(rd->pino), name, name, je32_to_cpu(rd->ino), in jffs2_write_dirent()
219 je32_to_cpu(rd->name_crc)); in jffs2_write_dirent()
221 D1(if(je32_to_cpu(rd->hdr_crc) != crc32(0, rd, sizeof(struct jffs2_unknown_node)-4)) { in jffs2_write_dirent()
231 je32_to_cpu(rd->pino), name, name, je32_to_cpu(rd->ino), in jffs2_write_dirent()
232 je32_to_cpu(rd->name_crc)); in jffs2_write_dirent()
237 vecs[0].iov_base = rd; in jffs2_write_dirent()
238 vecs[0].iov_len = sizeof(*rd); in jffs2_write_dirent()
246 fd->version = je32_to_cpu(rd->version); in jffs2_write_dirent()
247 fd->ino = je32_to_cpu(rd->ino); in jffs2_write_dirent()
[all …]
H A Ddir.c292 struct jffs2_raw_dirent *rd; in jffs2_symlink() local
386 ret = jffs2_reserve_space(c, sizeof(*rd)+namelen, &alloclen, in jffs2_symlink()
391 rd = jffs2_alloc_raw_dirent(); in jffs2_symlink()
392 if (!rd) { in jffs2_symlink()
402 rd->magic = cpu_to_je16(JFFS2_MAGIC_BITMASK); in jffs2_symlink()
403 rd->nodetype = cpu_to_je16(JFFS2_NODETYPE_DIRENT); in jffs2_symlink()
404 rd->totlen = cpu_to_je32(sizeof(*rd) + namelen); in jffs2_symlink()
405 rd->hdr_crc = cpu_to_je32(crc32(0, rd, sizeof(struct jffs2_unknown_node)-4)); in jffs2_symlink()
407 rd->pino = cpu_to_je32(dir_i->i_ino); in jffs2_symlink()
408 rd->version = cpu_to_je32(++dir_f->highest_version); in jffs2_symlink()
[all …]
/linux/drivers/powercap/
H A Dintel_rapl_common.c125 static bool is_pl_valid(struct rapl_domain *rd, int pl) in is_pl_valid() argument
129 return rd->rpl[pl].name ? true : false; in is_pl_valid()
132 static int get_pl_lock_prim(struct rapl_domain *rd, int pl) in get_pl_lock_prim() argument
134 if (rd->rp->priv->type == RAPL_IF_TPMI) { in get_pl_lock_prim()
151 if (rd->rp->priv->limits[rd->id] & BIT(POWER_LIMIT2)) in get_pl_lock_prim()
156 static int get_pl_prim(struct rapl_domain *rd, int pl, enum pl_prims prim) in get_pl_prim() argument
162 if (prim == PL_CLAMP && rd->rp->priv->type != RAPL_IF_TPMI) in get_pl_prim()
171 return get_pl_lock_prim(rd, pl); in get_pl_prim()
176 if (prim == PL_CLAMP && rd->rp->priv->type != RAPL_IF_TPMI) in get_pl_prim()
185 return get_pl_lock_prim(rd, pl); in get_pl_prim()
[all …]
/linux/arch/parisc/net/
H A Dbpf_jit_comp64.c70 static void emit_hppa_copy(const s8 rs, const s8 rd, struct hppa_jit_context *ctx) in emit_hppa_copy() argument
72 REG_SET_SEEN(ctx, rd); in emit_hppa_copy()
73 if (OPTIMIZE_HPPA && (rs == rd)) in emit_hppa_copy()
76 emit(hppa_copy(rs, rd), ctx); in emit_hppa_copy()
135 static void emit_imm32(u8 rd, s32 imm, struct hppa_jit_context *ctx) in emit_imm32() argument
139 REG_SET_SEEN(ctx, rd); in emit_imm32()
141 emit(hppa_ldi(imm, rd), ctx); in emit_imm32()
145 emit(hppa_ldo(lower, HPPA_REG_ZERO, rd), ctx); in emit_imm32()
148 emit(hppa_ldil(imm, rd), ctx); in emit_imm32()
151 emit(hppa_ldo(lower, rd, rd), ctx); in emit_imm32()
[all …]
H A Dbpf_jit_comp32.c120 static void emit_hppa_copy(const s8 rs, const s8 rd, struct hppa_jit_context *ctx) in emit_hppa_copy() argument
122 REG_SET_SEEN(ctx, rd); in emit_hppa_copy()
123 if (OPTIMIZE_HPPA && (rs == rd)) in emit_hppa_copy()
126 emit(hppa_copy(rs, rd), ctx); in emit_hppa_copy()
141 static void emit_imm(const s8 rd, s32 imm, struct hppa_jit_context *ctx) in emit_imm() argument
145 REG_SET_SEEN(ctx, rd); in emit_imm()
147 emit(hppa_ldi(imm, rd), ctx); in emit_imm()
150 emit(hppa_ldil(imm, rd), ctx); in emit_imm()
153 emit(hppa_ldo(lower, rd, rd), ctx); in emit_imm()
156 static void emit_imm32(const s8 *rd, s32 imm, struct hppa_jit_context *ctx) in emit_imm32() argument
[all …]
/linux/arch/loongarch/net/
H A Dbpf_jit.h85 static inline void move_addr(struct jit_ctx *ctx, enum loongarch_gpr rd, u64 addr) in move_addr() argument
91 emit_insn(ctx, lu12iw, rd, imm_31_12); in move_addr()
95 emit_insn(ctx, ori, rd, rd, imm_11_0); in move_addr()
99 emit_insn(ctx, lu32id, rd, imm_51_32); in move_addr()
103 emit_insn(ctx, lu52id, rd, rd, imm_63_52); in move_addr()
106 static inline void move_imm(struct jit_ctx *ctx, enum loongarch_gpr rd, long imm, bool is32) in move_imm() argument
112 emit_insn(ctx, or, rd, LOONGARCH_GPR_ZERO, LOONGARCH_GPR_ZERO); in move_imm()
118 emit_insn(ctx, addiw, rd, LOONGARCH_GPR_ZERO, imm); in move_imm()
124 emit_insn(ctx, ori, rd, LOONGARCH_GPR_ZERO, imm); in move_imm()
132 emit_insn(ctx, lu52id, rd, LOONGARCH_GPR_ZERO, imm_63_52); in move_imm()
[all …]
/linux/drivers/media/tuners/
H A Dqt1010.c51 qt1010_i2c_oper_t rd[48] = { in qt1010_set_params() local
123 rd[2].val = reg05; in qt1010_set_params()
126 rd[4].val = (freq + QT1010_OFFSET) / FREQ1; in qt1010_set_params()
129 if (mod1 < 8000000) rd[6].val = 0x1d; in qt1010_set_params()
130 else rd[6].val = 0x1c; in qt1010_set_params()
133 if (mod1 < 1*FREQ2) rd[7].val = 0x09; /* +0 MHz */ in qt1010_set_params()
134 else if (mod1 < 2*FREQ2) rd[7].val = 0x08; /* +4 MHz */ in qt1010_set_params()
135 else if (mod1 < 3*FREQ2) rd[7].val = 0x0f; /* +8 MHz */ in qt1010_set_params()
136 else if (mod1 < 4*FREQ2) rd[7].val = 0x0e; /* +12 MHz */ in qt1010_set_params()
137 else if (mod1 < 5*FREQ2) rd[7].val = 0x0d; /* +16 MHz */ in qt1010_set_params()
[all …]
/linux/arch/sparc/include/asm/
H A Dhead_32.h13 rd %psr, %l0; b label; rd %wim, %l3; nop;
16 #define SRMMU_TFAULT rd %psr, %l0; rd %wim, %l3; b srmmu_fault; mov 1, %l7;
17 #define SRMMU_DFAULT rd %psr, %l0; rd %wim, %l3; b srmmu_fault; mov 0, %l7;
21 rd %psr, %l0; mov num, %l7; b bad_trap_handler; rd %wim, %l3;
38 rd %psr, %l0;
42 rd %psr,%l0; \
50 rd %psr,%l0; \
59 b getcc_trap_handler; rd %psr, %l0; nop; nop;
63 b setcc_trap_handler; rd %psr, %l0; nop; nop;
67 rd %psr, %i0; jmp %l2; rett %l2 + 4; nop;
[all …]
/linux/drivers/reset/
H A Dreset-pistachio.c66 struct pistachio_reset_data *rd; in pistachio_reset_assert() local
70 rd = container_of(rcdev, struct pistachio_reset_data, rcdev); in pistachio_reset_assert()
76 return regmap_update_bits(rd->periph_regs, PISTACHIO_SOFT_RESET, in pistachio_reset_assert()
83 struct pistachio_reset_data *rd; in pistachio_reset_deassert() local
87 rd = container_of(rcdev, struct pistachio_reset_data, rcdev); in pistachio_reset_deassert()
93 return regmap_update_bits(rd->periph_regs, PISTACHIO_SOFT_RESET, in pistachio_reset_deassert()
104 struct pistachio_reset_data *rd; in pistachio_reset_probe() local
108 rd = devm_kzalloc(dev, sizeof(*rd), GFP_KERNEL); in pistachio_reset_probe()
109 if (!rd) in pistachio_reset_probe()
112 rd->periph_regs = syscon_node_to_regmap(np->parent); in pistachio_reset_probe()
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/linux/arch/arm/mach-tegra/
H A Dsleep.h51 .macro cpu_to_halt_reg rd, rcpu
53 subne \rd, \rcpu, #1
54 movne \rd, \rd, lsl #3
55 addne \rd, \rd, #0x14
56 moveq \rd, #0
60 .macro cpu_to_csr_reg rd, rcpu
62 subne \rd, \rcpu, #1
63 movne \rd, \rd, lsl #3
64 addne \rd, \rd, #0x18
65 moveq \rd, #8
[all …]
/linux/arch/loongarch/kernel/
H A Dinst.c16 unsigned int rd = insn.reg1i20_format.rd; in simu_pc() local
26 regs->regs[rd] = pc + sign_extend64(imm << 2, 21); in simu_pc()
29 regs->regs[rd] = pc + sign_extend64(imm << 12, 31); in simu_pc()
32 regs->regs[rd] = pc + sign_extend64(imm << 18, 37); in simu_pc()
35 regs->regs[rd] = pc + sign_extend64(imm << 12, 31); in simu_pc()
36 regs->regs[rd] &= ~((1 << 12) - 1); in simu_pc()
48 unsigned int imm, imm_l, imm_h, rd, rj; in simu_branch() local
88 rd = insn.reg2i16_format.rd; in simu_branch()
91 if (regs->regs[rj] == regs->regs[rd]) in simu_branch()
97 if (regs->regs[rj] != regs->regs[rd]) in simu_branch()
[all …]

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