16 	unsigned int rd = insn.reg1i20_format.rd;  in simu_pc()  local
26 		regs->regs[rd] = pc + sign_extend64(imm << 2, 21);  in simu_pc()
29 		regs->regs[rd] = pc + sign_extend64(imm << 12, 31);  in simu_pc()
32 		regs->regs[rd] = pc + sign_extend64(imm << 18, 37);  in simu_pc()
35 		regs->regs[rd] = pc + sign_extend64(imm << 12, 31);  in simu_pc()
36 		regs->regs[rd] &= ~((1 << 12) - 1);  in simu_pc()
48 	unsigned int imm, imm_l, imm_h, rd, rj;  in simu_branch()  local
88 	rd = insn.reg2i16_format.rd;  in simu_branch()
91 		if (regs->regs[rj] == regs->regs[rd])  in simu_branch()
97 		if (regs->regs[rj] != regs->regs[rd])  in simu_branch()
103 		if ((long)regs->regs[rj] < (long)regs->regs[rd])  in simu_branch()
109 		if ((long)regs->regs[rj] >= (long)regs->regs[rd])  in simu_branch()
115 		if (regs->regs[rj] < regs->regs[rd])  in simu_branch()
121 		if (regs->regs[rj] >= regs->regs[rd])  in simu_branch()
128 		regs->regs[rd] = pc + LOONGARCH_INSN_SIZE;  in simu_branch()
270 u32 larch_insn_gen_or(enum loongarch_gpr rd, enum loongarch_gpr rj, enum loongarch_gpr rk)  in larch_insn_gen_or()  argument
274 	emit_or(&insn, rd, rj, rk);  in larch_insn_gen_or()
279 u32 larch_insn_gen_move(enum loongarch_gpr rd, enum loongarch_gpr rj)  in larch_insn_gen_move()  argument
281 	return larch_insn_gen_or(rd, rj, 0);  in larch_insn_gen_move()
284 u32 larch_insn_gen_lu12iw(enum loongarch_gpr rd, int imm)  in larch_insn_gen_lu12iw()  argument
293 	emit_lu12iw(&insn, rd, imm);  in larch_insn_gen_lu12iw()
298 u32 larch_insn_gen_lu32id(enum loongarch_gpr rd, int imm)  in larch_insn_gen_lu32id()  argument
307 	emit_lu32id(&insn, rd, imm);  in larch_insn_gen_lu32id()
312 u32 larch_insn_gen_lu52id(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm)  in larch_insn_gen_lu52id()  argument
321 	emit_lu52id(&insn, rd, rj, imm);  in larch_insn_gen_lu52id()
326 u32 larch_insn_gen_jirl(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm)  in larch_insn_gen_jirl()  argument
335 	emit_jirl(&insn, rj, rd, imm >> 2);  in larch_insn_gen_jirl()