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Searched refs:scr2 (Results 1 – 18 of 18) sorted by relevance

/illumos-gate/usr/src/uts/sun4u/sys/
H A Dtraptrace.h213 #define TRACE_NEXT(scr1, scr2, scr3) \ argument
214 CPU_INDEX(scr2, scr1); \
215 sll scr2, TRAPTR_SIZE_SHIFT, scr2; \
217 add scr1, scr2, scr2; \
218 ldub [scr2 + TRAPTR_ASIBUF], scr1; \
224 ld [scr2 + TRAPTR_OFFSET], scr1; \
225 ld [scr2 + TRAPTR_LIMIT], scr3; \
226 st scr1, [scr2 + TRAPTR_LAST_OFFSET]; \
231 st scr1, [scr2 + TRAPTR_OFFSET];
258 #define TRACE_RTT(code, scr1, scr2, scr3, scr4) \ argument
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H A Dcheetahasm.h59 #define GET_CPU_PRIVATE_PTR(off_reg, scr1, scr2, label) \ argument
60 CPU_ADDR(scr1, scr2); \
78 #define GET_DCACHE_DTAG(afar, datap, scr1, scr2, scr3) \ argument
81 srlx afar, CH_DCTAG_PA_SHIFT, scr2; \
83 or scr2, CH_DCTAG_VALID_BIT, scr2; /* tag we want */ \
87 cmp scr1, scr2; \
99 clr scr2; \
102 ldxa [scr3 + scr2]ASI_DC_DATA, scr1; /* read data */ \
106 cmp scr2, CH_DC_DATA_REG_SIZE - 8; \
108 add scr2, 8, scr2; \
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H A Dmachthread.h159 #define RESET_USER_RTT_REGS(scr1, scr2, label) \ argument
178 set rtt_ctx_end, scr2; \
179 cmp scr1, scr2; \
182 set rtt_ctx_start, scr2; \
183 cmp scr1, scr2; \
197 set TSTATE_KERN | TSTATE_IE, scr2; \
198 or scr1, scr2, scr2; \
199 wrpr %g0, scr2, %tstate; \
248 sethi %hi(kcontextreg), scr2; \
249 ldx [scr2 + %lo(kcontextreg)], scr2; \
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H A Dmachclock.h47 #define RD_TICK(out, scr1, scr2, label) \ argument
58 #define RD_CLOCK_TICK(out, scr1, scr2, label) \ argument
60 RD_TICK(out,scr1,scr2,label)
/illumos-gate/usr/src/uts/sun4v/sys/
H A Dtraptrace.h270 #define TRACE_NEXT(scr1, scr2, scr3) \ argument
271 CPU_INDEX(scr2, scr1); \
272 sll scr2, TRAPTR_SIZE_SHIFT, scr2; \
274 add scr1, scr2, scr2; \
275 ldub [scr2 + TRAPTR_ASIBUF], scr1; \
281 ld [scr2 + TRAPTR_OFFSET], scr1; \
282 ld [scr2 + TRAPTR_LIMIT], scr3; \
283 st scr1, [scr2 + TRAPTR_LAST_OFFSET]; \
288 st scr1, [scr2 + TRAPTR_OFFSET];
318 #define TRACE_RTT(code, scr1, scr2, scr3, scr4) \ argument
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H A Dmachclock.h55 #define RD_STICK(out, scr1, scr2, label) \ argument
58 ldx [scr1 + %lo(native_stick_offset)], scr2; \
61 sub scr1, scr2, scr2; \
63 brnz,pn scr2, .rd_stick.label; \
79 #define RD_CLOCK_TICK(out, scr1, scr2, label) \ argument
81 RD_STICK(out,scr1,scr2,label)
103 #define RD_TICK(out, scr1, scr2, label) \ argument
106 ldx [scr1 + %lo(native_tick_offset)], scr2; \
109 sub scr1, scr2, scr2; \
111 brnz,pn scr2, .rd_tick.label; \
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/illumos-gate/usr/src/uts/sparc/v7/sys/
H A Dtraptrace.h119 #define TRACE_NEXT(ptr, scr1, scr2) \ argument
120 CPU_INDEX(scr2); \
121 sll scr2, TRAPTR_SIZE_SHIFT, scr2; \
123 add scr2, scr1, scr1; \
125 ld [scr1 + TRAPTR_LIMIT], scr2; \
126 cmp ptr, scr2; \
130 set panicstr, scr2; \
131 ld [scr2], scr2; \
132 tst scr2; \
143 #define TRACE_RESTORE_PSR(old, scr1, scr2) \ argument
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/illumos-gate/usr/src/uts/intel/sys/
H A Dtraptrace.h116 #define TRACE_PTR(ptr, scr1, scr1_32, scr2, marker) \
123 leaq trap_trace_ctl(%rip), scr2; \
124 addq scr2, scr1; \
126 leaq TRAP_ENT_SIZE(ptr), scr2; \
127 cmpq TRAPTR_LIMIT(scr1), scr2; \
129 movq TRAPTR_FIRST(scr1), scr2; \
130 8: movq scr2, TRAPTR_NEXT(scr1); \
135 #define TRACE_PTR(ptr, scr1, scr1_32, scr2, marker) \
144 leal TRAP_ENT_SIZE(ptr), scr2; \
145 cmpl TRAPTR_LIMIT(scr1), scr2; \
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/illumos-gate/usr/src/uts/sun4v/vm/
H A Dmach_sfmmu.h87 #define TSTAT_CHECK_TL1(label, scr1, scr2) \ argument
89 sethi %hi(KERNELBASE), scr2; \
90 or scr2, %lo(KERNELBASE), scr2; \
91 cmp scr1, scr2; \
179 #define GET_MMU_BOTH_TAGACC(dtagacc, itagacc, scr1, scr2) \ argument
181 ldx [scr1 + MMFSA_D_ADDR], scr2; \
183 srlx scr2, MMU_PAGESHIFT, scr2; /* align to page boundary */ \
185 sllx scr2, MMU_PAGESHIFT, scr2; \
187 or scr2, dtagacc, dtagacc; \
188 ldx [scr1 + MMFSA_I_ADDR], scr2; \
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/illumos-gate/usr/src/uts/sun4u/cpu/
H A Dus3_jalapeno_asm.S102 #define SET_JP_SPEED(speed, scr1, scr2) \ argument
104 set JBUS_CONFIG_ECLK_MASK, scr2; \
105 andn scr1, scr2, scr1; \
106 set speed, scr2; \
107 or scr1, scr2, scr1; \
129 #define SET_SLAVE_T_SPEED(speed, scr1, scr2) \ argument
130 ldxa [%g0]ASI_JBUS_CONFIG, scr2; \
131 srlx scr2, JBUS_SLAVE_T_PORT_BIT, scr2; \
132 btst 1, scr2; \
135 SET_64BIT_PA(scr1, scr2, TOM_HIGH_PA, S_T_ESTAR_CTRL_PA); \
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H A Dus3_cheetahplus_asm.S66 #define ECACHE_REFLUSH_LINE(ec_set_size, index, scr2) \ argument
74 #define ECACHE_FLUSH_LINE(physaddr, ec_set_size, scr1, scr2) \ argument
77 set CHP_ECACHE_IDX_DISP_FLUSH, scr2; \
78 or scr2, scr1, scr1; \
79 ECACHE_REFLUSH_LINE(ec_set_size, scr1, scr2)
96 #define PN_ECACHE_REFLUSH_LINE(l2_index, l3_index, scr2, scr3) \ argument
97 set PN_L2_MAX_SET, scr2; \
100 ldxa [l2_index + scr2]ASI_L2_TAG, %g0; \
101 cmp scr2, %g0; \
103 sub scr2, scr3, scr2; \
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H A Dus3_cheetah_asm.S58 #define ECACHE_REFLUSH_LINE(ecache_size, alias_address, scr2) \ argument
61 #define ECACHE_FLUSH_LINE(physaddr, ecache_size, scr1, scr2) \ argument
63 add ecache_size, ecache_size, scr2; \
64 sub scr2, 1, scr2; \
65 and scr1, scr2, scr1; \
66 ASM_LDX(scr2, ecache_flushaddr); \
67 add scr1, scr2, scr1; \
68 ECACHE_REFLUSH_LINE(ecache_size, scr1, scr2)
H A Dcommon_asm.S52 #define GET_NATIVE_TIME(out, scr1, scr2) \ argument
54 #define DELTA_NATIVE_TIME(delta, reg, scr1, scr2, scr3) \ argument
60 #define WR_TICKCMPR(in, scr1, scr2, label) \ argument
182 #define GET_NATIVE_TIME(out, scr1, scr2) \ argument
184 #define DELTA_NATIVE_TIME(delta, reg, scr1, scr2, scr3) \ argument
199 #define WR_TICKCMPR(cmpr,scr1,scr2,label) \ argument
206 #define WR_TICKCMPR(in,scr1,scr2,label) \ argument
H A Dopl_olympus_asm.S448 #define OPL_TRAPTRACE(ptr, scr1, scr2, label) \ argument
459 rd %asi, scr2; \
477 wr %g0, scr2, %asi; \
483 ld [ptr + TRAPTR_LIMIT], scr2; \
486 sub scr2, TRAP_ENT_SIZE, scr2; \
487 cmp scr1, scr2; \
H A Dspitfire_asm.S311 #define GET_CPU_PRIVATE_PTR(r_or_s, scr1, scr2, label) \ argument
312 CPU_ADDR(scr1, scr2); \
/illumos-gate/usr/src/uts/sun4/sys/
H A Dclock.h244 #define NATIVE_TIME_TO_NSEC_SCALE(out, scr1, scr2, shift) \ argument
245 srlx out, 32, scr2; /* check high 32 bits */ \
247 brz,a,pt scr2, 6f; /* if clear, 32-bit fast path */\
250 srlx out, 32, scr2; /* scr2 = hi32(tick<<4) = H */ \
251 mulx scr2, scr1, scr2; /* scr2 = (H*F) */ \
256 add scr1, scr2, out; /* out = (H*F) + ((L*F) >> 32) */\
261 #define NATIVE_TIME_TO_NSEC(out, scr1, scr2) \ argument
264 NATIVE_TIME_TO_NSEC_SCALE(out, scr1, scr2, NSEC_SHIFT);
/illumos-gate/usr/src/uts/sun4u/vm/
H A Dmach_sfmmu.h120 #define TSTAT_CHECK_TL1(label, scr1, scr2) \ argument
122 sethi %hi(KERNELBASE), scr2; \
123 or scr2, %lo(KERNELBASE), scr2; \
124 cmp scr1, scr2; \
188 #define GET_MMU_BOTH_TAGACC(dtagacc, itagacc, scr1, scr2) \ argument
215 #define ITLB_STUFF(tte, scr1, scr2, scr3, scr4) \ argument
225 #define DTLB_STUFF(tte, scr1, scr2, scr3, scr4) \ argument
239 #define TTETOPFN(tte, vaddr, label, scr1, scr2, scr3) \ argument
245 sllx scr1, 1, scr2; \
246 add scr2, scr1, scr2; /* mulx 3 */ \
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/illumos-gate/usr/src/uts/sun4u/io/
H A Dpanther_asm.S75 #define PN_ECACHE_REFLUSH_LINE(l2_index, l3_index, scr2, scr3) \ argument
76 set PN_L2_MAX_SET, scr2; \
79 ldxa [l2_index + scr2]ASI_L2_TAG, %g0; \
80 cmp scr2, %g0; \
82 sub scr2, scr3, scr2; \
83 mov 6, scr2; \
85 cmp scr2, %g0; \
87 sub scr2, 1, scr2; \
88 set PN_L3_MAX_SET, scr2; \
91 ldxa [l3_index + scr2]ASI_EC_DIAG, %g0; \
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