102 #define	SET_JP_SPEED(speed, scr1, scr2)					\  argument
104 	set	JBUS_CONFIG_ECLK_MASK, scr2;				\
105 	andn	scr1, scr2, scr1;					\
106 	set	speed, scr2;						\
107 	or	scr1, scr2, scr1;					\
129 #define	SET_SLAVE_T_SPEED(speed, scr1, scr2)				\  argument
130 	ldxa	[%g0]ASI_JBUS_CONFIG, scr2;				\
131 	srlx	scr2, JBUS_SLAVE_T_PORT_BIT, scr2;			\
132 	btst	1, scr2;						\
135 	SET_64BIT_PA(scr1, scr2, TOM_HIGH_PA, S_T_ESTAR_CTRL_PA);	\
136 	SET_TOM_SPEED(speed, scr1, scr2);				\
147 #define	JP_ADJUST_FSM(value, scr1, scr2)				\  argument
149 	set	JP_MCU_FSM_MASK, scr2;					\
150 	andn	scr1, scr2, scr1;					\
151 	set	value, scr2;						\
152 	or	scr1, scr2, scr1;					\
177 #define	JP_FORCE_FULL_SPEED(old_lvl, scr2, scr3, scr4)			\  argument
181 	SET_64BIT_PA(scr2, scr3, TOM_HIGH_PA, M_T_ESTAR_CTRL_PA);	\
182 	ldxa	[scr2]ASI_IO, scr3;					\
195 	SET_TOM_SPEED(TOM_HALF_SPEED, scr2, scr3);			\
205 	SET_TOM_SPEED(TOM_FULL_SPEED, scr2, scr3);			\
225 #define	JP_RESTORE_SPEED(old_lvl, scr2, scr3, scr4)			\  argument
226 	srlx	old_lvl, JBUS_CONFIG_ECLK_SHIFT, scr2;			\
227 	and	scr2, 3, scr2;						\
228 	add	scr2, 1, scr2;						\
229 	cmp	scr2, 3;						\
232 	set	TOM_SLOW_SPEED, scr2;					\
236 	or	scr2, old_lvl, old_lvl;					\
244 	SET_64BIT_PA(scr2, scr3, TOM_HIGH_PA, M_T_ESTAR_CTRL_PA);	\
245 	SET_TOM_SPEED(TOM_HALF_SPEED, scr2, scr3);			\
258 	SET_TOM_SPEED(TOM_SLOW_SPEED, scr2, scr3);			\
298 #define	ECACHE_FLUSH_LINE(physaddr, ec_set_size, scr1, scr2)		\  argument
299 	CPU_INDEX(scr1, scr2);						\
301 	set	JP_ECACHE_IDX_DISP_FLUSH, scr2;				\
302 	or	scr2, scr1, scr2;					\
305 	or	scr2, scr1, scr1;					\
306 	ECACHE_REFLUSH_LINE(ec_set_size, scr1, scr2)
313 #define	GET_ECACHE_SIZE(scr1, scr2)					\  argument
314 	CPU_INDEX(scr1, scr2);						\
316 	set	cpunodes + ECACHE_SIZE, scr2;				\
317 	ld	[scr1 + scr2], scr1