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Searched refs:reg (Results 1 – 25 of 679) sorted by relevance

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/illumos-gate/usr/src/common/vga/
H A Dvgasubr.c52 #define PUTB(reg, off, v) ddi_put8(reg->handle, reg->addr + (off), v) argument
53 #define GETB(reg, off) ddi_get8(reg->handle, reg->addr + (off)) argument
60 #define PUTB(reg, off, v) outb(reg + (off), v) argument
61 #define GETB(reg, off) inb(reg + (off)) argument
92 vga_get_hardware_settings(vgaregmap_t reg, int *width, int *height) in vga_get_hardware_settings() argument
94 *width = (GET_HORIZ_END(reg)+1)*8; in vga_get_hardware_settings()
95 *height = GET_VERT_END(reg)+1; in vga_get_hardware_settings()
96 if (GET_VERT_X2(reg)) *height *= 2; in vga_get_hardware_settings()
100 vga_get_reg(vgaregmap_t reg, int indexreg) in vga_get_reg() argument
102 return (GETB(reg, indexreg)); in vga_get_reg()
[all …]
/illumos-gate/usr/src/uts/intel/io/intel_nhm/
H A Dintel_nhm.h62 #define MC_SCRUB_CONTROL_WR(cpu, reg) nhm_pci_putl(SOCKET_BUS(cpu), 3, 2, \ argument
63 0x4c, reg);
65 #define MC_SSR_CONTROL_WR(cpu, reg) nhm_pci_putl(SOCKET_BUS(cpu), 3, 2, 0x48, \ argument
66 reg);
102 #define MC_CONTROL_CHANNEL_ACTIVE(reg, channel) \ argument
103 ((reg) & (1 << (8 + (channel))) != 0)
104 #define MC_CONTROL_ECCEN(reg) (((reg) >> 1) & 1) argument
105 #define MC_CONTROL_CLOSED_PAGE(reg) ((reg) & 1) argument
106 #define MC_CONTROL_DIVBY3(reg) ((reg >> 6) &1) argument
113 #define CHANNEL_DISABLED(reg, channel) ((reg) & (1 << (channel))) argument
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H A Dnhm_pci_cfg.c49 pci_regspec_t reg; in nhm_pci_cfg_setup() local
52 reg.pci_phys_mid = 0; in nhm_pci_cfg_setup()
53 reg.pci_phys_low = 0; in nhm_pci_cfg_setup()
54 reg.pci_size_hi = 0; in nhm_pci_cfg_setup()
55 reg.pci_size_low = PCIE_CONF_HDR_SIZE; /* overriden in pciex */ in nhm_pci_cfg_setup()
59 reg.pci_phys_hi = PCI_REG_MAKE_BDFR( in nhm_pci_cfg_setup()
63 (int *)&reg, sizeof (reg)/sizeof (int)) != in nhm_pci_cfg_setup()
110 nhm_pci_getb(int bus, int dev, int func, int reg, int *interpose) in nhm_pci_getb() argument
115 return (cmi_pci_getb(bus, dev, func, reg, interpose, hdl)); in nhm_pci_getb()
119 nhm_pci_getw(int bus, int dev, int func, int reg, int *interpose) in nhm_pci_getw() argument
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/illumos-gate/usr/src/uts/common/io/ixgbe/core/
H A Dixgbe_dcb_82599.c126 u32 reg = 0; in ixgbe_dcb_config_rx_arbiter_82599() local
135 reg = IXGBE_RTRPCS_RRM | IXGBE_RTRPCS_RAC | IXGBE_RTRPCS_ARBDIS; in ixgbe_dcb_config_rx_arbiter_82599()
136 IXGBE_WRITE_REG(hw, IXGBE_RTRPCS, reg); in ixgbe_dcb_config_rx_arbiter_82599()
144 reg = 0; in ixgbe_dcb_config_rx_arbiter_82599()
146 reg |= (map[i] << (i * IXGBE_RTRUP2TC_UP_SHIFT)); in ixgbe_dcb_config_rx_arbiter_82599()
148 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg); in ixgbe_dcb_config_rx_arbiter_82599()
154 reg = credit_refill | (credit_max << IXGBE_RTRPT4C_MCL_SHIFT); in ixgbe_dcb_config_rx_arbiter_82599()
156 reg |= (u32)(bwg_id[i]) << IXGBE_RTRPT4C_BWG_SHIFT; in ixgbe_dcb_config_rx_arbiter_82599()
159 reg |= IXGBE_RTRPT4C_LSP; in ixgbe_dcb_config_rx_arbiter_82599()
161 IXGBE_WRITE_REG(hw, IXGBE_RTRPT4C(i), reg); in ixgbe_dcb_config_rx_arbiter_82599()
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H A Dixgbe_dcb_82598.c124 u32 reg = 0; in ixgbe_dcb_config_rx_arbiter_82598() local
129 reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA; in ixgbe_dcb_config_rx_arbiter_82598()
130 IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg); in ixgbe_dcb_config_rx_arbiter_82598()
132 reg = IXGBE_READ_REG(hw, IXGBE_RMCS); in ixgbe_dcb_config_rx_arbiter_82598()
134 reg &= ~IXGBE_RMCS_ARBDIS; in ixgbe_dcb_config_rx_arbiter_82598()
136 reg |= IXGBE_RMCS_RRM; in ixgbe_dcb_config_rx_arbiter_82598()
138 reg |= IXGBE_RMCS_DFP; in ixgbe_dcb_config_rx_arbiter_82598()
140 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg); in ixgbe_dcb_config_rx_arbiter_82598()
147 reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT); in ixgbe_dcb_config_rx_arbiter_82598()
150 reg |= IXGBE_RT2CR_LSP; in ixgbe_dcb_config_rx_arbiter_82598()
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/illumos-gate/usr/src/uts/common/io/mii/
H A Dmii_marvell.c151 uint16_t reg; in mvphy_reset_88e3016() local
156 reg = phy_read(ph, MVPHY_PSC); in mvphy_reset_88e3016()
158 reg |= MV_PSC_AUTO_MDIX; in mvphy_reset_88e3016()
159 reg &= ~(MV_PSC_EN_DETECT | MV_PSC_DIS_SCRAMBLER); in mvphy_reset_88e3016()
160 reg |= MV_PSC_LPNP; in mvphy_reset_88e3016()
165 phy_write(ph, MVPHY_PSC, reg); in mvphy_reset_88e3016()
184 uint16_t reg; in mvphy_loop_88e3016() local
193 reg = phy_read(ph, MII_CONTROL); in mvphy_loop_88e3016()
194 reg |= MII_CONTROL_RESET; in mvphy_loop_88e3016()
195 phy_write(ph, MII_CONTROL, reg); in mvphy_loop_88e3016()
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/illumos-gate/usr/src/uts/common/io/scsi/adapters/lmrc/
H A Dlmrc_reg.h66 #define LMRC_FW_RESET_REQUIRED(reg) (bitx32((reg), 0, 0) != 0) argument
67 #define LMRC_FW_RESET_ADAPTER(reg) (bitx32((reg), 1, 1) != 0) argument
68 #define LMRC_FW_MAX_CMD(reg) bitx32((reg), 15, 0) argument
69 #define LMRC_FW_MSIX_ENABLED(reg) (bitx32((reg), 26, 26) != 0) argument
70 #define LMRC_FW_STATE(reg) bitx32((reg), 31, 28) argument
73 #define LMRC_MAX_CHAIN_SIZE(reg) bitx32((reg), 9, 5) argument
74 #define LMRC_MAX_REPLY_QUEUES_EXT(reg) bitx32((reg), 21, 14) argument
75 #define LMRC_EXT_CHAIN_SIZE_SUPPORT(reg) (bitx32((reg), 22, 22) != 0) argument
76 #define LMRC_RDPQ_MODE_SUPPORT(reg) (bitx32((reg), 23, 23) != 0) argument
77 #define LMRC_SYNC_CACHE_SUPPORT(reg) (bitx32((reg), 24, 24) != 0) argument
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/illumos-gate/usr/src/uts/common/io/i40e/
H A Di40e_intr.c214 uint32_t reg; in i40e_intr_adminq_enable() local
216 reg = I40E_PFINT_DYN_CTL0_INTENA_MASK | in i40e_intr_adminq_enable()
219 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, reg); in i40e_intr_adminq_enable()
227 uint32_t reg; in i40e_intr_adminq_disable() local
229 reg = I40E_ITR_INDEX_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT; in i40e_intr_adminq_disable()
230 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, reg); in i40e_intr_adminq_disable()
243 uint32_t reg; in i40e_intr_io_enable() local
247 reg = I40E_PFINT_DYN_CTLN_INTENA_MASK | in i40e_intr_io_enable()
250 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vector - 1), reg); in i40e_intr_io_enable()
256 uint32_t reg; in i40e_intr_io_disable() local
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/illumos-gate/usr/src/uts/intel/io/intel_nb5000/
H A Dnb_pci_cfg.c49 pci_regspec_t reg; in nb_pci_cfg_setup() local
52 reg.pci_phys_hi = 16 << PCI_REG_DEV_SHIFT; /* Bus=0, Dev=16, Func=0 */ in nb_pci_cfg_setup()
53 reg.pci_phys_mid = 0; in nb_pci_cfg_setup()
54 reg.pci_phys_low = 0; in nb_pci_cfg_setup()
55 reg.pci_size_hi = 0; in nb_pci_cfg_setup()
56 reg.pci_size_low = PCIE_CONF_HDR_SIZE; /* overriden in pciex */ in nb_pci_cfg_setup()
60 (int *)&reg, sizeof (reg)/sizeof (int)) != DDI_PROP_SUCCESS) in nb_pci_cfg_setup()
67 reg.pci_phys_hi += 1 << PCI_REG_FUNC_SHIFT; in nb_pci_cfg_setup()
69 reg.pci_phys_hi = 17 << PCI_REG_DEV_SHIFT; /* Bus=0, Dev=17, Func=0 */ in nb_pci_cfg_setup()
72 (int *)&reg, sizeof (reg)/sizeof (int)) != DDI_PROP_SUCCESS) in nb_pci_cfg_setup()
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/illumos-gate/usr/src/uts/i86pc/sys/
H A Dpci_cfgspace_impl.h44 extern uint8_t pci_mech1_getb(int bus, int dev, int func, int reg);
45 extern uint16_t pci_mech1_getw(int bus, int dev, int func, int reg);
46 extern uint32_t pci_mech1_getl(int bus, int dev, int func, int reg);
47 extern void pci_mech1_putb(int bus, int dev, int func, int reg, uint8_t val);
48 extern void pci_mech1_putw(int bus, int dev, int func, int reg, uint16_t val);
49 extern void pci_mech1_putl(int bus, int dev, int func, int reg, uint32_t val);
55 extern uint8_t pci_mech1_amd_getb(int bus, int dev, int func, int reg);
56 extern uint16_t pci_mech1_amd_getw(int bus, int dev, int func, int reg);
57 extern uint32_t pci_mech1_amd_getl(int bus, int dev, int func, int reg);
58 extern void pci_mech1_amd_putb(int bus, int dev, int func, int reg,
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/illumos-gate/usr/src/uts/i86pc/os/
H A Dpci_mech1.c50 pci_mech1_getb(int bus, int device, int function, int reg) in pci_mech1_getb() argument
58 if (reg > pci_iocfg_max_offset) { in pci_mech1_getb()
63 outl(PCI_CONFADD, PCI_CADDR1(bus, device, function, reg)); in pci_mech1_getb()
64 val = inb(PCI_CONFDATA | (reg & 0x3)); in pci_mech1_getb()
70 pci_mech1_getw(int bus, int device, int function, int reg) in pci_mech1_getw() argument
79 if (reg > pci_iocfg_max_offset) { in pci_mech1_getw()
84 outl(PCI_CONFADD, PCI_CADDR1(bus, device, function, reg)); in pci_mech1_getw()
85 val = inw(PCI_CONFDATA | (reg & 0x2)); in pci_mech1_getw()
91 pci_mech1_getl(int bus, int device, int function, int reg) in pci_mech1_getl() argument
100 if (reg > pci_iocfg_max_offset) { in pci_mech1_getl()
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H A Dpci_mech2.c76 pci_mech2_getb(int bus, int device, int function, int reg) in pci_mech2_getb() argument
81 if (device >= PCI_MAX_DEVS_2 || reg > pci_iocfg_max_offset) in pci_mech2_getb()
85 val = inb(PCI_CADDR2(device, reg)); in pci_mech2_getb()
92 pci_mech2_getw(int bus, int device, int function, int reg) in pci_mech2_getw() argument
97 if (device >= PCI_MAX_DEVS_2 || reg > pci_iocfg_max_offset) in pci_mech2_getw()
101 val = inw(PCI_CADDR2(device, reg)); in pci_mech2_getw()
108 pci_mech2_getl(int bus, int device, int function, int reg) in pci_mech2_getl() argument
113 if (device >= PCI_MAX_DEVS_2 || reg > pci_iocfg_max_offset) in pci_mech2_getl()
117 val = inl(PCI_CADDR2(device, reg)); in pci_mech2_getl()
124 pci_mech2_putb(int bus, int device, int function, int reg, uint8_t val) in pci_mech2_putb() argument
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H A Dpci_mech1_amd.c95 pci_mech1_amd_getb(int bus, int device, int function, int reg) in pci_mech1_amd_getb() argument
104 if (reg > pci_iocfg_max_offset) { in pci_mech1_amd_getb()
109 outl(PCI_CONFADD, PCI_CADDR1_ECS(bus, device, function, reg)); in pci_mech1_amd_getb()
110 val = inb(PCI_CONFDATA | (reg & 0x3)); in pci_mech1_amd_getb()
116 pci_mech1_amd_getw(int bus, int device, int function, int reg) in pci_mech1_amd_getw() argument
125 if (reg > pci_iocfg_max_offset) { in pci_mech1_amd_getw()
130 outl(PCI_CONFADD, PCI_CADDR1_ECS(bus, device, function, reg)); in pci_mech1_amd_getw()
131 val = inw(PCI_CONFDATA | (reg & 0x2)); in pci_mech1_amd_getw()
137 pci_mech1_amd_getl(int bus, int device, int function, int reg) in pci_mech1_amd_getl() argument
146 if (reg > pci_iocfg_max_offset) { in pci_mech1_amd_getl()
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/illumos-gate/usr/src/cmd/rcm_daemon/common/
H A Dmpxio_rcm.c161 phci_list_t *reg; in rcm_mod_fini() local
170 reg = reg_list; in rcm_mod_fini()
171 while (reg) { in rcm_mod_fini()
172 next = reg->next; in rcm_mod_fini()
173 free(reg->phci.path); in rcm_mod_fini()
174 free(reg); in rcm_mod_fini()
175 reg = next; in rcm_mod_fini()
243 phci_list_t *reg; in mpxio_unregister() local
249 for (reg = reg_list; reg != NULL; reg = reg->next) { in mpxio_unregister()
250 (void) rcm_unregister_interest(hdl, reg->phci.path, 0); in mpxio_unregister()
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/illumos-gate/usr/src/common/bitext/
H A Dbitext.c27 bitx8(uint8_t reg, uint_t high, uint_t low) in bitx8() argument
36 return ((reg >> low) & mask); in bitx8()
40 bitx16(uint16_t reg, uint_t high, uint_t low) in bitx16() argument
49 return ((reg >> low) & mask); in bitx16()
54 bitx32(uint32_t reg, uint_t high, uint_t low) in bitx32() argument
64 return ((reg >> low) & mask); in bitx32()
68 bitx64(uint64_t reg, uint_t high, uint_t low) in bitx64() argument
77 return ((reg >> low) & mask); in bitx64()
81 bitset8(uint8_t reg, uint_t high, uint_t low, uint8_t val) in bitset8() argument
92 reg &= ~(mask << low); in bitset8()
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/illumos-gate/usr/src/uts/common/io/audio/drv/audio1575/
H A Daudio1575.h395 #define GET8(reg) \ argument
396 ddi_get8(statep->regsh, (void *)(statep->regsp + (reg)))
398 #define GET16(reg) \ argument
399 ddi_get16(statep->regsh, (void *)(statep->regsp + (reg)))
401 #define GET32(reg) \ argument
402 ddi_get32(statep->regsh, (void *)(statep->regsp + (reg)))
404 #define PUT8(reg, val) \ argument
405 ddi_put8(statep->regsh, (void *)(statep->regsp + (reg)), (val))
407 #define PUT16(reg, val) \ argument
408 ddi_put16(statep->regsh, (void *)(statep->regsp + (reg)), (val))
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/illumos-gate/usr/src/uts/common/sys/
H A Dvgasubr.h49 extern int vga_get_reg(vgaregmap_t reg, int i);
50 extern void vga_set_reg(vgaregmap_t reg, int i, int v);
51 extern int vga_get_crtc(vgaregmap_t reg, int i);
52 extern void vga_set_crtc(vgaregmap_t reg, int i, int v);
53 extern int vga_get_seq(vgaregmap_t reg, int i);
54 extern void vga_set_seq(vgaregmap_t reg, int i, int v);
55 extern int vga_get_grc(vgaregmap_t reg, int i);
56 extern void vga_set_grc(vgaregmap_t reg, int i, int v);
57 extern int vga_get_atr(vgaregmap_t reg, int i);
58 extern void vga_set_atr(vgaregmap_t reg, int i, int v);
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/illumos-gate/usr/src/tools/smatch/src/
H A Dexample.c156 struct hardreg *reg; member
183 return op->reg->name; in show_op()
381 static void flush_reg(struct bb_state *state, struct hardreg *reg) in flush_reg() argument
385 if (reg->busy) in flush_reg()
386 output_comment(state, "reg %s flushed while busy is %d!", reg->name, reg->busy); in flush_reg()
387 if (!reg->contains) in flush_reg()
389 reg->dead = 0; in flush_reg()
390 reg->used = 1; in flush_reg()
391 FOR_EACH_PTR_TAG(reg->contains, pseudo) { in flush_reg()
396 flush_one_pseudo(state, reg, pseudo); in flush_reg()
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/illumos-gate/usr/src/uts/common/io/usb/hcd/xhci/
H A Dxhci_hub.c248 uint32_t reg; in xhci_root_hub_handle_port_clear_feature() local
257 reg = xhci_get32(xhcip, XHCI_R_OPER, XHCI_PORTSC(port)); in xhci_root_hub_handle_port_clear_feature()
272 reg &= ~XHCI_PS_CLEAR; in xhci_root_hub_handle_port_clear_feature()
276 reg |= XHCI_PS_PED; in xhci_root_hub_handle_port_clear_feature()
279 reg &= ~XHCI_PS_PP; in xhci_root_hub_handle_port_clear_feature()
282 reg |= XHCI_PS_CSC; in xhci_root_hub_handle_port_clear_feature()
285 reg |= XHCI_PS_PRC; in xhci_root_hub_handle_port_clear_feature()
288 reg |= XHCI_PS_OCC; in xhci_root_hub_handle_port_clear_feature()
292 reg |= XHCI_PS_PLC; in xhci_root_hub_handle_port_clear_feature()
295 reg |= XHCI_PS_PEC; in xhci_root_hub_handle_port_clear_feature()
[all …]
/illumos-gate/usr/src/cmd/fm/modules/common/fabric-xlate/
H A Dfx_fire.c139 uint64_t reg; in fab_xlate_fire_ce() local
155 if (nvlist_lookup_uint64(erpt, "tlu-cess", &reg) == 0) { in fab_xlate_fire_ce()
156 data->pcie_ce_status = (uint32_t)reg | (uint32_t)(reg >> 32); in fab_xlate_fire_ce()
167 uint64_t reg; in fab_xlate_fire_ue() local
195 if (nvlist_lookup_uint64(erpt, "tlu-uess", &reg) == 0) { in fab_xlate_fire_ue()
196 data->pcie_ue_status = (uint32_t)reg | (uint32_t)(reg >> 32); in fab_xlate_fire_ue()
200 if ((reg & (uint64_t)entry->fire_bit) && in fab_xlate_fire_ue()
211 if (nvlist_lookup_uint64(erpt, "tlu-tueh1l", &reg) == 0) { in fab_xlate_fire_ue()
212 data->pcie_ue_hdr[0] = (uint32_t)(reg >> 32); in fab_xlate_fire_ue()
213 data->pcie_ue_hdr[1] = (uint32_t)(reg); in fab_xlate_fire_ue()
[all …]
/illumos-gate/usr/src/uts/common/io/e1000g/
H A De1000_osdep.h123 #define E1000_WRITE_REG(hw, reg, value) \ argument
127 (uint32_t *)((uintptr_t)(hw)->hw_addr + reg), \
132 e1000_translate_register_82542(reg)), \
136 #define E1000_READ_REG(hw, reg) (\ argument
139 (uint32_t *)((uintptr_t)(hw)->hw_addr + reg)) : \
142 e1000_translate_register_82542(reg))))
144 #define E1000_WRITE_REG_ARRAY(hw, reg, offset, value) \ argument
149 reg + ((offset) << 2)),\
154 e1000_translate_register_82542(reg) + \
158 #define E1000_READ_REG_ARRAY(hw, reg, offset) (\ argument
[all …]
/illumos-gate/usr/src/uts/common/io/
H A Dsock_conf.c71 smod_register(const smod_reg_t *reg) in smod_register() argument
79 if (reg->smod_version != SOCKMOD_VERSION || in smod_register()
80 reg->smod_dc_version != SOCK_DC_VERSION || in smod_register()
81 reg->smod_uc_version != SOCK_UC_VERSION) { in smod_register()
84 reg->smod_name); in smod_register()
90 if ((smodp = smod_find(reg->smod_name)) != NULL) { in smod_register()
97 smodp = smod_create(reg->smod_name); in smod_register()
98 smodp->smod_version = reg->smod_version; in smod_register()
103 ASSERT(reg->__smod_priv != NULL); in smod_register()
105 reg->__smod_priv->smodp_sock_create_func; in smod_register()
[all …]
/illumos-gate/usr/src/uts/common/io/igb/
H A De1000_osdep.h113 #define E1000_WRITE_REG(hw, reg, value) \ argument
115 (uint32_t *)((uintptr_t)(hw)->hw_addr + reg), (value))
117 #define E1000_READ_REG(hw, reg) \ argument
119 (uint32_t *)((uintptr_t)(hw)->hw_addr + reg))
121 #define E1000_WRITE_REG_ARRAY(hw, reg, offset, value) \ argument
123 (uint32_t *)((uintptr_t)(hw)->hw_addr + reg + ((offset) << 2)), \
126 #define E1000_READ_REG_ARRAY(hw, reg, offset) \ argument
128 (uint32_t *)((uintptr_t)(hw)->hw_addr + reg + ((offset) << 2)))
130 #define E1000_WRITE_REG_ARRAY_DWORD(a, reg, offset, value) \ argument
131 E1000_WRITE_REG_ARRAY(a, reg, offset, value)
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/illumos-gate/usr/src/uts/common/io/ntxn/
H A Dniu.c99 unm_niu_gbe_phy_read(struct unm_adapter_s *adapter, long reg, in unm_niu_gbe_phy_read() argument
134 address.reg_addr = (unm_crbword_t)reg; in unm_niu_gbe_phy_read()
402 unm_niu_gb_drop_crc_t reg; in unm_niu_set_promiscuous_mode() local
443 &reg, 4); in unm_niu_set_promiscuous_mode()
446 reg.drop_gb0 = data; in unm_niu_set_promiscuous_mode()
449 reg.drop_gb1 = data; in unm_niu_set_promiscuous_mode()
452 reg.drop_gb2 = data; in unm_niu_set_promiscuous_mode()
455 reg.drop_gb3 = data; in unm_niu_set_promiscuous_mode()
462 &reg, 4); in unm_niu_set_promiscuous_mode()
549 long reg; in unm_niu_xg_set_promiscuous_mode() local
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/illumos-gate/usr/src/lib/libc/sparc/gen/
H A Dmakectxt.c57 greg_t *reg; in makecontext() local
64 reg = ucp->uc_mcontext.gregs; in makecontext()
65 reg[REG_PC] = (greg_t)func; in makecontext()
66 reg[REG_nPC] = reg[REG_PC] + 0x4; in makecontext()
96 *tsp++ = reg[REG_O0 + argno] = va_arg(ap, long); in makecontext()
103 reg[REG_SP] = (greg_t)sp - STACK_BIAS; /* sp (when done) */ in makecontext()
104 reg[REG_O7] = (greg_t)resumecontext - 8; /* return pc */ in makecontext()
110 greg_t *reg; in __makecontext_v2() local
117 reg = ucp->uc_mcontext.gregs; in __makecontext_v2()
118 reg[REG_PC] = (greg_t)func; in __makecontext_v2()
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