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Searched refs:pil (Results 1 – 25 of 49) sorted by relevance

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/illumos-gate/usr/src/uts/i86pc/os/
H A Dintr.c539 hilevel_intr_prolog(struct cpu *cpu, uint_t pil, uint_t oldpil, struct regs *rp) in hilevel_intr_prolog() argument
546 ASSERT(pil > LOCK_LEVEL); in hilevel_intr_prolog()
548 if (pil == CBE_HIGH_PIL) { in hilevel_intr_prolog()
573 ASSERT(nestpil < pil); in hilevel_intr_prolog()
600 smt_begin_intr(pil); in hilevel_intr_prolog()
605 mcpu->pil_high_start[pil - (LOCK_LEVEL + 1)] = now; in hilevel_intr_prolog()
607 ASSERT((cpu->cpu_intr_actv & (1 << pil)) == 0); in hilevel_intr_prolog()
609 if (pil == 15) { in hilevel_intr_prolog()
622 cpu->cpu_intr_actv |= (1 << pil); in hilevel_intr_prolog()
637 hilevel_intr_epilog(struct cpu *cpu, uint_t pil, uint_t oldpil, uint_t vecnum) in hilevel_intr_epilog() argument
[all …]
/illumos-gate/usr/src/uts/i86pc/io/apix/
H A Dapix_intr.c230 apix_do_softint_prolog(struct cpu *cpu, uint_t pil, uint_t oldpil, in apix_do_softint_prolog() argument
238 ASSERT(pil > mcpu->mcpu_pri && pil > cpu->cpu_base_spl); in apix_do_softint_prolog()
240 atomic_and_32((uint32_t *)&mcpu->mcpu_softinfo.st_pending, ~(1 << pil)); in apix_do_softint_prolog()
242 mcpu->mcpu_pri = pil; in apix_do_softint_prolog()
259 mcpu->intrstat[pil][0] += intrtime; in apix_do_softint_prolog()
285 smt_begin_intr(pil); in apix_do_softint_prolog()
290 ASSERT((cpu->cpu_intr_actv & (1 << pil)) == 0); in apix_do_softint_prolog()
291 cpu->cpu_intr_actv |= (1 << pil); in apix_do_softint_prolog()
296 it->t_pil = (uchar_t)pil; in apix_do_softint_prolog()
297 it->t_pri = (pri_t)pil + intr_pri; in apix_do_softint_prolog()
[all …]
/illumos-gate/usr/src/uts/sun4/io/
H A Divintr.c184 add_ivintr(uint_t inum, uint_t pil, intrfunc intr_handler, in add_ivintr() argument
189 if (inum >= MAXIVNUM || pil > PIL_MAX) in add_ivintr()
202 if (iv_p->iv_pil == pil) { in add_ivintr()
215 new_iv_p->iv_pil = (ushort_t)pil; in add_ivintr()
229 rem_ivintr(uint_t inum, uint_t pil) in rem_ivintr() argument
233 if (inum >= MAXIVNUM || pil > PIL_MAX) in rem_ivintr()
240 if (iv_p->iv_pil == pil) in rem_ivintr()
265 add_softintr(uint_t pil, softintrfunc intr_handler, caddr_t intr_arg1, in add_softintr() argument
270 if (pil > PIL_MAX) in add_softintr()
277 iv_p->iv_pil = (ushort_t)pil; in add_softintr()
[all …]
H A Debus.c746 uint32_t pil; member
813 ebus_name_to_pil[i].pil); in ebus_intr_ops()
815 hdlp->ih_pri = ebus_name_to_pil[i].pil; in ebus_intr_ops()
831 string, ebus_device_type_to_pil[i].pil); in ebus_intr_ops()
833 hdlp->ih_pri = ebus_device_type_to_pil[i].pil; in ebus_intr_ops()
/illumos-gate/usr/src/uts/sun4v/promif/
H A Dpromif_mon.c66 PIL_DECL(pil); in promif_exit_to_mon()
68 PIL_SET7(pil); in promif_exit_to_mon()
82 PIL_REST(pil); in promif_exit_to_mon()
93 PIL_DECL(pil); in promif_enter_mon()
95 PIL_SET7(pil); in promif_enter_mon()
140 PIL_REST(pil); in promif_enter_mon()
/illumos-gate/usr/src/uts/sun4/ml/
H A Dinterrupt.S50 ! %g4 - pil
53 ! Grab the first or list head intr_vec_t off the intr_head[pil]
55 ! intr_head[pil] to next intr_vec_t on the list and clear softint
61 sll %g4, CPTRSHIFT, %g5 ! %g5 = offset to the pil entry
63 add %g6, %g5, %g6 ! %g6 = &cpu->m_cpu.intr_head[pil]
64 ldn [%g6], %g2 ! %g2 = cpu->m_cpu.intr_head[pil]
80 stn %g3, [%g6] ! update cpu->m_cpu.intr_head[pil]
82 stn %g0, [%g5 + %g6] ! clear cpu->m_cpu.intr_tail[pil]
84 sll %g5, %g4, %g5 ! %g5 = 1 << pil
85 wr %g5, CLEAR_SOFTINT ! clear interrupt on this pil
[all …]
H A Dxc.S75 rdpr %pil, %g4
/illumos-gate/usr/src/psm/stand/boot/sparc/common/
H A Dsparcv9_subr.S227 rdpr %pil, %o1 ! get current pil
228 wrpr %o0, %pil
263 rdpr %pil, %o1 ! get current pil
267 wrpr %o0, %pil
269 mov %o1, %o0 ! return the old pil
/illumos-gate/usr/src/uts/sun4/os/
H A Dintr.c336 no_ivintr(struct regs *rp, int inum, int pil) in no_ivintr() argument
340 inum, pil); in no_ivintr()
348 intr_dequeue_req(uint_t pil, uint64_t inum) in intr_dequeue_req() argument
363 next = mcpu->intr_head[pil]; in intr_dequeue_req()
380 mcpu->intr_head[pil] = next_iv; /* head */ in intr_dequeue_req()
383 mcpu->intr_tail[pil] = prev; /* tail */ in intr_dequeue_req()
387 if (mcpu->intr_head[pil] == NULL) { in intr_dequeue_req()
388 clr = 1 << pil; in intr_dequeue_req()
389 if (pil == PIL_14) in intr_dequeue_req()
846 create_softint(uint_t pil, uint_t (*func)(caddr_t, caddr_t), caddr_t arg1) in create_softint() argument
[all …]
/illumos-gate/usr/src/uts/sun4/sys/
H A Divintr.h118 extern int add_ivintr(uint_t inum, uint_t pil, intrfunc intr_handler,
120 extern int rem_ivintr(uint_t inum, uint_t pil);
122 extern uint64_t add_softintr(uint_t pil, softintrfunc intr_handler,
126 extern int update_softint_pri(uint64_t softint_id, uint_t pil);
/illumos-gate/usr/src/uts/sparc/v9/ml/
H A Dsparcv9_subr.S64 rdpr %pil, %o1; /* get current PIL */ \
68 wrpr %g0, PIL_MAX, %pil; /* freeze CPU_BASE_SPL */ \
73 wrpr %g0, %o2, %pil; \
85 rdpr %pil, %o1; /* get current PIL */ \
89 wrpr %g0, level, %pil; /* use chose value */ \
102 rdpr %pil, %o1; /* get current PIL */ \
103 wrpr %g0, PIL_MAX, %pil; /* freeze CPU_BASE_SPL */ \
108 wrpr %g0, %o2, %pil; \
120 rdpr %pil, %o1; /* get current PIL */ \
121 wrpr %g0, level, %pil; \
H A Dlock_prim.S175 rdpr %pil, %o3 ! %o3 = current pil
176 cmp %o3, %o1 ! is current pil high enough?
177 bl,a,pt %icc, 1f ! if not, write %pil in delay
178 wrpr %g0, %o1, %pil
185 sth %o3, [%o2] ! delay - save original pil
205 wrpr %g0, %o2, %pil
/illumos-gate/usr/src/uts/intel/os/
H A Dsmt.c187 smt_intr_alloc_pil(uint_t pil) in smt_intr_alloc_pil() argument
189 ASSERT(pil <= PIL_MAX); in smt_intr_alloc_pil()
191 if (empty_pil == pil) in smt_intr_alloc_pil()
380 pil_needs_kick(uint_t pil) in pil_needs_kick() argument
382 return (pil != empty_pil); in pil_needs_kick()
386 smt_begin_intr(uint_t pil) in smt_begin_intr() argument
391 ASSERT(pil <= PIL_MAX); in smt_begin_intr()
401 if (atomic_inc_64_nv(&smt->cs_intr_depth) == 1 && pil_needs_kick(pil)) { in smt_begin_intr()
/illumos-gate/usr/src/uts/sun4u/io/pci/
H A Dpci_ib.c511 ib_new_ino_pil(ib_t *ib_p, ib_ino_t ino_num, uint_t pil, ih_t *ih_p) in ib_new_ino_pil() argument
528 ino_p->ino_lopil = pil; in ib_new_ino_pil()
532 ipil_p->ipil_pil = pil; in ib_new_ino_pil()
543 if (ino_p->ino_lopil > pil) in ib_new_ino_pil()
544 ino_p->ino_lopil = pil; in ib_new_ino_pil()
554 ushort_t pil = ipil_p->ipil_pil; in ib_delete_ino_pil() local
571 if ((--ino_p->ino_ipil_size) && (ino_p->ino_lopil == pil)) { in ib_delete_ino_pil()
572 for (next = ino_p->ino_ipil_p, pil = next->ipil_pil; in ib_delete_ino_pil()
575 if (pil > next->ipil_pil) in ib_delete_ino_pil()
576 pil = next->ipil_pil; in ib_delete_ino_pil()
[all …]
/illumos-gate/usr/src/uts/sun4/io/px/
H A Dpx_ib.c485 px_ib_new_ino_pil(px_ib_t *ib_p, devino_t ino_num, uint_t pil, px_ih_t *ih_p) in px_ib_new_ino_pil() argument
496 ipil_p->ipil_pil = pil; in px_ib_new_ino_pil()
507 if ((ino_p->ino_lopil == 0) || (ino_p->ino_lopil > pil)) in px_ib_new_ino_pil()
508 ino_p->ino_lopil = pil; in px_ib_new_ino_pil()
517 ushort_t pil = ipil_p->ipil_pil; in px_ib_delete_ino_pil() local
535 if ((--ino_p->ino_ipil_size) && (ino_p->ino_lopil == pil)) { in px_ib_delete_ino_pil()
536 for (next = ino_p->ino_ipil_p, pil = next->ipil_pil; in px_ib_delete_ino_pil()
539 if (pil > next->ipil_pil) in px_ib_delete_ino_pil()
540 pil = next->ipil_pil; in px_ib_delete_ino_pil()
546 ino_p->ino_lopil = pil; in px_ib_delete_ino_pil()
[all …]
H A Dpx_ib.h142 extern px_ino_pil_t *px_ib_ino_locate_ipil(px_ino_t *ino_p, uint_t pil);
145 uint_t pil, px_ih_t *ih_p);
158 devino_t ino, uint_t pil, uint_t new_intr_state,
/illumos-gate/usr/src/uts/sun4v/io/
H A Dcnex.c611 int rv, idx, pil; in cnex_add_intr() local
684 for (idx = 0, pil = PIL_3; idx < CNEX_MAX_DEVS; idx++) { in cnex_add_intr()
686 pil = cnex_class_to_intr[idx].pil; in cnex_add_intr()
692 if (add_ivintr(iinfo->icookie, pil, (intrfunc)cnex_intr_wrapper, in cnex_add_intr()
734 (void) rem_ivintr(iinfo->icookie, pil); in cnex_add_intr()
800 int rv, idx, pil; in cnex_rem_intr() local
878 for (idx = 0, pil = PIL_3; idx < CNEX_MAX_DEVS; idx++) { in cnex_rem_intr()
880 pil = cnex_class_to_intr[idx].pil; in cnex_rem_intr()
888 (void) rem_ivintr(iinfo->icookie, pil); in cnex_rem_intr()
/illumos-gate/usr/src/uts/sun4v/ml/
H A Dmach_interrupt.S416 rdpr %pil, %g4
440 rdpr %pil, %g4
600 rdpr %pil, %g4
612 rdpr %pil, %g4
H A Dmach_locore.S930 rdpr %pil, %o0 ! compare old pil level
931 cmp %l6, %o0 ! with current pil level
932 movg %xcc, %o0, %l6 ! if current is lower, drop old pil
977 ! set %pil from max(old pil, cpu_base_spl)
983 wrpr %g0, %l0, %pil
/illumos-gate/usr/src/uts/sun4u/sys/pci/
H A Dpci_ib.h198 extern ib_ino_pil_t *ib_new_ino_pil(ib_t *ib_p, ib_ino_t ino_num, uint_t pil,
202 extern ib_ino_pil_t *ib_ino_locate_ipil(ib_ino_info_t *ino_p, uint_t pil);
215 extern uint32_t ib_register_intr(ib_t *ib_p, ib_mondo_t mondo, uint_t pil,
/illumos-gate/usr/src/uts/sun4u/ml/
H A Dmach_locore.S765 rdpr %pil, %o0 ! compare old pil level
766 cmp %l6, %o0 ! with current pil level
767 movg %xcc, %o0, %l6 ! if current is lower, drop old pil
812 ! set %pil from max(old pil, cpu_base_spl)
818 wrpr %g0, %l0, %pil
/illumos-gate/usr/src/cmd/intrd/
H A Dintrd.pl251 $stat{$cpu}{ivecs}{$cookie}{pil} = $intrcfg->{pil};
511 $dltivec{pil} = $newivec->{pil};
583 $newivecs->{$inum}{pil} = $ivec->{pil};
/illumos-gate/usr/src/uts/sun4u/sys/
H A Dmachsystm.h233 extern void intr_enqueue_req(uint_t pil, uint64_t inum);
234 extern void intr_dequeue_req(uint_t pil, uint64_t inum);
/illumos-gate/usr/src/uts/sun4u/io/
H A Dsysiosbus.c224 uint32_t *pil, int32_t ign);
1573 spurious_cntr = &intr_info->softsp->spurious_cntrs[intr_info->pil]; in sbus_intr_wrapper()
1614 else if (intr_info->pil >= LOCK_LEVEL) { in sbus_intr_wrapper()
1617 intr_info->pil); in sbus_intr_wrapper()
1797 sbus_arg->pil = hdlp->ih_pri; in sbus_add_intr_impl()
1980 uint32_t *pil, int32_t ign) in sbus_xlate_intrs() argument
2028 if (*pil == 0) { in sbus_xlate_intrs()
2034 *pil = SOC_PRIORITY; in sbus_xlate_intrs()
2037 *pil = interrupt_priorities[ino]; in sbus_xlate_intrs()
2046 ddi_driver_name(rdip), *intr, ino, *pil, level)); in sbus_xlate_intrs()
/illumos-gate/usr/src/uts/sun4v/sys/
H A Dcnex.h49 uint32_t pil; /* PIL for device class */ member

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