Lines Matching refs:pil
50 ! %g4 - pil
53 ! Grab the first or list head intr_vec_t off the intr_head[pil]
55 ! intr_head[pil] to next intr_vec_t on the list and clear softint
61 sll %g4, CPTRSHIFT, %g5 ! %g5 = offset to the pil entry
63 add %g6, %g5, %g6 ! %g6 = &cpu->m_cpu.intr_head[pil]
64 ldn [%g6], %g2 ! %g2 = cpu->m_cpu.intr_head[pil]
80 stn %g3, [%g6] ! update cpu->m_cpu.intr_head[pil]
82 stn %g0, [%g5 + %g6] ! clear cpu->m_cpu.intr_tail[pil]
84 sll %g5, %g4, %g5 ! %g5 = 1 << pil
85 wr %g5, CLEAR_SOFTINT ! clear interrupt on this pil
103 ldn [%g6 + %g3], %g6 ! %g6=cpu->m_cpu.intr_head[pil]
104 stna %g6, [%g5 + TRAP_ENT_F2]%asi ! trap_f2 = intr_head[pil]
106 ldn [%g6 + %g3], %g6 ! %g6=cpu->m_cpu.intr_tail[pil]
107 stna %g6, [%g5 + TRAP_ENT_F3]%asi ! trap_f3 = intr_tail[pil]
108 stna %g4, [%g5 + TRAP_ENT_F4]%asi ! trap_f4 = pil
127 ! %g3 - pil
128 ! %g4 - initial pil for handler
130 ! figure which handler to run and which %pil it starts at
134 mov %g4, %g3 ! %g3 = %g4, pil
136 bg,a,pt %xcc, 3f ! branch if pil > LOCK_LEVEL
202 rdpr %pil, %o3; \
269 rdpr %pil, os3; \
300 rdpr %pil, os3; \
534 ! higher effective pil because a higher-level interrupt may have
537 wrpr %g0, DISP_LEVEL, %pil
669 wrpr %g0, DISP_LEVEL, %pil ! up from cpu_base_spl
677 ! Restore %pil before calling serve_intr() again. We must check
678 ! CPU_BASE_SPL and set %pil to max(our-pil, CPU_BASE_SPL)
683 wrpr %g0, %o4, %pil
905 stn %l2, [%o3 + %o4] ! save onfault label for pil %o2
907 stn %l3, [%o3 + %o4] ! save lofault data for pil %o2
917 stn %l2, [%o3 + %o4] ! save on_trap label for pil %o2
1211 ! ASSERT(cpu.cpu_m.pil_high_start[pil - (LOCK_LEVEL + 1)] != 0)
1345 wrpr %g0, %o2, %pil ! enable interrupts
1378 ldub [%o0 + T_PIL], %o0 ! return saved pil
1382 rdpr %pil, %o0
1384 wrpr %g0, PIL_MAX, %pil ! disable interrupts (1-15)
1389 wrpr %o0, %pil
1482 add %l4, INTR_HEAD, %l6 ! %l6 = &cpu->m_cpu.intr_head[pil]
1483 stn %i0, [%l6 + %l0] ! cpu->m_cpu.intr_head[pil] = iv
1486 ! Write %set_softint with (1<<pil) to cause a "pil" level trap
1489 sll %l1, %l2, %l1 ! %l1 = 1 << pil
1490 wr %l1, SET_SOFTINT ! trigger required pil softint
1503 ! %g2 - pil
1519 sll %g2, CPTRSHIFT, %g7 ! %g7 = offset to pil entry
1521 ldn [%g6 + %g7], %g5 ! %g5 = cpu->m_cpu.intr_tail[pil]
1625 ! CPU softint priority queue, and compose the final softint pil mask.
1631 mov %g0, %g1 ! %g1 = 0, initialize pil mask to 0
1669 add %g4, INTR_HEAD, %g6 ! %g6 = &cpu->m_cpu.intr_head[pil]
1670 stn %g3, [%g6 + %g7] ! cpu->m_cpu.intr_head[pil] = iv
1683 stna %g1, [%g5 + TRAP_ENT_F1]%asi ! trap_f1 = pil mask
1685 ldn [%g6 + %g7], %g6 ! %g6=cpu->m_cpu.intr_head[pil]
1686 stna %g6, [%g5 + TRAP_ENT_F2]%asi ! trap_f2 = intr_head[pil]
1688 ldn [%g6 + %g7], %g6 ! %g6=cpu->m_cpu.intr_tail[pil]
1689 stna %g6, [%g5 + TRAP_ENT_F3]%asi ! trap_f3 = intr_tail[pil]
1690 stna %g2, [%g5 + TRAP_ENT_F4]%asi ! trap_f4 = pil
1696 sll %g6, %g2, %g6 ! %g6 = 1 << pil
1697 or %g1, %g6, %g1 ! %g1 |= (1 << pil), pil mask
1701 wr %g1, SET_SOFTINT ! triggered one or more pil softints
1705 ! no_ivintr: arguments: rp, inum (%g1), pil (%g2 == 0)
1956 ! ASSERT(%pil <= LOCK_LEVEL)
1958 rdpr %pil, %o1
1990 ! %o1 = pil
1996 wrpr %g0, PIL_MAX, %pil ! make this easy -- block normal intrs
2022 ! Increment cpu_m.intrstat[pil][0]. Calculate elapsed time since
2023 ! cpu_m.intrstat[pil][1], which is either when the interrupt was
2025 ! update cpu_m.intrstat[pil][1] to match [0].
2030 add %o3, %o5, %o3 ! %o3 = cpu_m.intrstat[pil][0]
2034 ldx [%o3 + 8], %o4 ! %o4 = cpu_m.intrstat[pil][1]
2038 ld [%o5 + CPU_BASE_SPL], %o2 ! restore %pil to the greater
2039 cmp %o2, %o1 ! of either our pil %o1 or
2042 wrpr %g0, %o2, %pil