| /illumos-gate/usr/src/uts/common/io/nxge/npi/ |
| H A D | npi_fflp.c | 237 (tctl.bits.ldw.stat != TCAM_CTL_RWC_RWC_STAT)) { in npi_fflp_tcam_check_completion()
257 (tctl.bits.ldw.match != TCAM_CTL_RWC_RWC_MATCH)) { in npi_fflp_tcam_check_completion()
314 tctl.bits.ldw.location = location; in npi_fflp_tcam_entry_invalidate()
315 tctl.bits.ldw.rwc = TCAM_CTL_RWC_TCAM_WR; in npi_fflp_tcam_entry_invalidate()
361 tctl.bits.ldw.rwc = TCAM_CTL_RWC_TCAM_CMP; in npi_fflp_tcam_entry_match()
373 if (tctl_stat.bits.ldw.match == TCAM_CTL_RWC_RWC_MATCH) { in npi_fflp_tcam_entry_match()
374 return (uint32_t)(tctl_stat.bits.ldw.location); in npi_fflp_tcam_entry_match()
406 tctl.bits.ldw.location = location; in npi_fflp_tcam_entry_read()
407 tctl.bits.ldw.rwc = TCAM_CTL_RWC_TCAM_RD; in npi_fflp_tcam_entry_read()
476 tctl.bits.ldw.location = location; in npi_fflp_tcam_entry_write()
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| H A D | npi_rxdma.c | 242 page_vld.bits.ldw.page0 = 0; in npi_rxdma_cfg_logical_page_disable()
245 page_vld.bits.ldw.page1 = 0; in npi_rxdma_cfg_logical_page_disable()
289 page_vld.bits.ldw.page0 = 0; in npi_rxdma_cfg_logical_page()
292 page_vld.bits.ldw.page1 = 0; in npi_rxdma_cfg_logical_page()
301 page_vld.bits.ldw.page0 = 1; in npi_rxdma_cfg_logical_page()
308 page_vld.bits.ldw.page1 = 1; in npi_rxdma_cfg_logical_page()
312 page_vld.bits.ldw.func = pg_cfg->func_num; in npi_rxdma_cfg_logical_page()
319 page_mask.bits.ldw.mask = pg_cfg->mask >> LOG_PAGE_ADDR_SHIFT; in npi_rxdma_cfg_logical_page()
320 page_value.bits.ldw.value = pg_cfg->value >> LOG_PAGE_ADDR_SHIFT; in npi_rxdma_cfg_logical_page()
321 page_reloc.bits.ldw.relo = pg_cfg->reloc >> LOG_PAGE_ADDR_SHIFT; in npi_rxdma_cfg_logical_page()
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| H A D | npi_zcp.c | 322 val.qw0.bits.ldw.rdc_tbl_offset = in npi_zcp_tt_static_entry()
323 sflow->qw0.bits.ldw.rdc_tbl_offset; in npi_zcp_tt_static_entry()
327 val.qw0.bits.ldw.buf_size = in npi_zcp_tt_static_entry()
328 sflow->qw0.bits.ldw.buf_size; in npi_zcp_tt_static_entry()
332 val.qw0.bits.ldw.num_buf = sflow->qw0.bits.ldw.num_buf; in npi_zcp_tt_static_entry()
336 val.qw0.bits.ldw.ulp_end = sflow->qw0.bits.ldw.ulp_end; in npi_zcp_tt_static_entry()
340 val.qw1.bits.ldw.ulp_end = sflow->qw1.bits.ldw.ulp_end; in npi_zcp_tt_static_entry()
344 val.qw1.bits.ldw.ulp_end_en = in npi_zcp_tt_static_entry()
345 sflow->qw1.bits.ldw.ulp_end_en; in npi_zcp_tt_static_entry()
349 val.qw1.bits.ldw.unmap_all_en = in npi_zcp_tt_static_entry()
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| H A D | npi_vir.c | 294 if (!sr.bits.ldw.tas) { in npi_dev_func_sr_init()
300 if (!sr.bits.ldw.sr) { in npi_dev_func_sr_init()
302 sr.bits.ldw.sr |= NPI_DEV_SR_LOCK_ST_FREE; in npi_dev_func_sr_init()
304 sr.bits.ldw.tas = 0; in npi_dev_func_sr_init()
311 sr.bits.ldw.sr)); in npi_dev_func_sr_init()
316 sr.bits.ldw)); in npi_dev_func_sr_init()
317 status = NPI_VIR_TAS_BUSY(sr.bits.ldw.funcid); in npi_dev_func_sr_init()
348 if (!sr.bits.ldw.tas) { in npi_dev_func_sr_lock_enter()
353 state = sr.bits.ldw.sr & NPI_DEV_SR_LOCK_ST_MASK; in npi_dev_func_sr_lock_enter()
359 sr.bits.ldw.sr |= (NPI_DEV_SR_LOCK_ST_BUSY | in npi_dev_func_sr_lock_enter()
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| H A D | npi_txdma.c | 258 mode32.bits.ldw.mode32 = 1; in npi_txdma_mode32_set()
260 mode32.bits.ldw.mode32 = 0; in npi_txdma_mode32_set()
322 vld.bits.ldw.func = cfgp->func_num; in npi_txdma_log_page_set()
347 vld.bits.ldw.func, in npi_txdma_log_page_set()
400 vld.bits.ldw.func = cfgp->func_num; in npi_txdma_log_page_get()
409 cfgp->func_num = vld.bits.ldw.func; in npi_txdma_log_page_get()
418 cfgp->valid = vld.bits.ldw.page0; in npi_txdma_log_page_get()
426 cfgp->valid = vld.bits.ldw.page1; in npi_txdma_log_page_get()
932 cs.bits.ldw.rst = 1; in npi_txdma_channel_control()
947 cs.bits.ldw.rst = 1; in npi_txdma_channel_control()
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| H A D | npi_txc.c | 432 cntl.bits.ldw.txc_enabled = 1; in npi_txc_global_enable()
459 cntl.bits.ldw.txc_enabled = 0; in npi_txc_global_disable()
870 if ((ecc.bits.ldw.correct_error) || (ecc.bits.ldw.uncorrect_error)) { in npi_txc_ro_states_get()
887 ecc.bits.ldw.ecc_address = 0; in npi_txc_ro_states_get()
888 ecc.bits.ldw.correct_error = 0; in npi_txc_ro_states_get()
889 ecc.bits.ldw.uncorrect_error = 0; in npi_txc_ro_states_get()
890 ecc.bits.ldw.clr_st = 1; in npi_txc_ro_states_get()
910 ctl.bits.ldw.clr_fail_state = 1; in npi_txc_ro_states_get()
962 if ((ecc.bits.ldw.correct_error) || (ecc.bits.ldw.uncorrect_error)) { in npi_txc_sf_states_get()
973 ecc.bits.ldw.ecc_address = 0; in npi_txc_sf_states_get()
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| H A D | npi_rxdma.h | 190 uint32_t ldw; member
192 uint32_t ldw;
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| H A D | npi_zcp.h | 117 } while ((ram_ctl.bits.ldw.busy != 0) && (cnt > 0));\
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| /illumos-gate/usr/src/uts/common/io/nxge/ |
| H A D | nxge_txc.c | 202 if (txc_control.bits.ldw.txc_enabled == 0) { in nxge_txc_tdc_bind()
346 if (istatus.bits.ldw.port0_int_status) { in nxge_txc_handle_sys_errors()
349 err_status = istatus.bits.ldw.port0_int_status; in nxge_txc_handle_sys_errors()
353 if (istatus.bits.ldw.port1_int_status) { in nxge_txc_handle_sys_errors()
356 err_status = istatus.bits.ldw.port1_int_status; in nxge_txc_handle_sys_errors()
360 if (istatus.bits.ldw.port2_int_status) { in nxge_txc_handle_sys_errors()
363 err_status = istatus.bits.ldw.port2_int_status; in nxge_txc_handle_sys_errors()
367 if (istatus.bits.ldw.port3_int_status) { in nxge_txc_handle_sys_errors()
370 err_status = istatus.bits.ldw.port3_int_status; in nxge_txc_handle_sys_errors()
488 istatus.bits.ldw.port0_int_status = err_status; in nxge_txc_handle_port_errors()
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| H A D | nxge_zcp.c | 334 zcps.bits.ldw.rrfifo_urun = 1; in nxge_zcp_inject_err()
336 zcps.bits.ldw.rspfifo_uc_err = 1; in nxge_zcp_inject_err()
338 zcps.bits.ldw.stat_tbl_perr = 1; in nxge_zcp_inject_err()
340 zcps.bits.ldw.dyn_tbl_perr = 1; in nxge_zcp_inject_err()
342 zcps.bits.ldw.buf_tbl_perr = 1; in nxge_zcp_inject_err()
346 zcps.bits.ldw.cfifo_ecc0 = 1; in nxge_zcp_inject_err()
349 zcps.bits.ldw.cfifo_ecc1 = 1; in nxge_zcp_inject_err()
352 zcps.bits.ldw.cfifo_ecc2 = 1; in nxge_zcp_inject_err()
355 zcps.bits.ldw.cfifo_ecc3 = 1; in nxge_zcp_inject_err()
363 zcps.bits.ldw.rrfifo_orun = 1; in nxge_zcp_inject_err()
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| H A D | nxge_txdma.c | 961 head_index = tx_head.bits.ldw.head; in nxge_txdma_reclaim()
962 head_wrap = tx_head.bits.ldw.wrap; in nxge_txdma_reclaim()
1180 if (!rs && cs.bits.ldw.mk) { in nxge_tx_intr()
1270 intr_dbg.bits.ldw.nack_pref = 1; in nxge_txdma_channel_disable()
1452 intr_dbg.bits.ldw.nack_pref = 1; in nxge_txdma_stop_inj_err()
1804 head_index = tx_head.bits.ldw.head; in nxge_txdma_channel_hung()
1805 head_wrap = tx_head.bits.ldw.wrap; in nxge_txdma_channel_hung()
1989 intr_dbg.bits.ldw.nack_pref = 1; in nxge_txdma_fixup_hung_channel()
2120 printf("\n\thead index %d", hdl.bits.ldw.head); in nxge_txdma_regs_dump()
2123 printf("\n\ttail index %d\n", kick.bits.ldw.tail); in nxge_txdma_regs_dump()
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| H A D | nxge_fm.c | 632 if (hash_log.bits.ldw.pio_err) { in nxge_fm_ereport()
724 zcp_stats.errlog.state_mach.bits.ldw.state; in nxge_fm_ereport()
801 bits.ldw.ecc_address, in nxge_fm_ereport()
804 bits.ldw.ro_ecc_data0, in nxge_fm_ereport()
807 bits.ldw.ro_ecc_data1, in nxge_fm_ereport()
810 bits.ldw.ro_ecc_data2, in nxge_fm_ereport()
813 bits.ldw.ro_ecc_data3, in nxge_fm_ereport()
816 bits.ldw.ro_ecc_data4, in nxge_fm_ereport()
848 bits.ldw.ecc_address, in nxge_fm_ereport()
851 bits.ldw.sf_ecc_data0, in nxge_fm_ereport()
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| H A D | nxge_rxdma.c | 584 rdc_desc.rcr_threshold = cfgb_p->bits.ldw.pthres; in nxge_enable_rxdma_channel()
590 rdc_desc.rcr_timeout = cfgb_p->bits.ldw.timeout; in nxge_enable_rxdma_channel()
591 rdc_desc.rcr_timeout_enable = cfgb_p->bits.ldw.entout; in nxge_enable_rxdma_channel()
1139 entry_p->bits.ldw.pkt_buf_addr)); in nxge_dump_rcr_entry()
1171 printf("nxge_rxdma_regs_dump: rbr len %d \n", rbr_stat.bits.ldw.qlen); in nxge_rxdma_regs_dump()
1824 mgm.bits.ldw.arm = 1; in nxge_rx_intr()
1825 mgm.bits.ldw.timer = ldgp->ldg_timer; in nxge_rx_intr()
1888 mgm.bits.ldw.arm = 0; in nxge_rx_intr()
1906 mgm.bits.ldw.arm = 1; in nxge_rx_intr()
1907 mgm.bits.ldw.timer = ldgp->ldg_timer; in nxge_rx_intr()
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| H A D | nxge_fzc.c | 355 red.bits.ldw.win = RXDMA_RED_WINDOW_DEFAULT; in nxge_init_fzc_rdc()
356 red.bits.ldw.thre = in nxge_init_fzc_rdc()
358 red.bits.ldw.win_syn = RXDMA_RED_WINDOW_DEFAULT; in nxge_init_fzc_rdc()
359 red.bits.ldw.thre_sync = in nxge_init_fzc_rdc()
364 red.bits.ldw.thre_sync, in nxge_init_fzc_rdc()
365 red.bits.ldw.thre_sync)); in nxge_init_fzc_rdc()
549 cfg.valid = rbrp->page_valid.bits.ldw.page0; in nxge_init_fzc_rxdma_channel_pages()
563 cfg.valid = rbrp->page_valid.bits.ldw.page1; in nxge_init_fzc_rxdma_channel_pages()
575 rbrp->page_hdl.bits.ldw.handle); in nxge_init_fzc_rxdma_channel_pages()
600 red.bits.ldw.win = RXDMA_RED_WINDOW_DEFAULT; in nxge_init_fzc_rxdma_channel_red()
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| H A D | nxge_fflp.c | 1501 tcam_ptr.match_action.bits.ldw.rdctbl = rdc_grp; in nxge_add_tcam_entry()
1502 tcam_ptr.match_action.bits.ldw.offset = offset; in nxge_add_tcam_entry()
1503 tcam_ptr.match_action.bits.ldw.tres = in nxge_add_tcam_entry()
1506 tcam_ptr.match_action.bits.ldw.disc = 1; in nxge_add_tcam_entry()
1568 tcam_ptr.match_action.bits.ldw.rdctbl = nxgep->class_config.mac_rdcgrp; in nxge_tcam_handle_ip_fragment()
1569 tcam_ptr.match_action.bits.ldw.offset = 0; /* use the default */ in nxge_tcam_handle_ip_fragment()
1570 tcam_ptr.match_action.bits.ldw.tres = in nxge_tcam_handle_ip_fragment()
2153 if (vlan_err.bits.ldw.m_err || vlan_err.bits.ldw.err) { in nxge_fflp_handle_sys_errors()
2157 portn, vlan_err.bits.ldw.addr, in nxge_fflp_handle_sys_errors()
2158 vlan_err.bits.ldw.data)); in nxge_fflp_handle_sys_errors()
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| H A D | nxge_hw.c | 432 if (estat.bits.ldw.smx) { in nxge_syserr_intr()
436 } else if (estat.bits.ldw.mac) { in nxge_syserr_intr()
445 } else if (estat.bits.ldw.ipp) { in nxge_syserr_intr()
449 } else if (estat.bits.ldw.zcp) { in nxge_syserr_intr()
454 } else if (estat.bits.ldw.tdmc) { in nxge_syserr_intr()
462 } else if (estat.bits.ldw.rdmc) { in nxge_syserr_intr()
467 } else if (estat.bits.ldw.txc) { in nxge_syserr_intr()
471 } else if ((nxgep->niu_type != N2_NIU) && estat.bits.ldw.peu) { in nxge_syserr_intr()
475 } else if (estat.bits.ldw.meta1) { in nxge_syserr_intr()
479 } else if (estat.bits.ldw.meta2) { in nxge_syserr_intr()
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| H A D | nxge_intr.c | 1094 mgm.bits.ldw.arm = 1; in nxge_hio_ldgimgn()
1095 mgm.bits.ldw.timer = group->ldg_timer; in nxge_hio_ldgimgn()
1097 mgm.bits.ldw.arm = 0; in nxge_hio_ldgimgn()
1098 mgm.bits.ldw.timer = 0; in nxge_hio_ldgimgn()
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| H A D | nxge_send.c | 746 sop_tx_desc_p->bits.ldw.sad = dma_ioaddr & 0xffffffff; in nxge_start()
755 tmp_desc_p->bits.ldw.sad = dma_ioaddr & 0xffffffff; in nxge_start()
989 kick.bits.ldw.wrap = in nxge_start()
991 kick.bits.ldw.tail = in nxge_start()
1034 kick.bits.ldw.wrap = tx_ring_p->wr_index_wrap; in nxge_start()
1035 kick.bits.ldw.tail = (uint16_t)tx_ring_p->wr_index; in nxge_start()
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| /illumos-gate/usr/src/uts/common/sys/nxge/ |
| H A D | nxge_hw.h | 104 } ldw; member
132 } ldw; member
181 } ldw; member
230 } ldw; member
263 uint32_t ldw; member
291 } ldw; member
329 } ldw; member
362 } ldw; member
389 } ldw; member
428 } ldw; member
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| H A D | nxge_txc_hw.h | 55 } ldw; member
76 } ldw; member
115 } ldw; member
145 } ldw; member
180 } ldw; member
208 } ldw; member
233 } ldw; member
260 } ldw; member
300 } ldw; member
327 } ldw; member
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| H A D | nxge_zcp_hw.h | 95 } ldw; member
140 } ldw; member
203 } ldw; member
247 } ldw; member
268 } ldw; member
322 } ldw; member
353 } ldw; member
376 } ldw; member
397 } ldw; member
418 } ldw; member
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| H A D | nxge_txdma_hw.h | 85 } ldw; member
136 } ldw; member
218 } ldw; member
259 } ldw; member
288 } ldw; member
357 } ldw; member
457 } ldw; member
497 } ldw; member
524 } ldw; member
549 } ldw; member
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| H A D | nxge_rxdma_hw.h | 58 } ldw; member
97 } ldw; member
118 } ldw; member
151 } ldw; member
185 } ldw; member
218 } ldw; member
278 } ldw; member
343 } ldw; member
388 } ldw; member
428 } ldw; member
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| H A D | nxge_fflp_hw.h | 97 } ldw; member
127 } ldw; member
164 } ldw; member
264 } ldw; member
324 } ldw; member
367 } ldw; member
445 } ldw; member
477 } ldw; member
516 } ldw; member
543 } ldw; member
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