584 	rdc_desc.rcr_threshold = cfgb_p->bits.ldw.pthres;  in nxge_enable_rxdma_channel()
590 		rdc_desc.rcr_timeout = cfgb_p->bits.ldw.timeout;  in nxge_enable_rxdma_channel()
591 		rdc_desc.rcr_timeout_enable = cfgb_p->bits.ldw.entout;  in nxge_enable_rxdma_channel()
1139 	    entry_p->bits.ldw.pkt_buf_addr));  in nxge_dump_rcr_entry()
1171 	printf("nxge_rxdma_regs_dump: rbr len %d \n", rbr_stat.bits.ldw.qlen);  in nxge_rxdma_regs_dump()
1824 				mgm.bits.ldw.arm = 1;  in nxge_rx_intr()
1825 				mgm.bits.ldw.timer = ldgp->ldg_timer;  in nxge_rx_intr()
1888 				mgm.bits.ldw.arm = 0;  in nxge_rx_intr()
1906 				mgm.bits.ldw.arm = 1;  in nxge_rx_intr()
1907 				mgm.bits.ldw.timer = ldgp->ldg_timer;  in nxge_rx_intr()
2122 		rcr_cfg_b.bits.ldw.entout = 1;  in nxge_rx_pkts()
2123 		rcr_cfg_b.bits.ldw.timeout = rcr_p->intr_timeout;  in nxge_rx_pkts()
2124 		rcr_cfg_b.bits.ldw.pthres = rcr_p->intr_threshold;  in nxge_rx_pkts()
2130 	cs.bits.ldw.pktread = npkt_read;  in nxge_rx_pkts()
2131 	cs.bits.ldw.ptrread = nrcr_read;  in nxge_rx_pkts()
2800 		cs.bits.ldw.pktread = 0;  in nxge_disable_poll()
2801 		cs.bits.ldw.ptrread = 0;  in nxge_disable_poll()
2829 				mgm.bits.ldw.arm = 1;  in nxge_disable_poll()
2830 				mgm.bits.ldw.timer = ldgp->ldg_timer;  in nxge_disable_poll()
3424 	rcfgb_p->bits.ldw.bufsz0 = rbrp->pkt_buf_size0;  in nxge_map_rxdma_channel_cfg_ring()
3425 	rcfgb_p->bits.ldw.vld0 = 1;  in nxge_map_rxdma_channel_cfg_ring()
3426 	rcfgb_p->bits.ldw.bufsz1 = rbrp->pkt_buf_size1;  in nxge_map_rxdma_channel_cfg_ring()
3427 	rcfgb_p->bits.ldw.vld1 = 1;  in nxge_map_rxdma_channel_cfg_ring()
3428 	rcfgb_p->bits.ldw.bufsz2 = rbrp->pkt_buf_size2;  in nxge_map_rxdma_channel_cfg_ring()
3429 	rcfgb_p->bits.ldw.vld2 = 1;  in nxge_map_rxdma_channel_cfg_ring()
3430 	rcfgb_p->bits.ldw.bksize = nxgep->rx_bksize_code;  in nxge_map_rxdma_channel_cfg_ring()
3455 	kick_p->bits.ldw.bkadd = rbrp->rbb_max;  in nxge_map_rxdma_channel_cfg_ring()
3550 	rbrp->page_valid.bits.ldw.page0 = 1;  in nxge_map_rxdma_channel_cfg_ring()
3551 	rbrp->page_valid.bits.ldw.page1 = 1;  in nxge_map_rxdma_channel_cfg_ring()
3629 	cfgb_p->bits.ldw.pthres = rcrp->intr_threshold;  in nxge_map_rxdma_channel_cfg_ring()
3630 	cfgb_p->bits.ldw.timeout = rcrp->intr_timeout;  in nxge_map_rxdma_channel_cfg_ring()
3631 	cfgb_p->bits.ldw.entout = 1;  in nxge_map_rxdma_channel_cfg_ring()
3651 	cfig1_p->bits.ldw.mbaddr_h = dmaaddrp;  in nxge_map_rxdma_channel_cfg_ring()
3658 	cfig2_p->bits.ldw.mbaddr = (dmaaddrp >> RXDMA_CFIG2_MBADDR_L_SHIFT);  in nxge_map_rxdma_channel_cfg_ring()
3667 	cfig2_p->bits.ldw.full_hdr = rcrp->full_hdr_flag;  in nxge_map_rxdma_channel_cfg_ring()
3674 				cfig2_p->bits.ldw.offset =  in nxge_map_rxdma_channel_cfg_ring()
3676 				cfig2_p->bits.ldw.offset256 = 0;  in nxge_map_rxdma_channel_cfg_ring()
3682 				cfig2_p->bits.ldw.offset =  in nxge_map_rxdma_channel_cfg_ring()
3684 				cfig2_p->bits.ldw.offset256 = 1;  in nxge_map_rxdma_channel_cfg_ring()
3687 				cfig2_p->bits.ldw.offset = SW_OFFSET_NO_OFFSET;  in nxge_map_rxdma_channel_cfg_ring()
3688 				cfig2_p->bits.ldw.offset256 = 0;  in nxge_map_rxdma_channel_cfg_ring()
3691 		cfig2_p->bits.ldw.offset = rcrp->sw_priv_hdr_len;  in nxge_map_rxdma_channel_cfg_ring()
4455 	if (stat.bits.ldw.id_mismatch) {  in nxge_rxdma_handle_sys_errors()
4462 	if ((stat.bits.ldw.zcp_eop_err) || (stat.bits.ldw.ipp_eop_err)) {  in nxge_rxdma_handle_sys_errors()
4465 			if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT0) ||  in nxge_rxdma_handle_sys_errors()
4466 			    (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT0)) {  in nxge_rxdma_handle_sys_errors()
4468 				zcp_err_status = stat.bits.ldw.zcp_eop_err;  in nxge_rxdma_handle_sys_errors()
4469 				ipp_err_status = stat.bits.ldw.ipp_eop_err;  in nxge_rxdma_handle_sys_errors()
4473 			if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT1) ||  in nxge_rxdma_handle_sys_errors()
4474 			    (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT1)) {  in nxge_rxdma_handle_sys_errors()
4476 				zcp_err_status = stat.bits.ldw.zcp_eop_err;  in nxge_rxdma_handle_sys_errors()
4477 				ipp_err_status = stat.bits.ldw.ipp_eop_err;  in nxge_rxdma_handle_sys_errors()
4481 			if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT2) ||  in nxge_rxdma_handle_sys_errors()
4482 			    (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT2)) {  in nxge_rxdma_handle_sys_errors()
4484 				zcp_err_status = stat.bits.ldw.zcp_eop_err;  in nxge_rxdma_handle_sys_errors()
4485 				ipp_err_status = stat.bits.ldw.ipp_eop_err;  in nxge_rxdma_handle_sys_errors()
4489 			if ((stat.bits.ldw.zcp_eop_err & FIFO_EOP_PORT3) ||  in nxge_rxdma_handle_sys_errors()
4490 			    (stat.bits.ldw.ipp_eop_err & FIFO_EOP_PORT3)) {  in nxge_rxdma_handle_sys_errors()
4492 				zcp_err_status = stat.bits.ldw.zcp_eop_err;  in nxge_rxdma_handle_sys_errors()
4493 				ipp_err_status = stat.bits.ldw.ipp_eop_err;  in nxge_rxdma_handle_sys_errors()
4842 			cdfs.bits.ldw.id_mismatch = (1 << nxgep->mac.portnum);  in nxge_rxdma_inject_err()
4844 			cdfs.bits.ldw.zcp_eop_err = (1 << nxgep->mac.portnum);  in nxge_rxdma_inject_err()
4846 			cdfs.bits.ldw.ipp_eop_err = (1 << nxgep->mac.portnum);  in nxge_rxdma_inject_err()