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Searched refs:bus_p (Results 1 – 25 of 25) sorted by relevance

/illumos-gate/usr/src/uts/common/io/pciex/
H A Dpcie.c507 static void pcie_print_bus(pcie_bus_t *bus_p);
776 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); in pcie_hpintr_enable() local
779 if (PCIE_IS_PCIE_HOTPLUG_ENABLED(bus_p)) { in pcie_hpintr_enable()
781 } else if (PCIE_IS_PCI_HOTPLUG_ENABLED(bus_p)) { in pcie_hpintr_enable()
796 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); in pcie_hpintr_disable() local
799 if (PCIE_IS_PCIE_HOTPLUG_ENABLED(bus_p)) { in pcie_hpintr_disable()
801 } else if (PCIE_IS_PCI_HOTPLUG_ENABLED(bus_p)) { in pcie_hpintr_disable()
827 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); in pcie_open() local
838 if ((bus_p->bus_soft_state == PCI_SOFT_STATE_OPEN_EXCL) || in pcie_open()
840 (bus_p->bus_soft_state != PCI_SOFT_STATE_CLOSED))) { in pcie_open()
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H A Dpcie_fault.c109 pcie_bus_t *bus_p, boolean_t bdg);
110 static void pf_pcix_regs_gather(pf_data_t *pfd_p, pcie_bus_t *bus_p);
111 static void pf_pcie_regs_gather(pf_data_t *pfd_p, pcie_bus_t *bus_p);
112 static void pf_pci_regs_gather(pf_data_t *pfd_p, pcie_bus_t *bus_p);
169 pf_eh_enter(pcie_bus_t *bus_p) in pf_eh_enter() argument
175 pf_eh_exit(pcie_bus_t *bus_p) in pf_eh_exit() argument
177 pcie_bus_t *rbus_p = PCIE_DIP2BUS(bus_p->bus_rp_dip); in pf_eh_exit()
357 pcie_bus_t *bus_p; in pf_dispatch() local
362 if (!(bus_p = pf_is_ready(dip))) in pf_dispatch()
377 (bus_p->bus_bdf == rid) || in pf_dispatch()
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H A Dpciev.c53 static void pcie_cache_domain_info(pcie_bus_t *bus_p);
54 static void pcie_uncache_domain_info(pcie_bus_t *bus_p);
64 pcie_bus_t *bus_p; in pcie_find_dip_by_bdf() local
69 bus_p = PCIE_DIP2BUS(dip); in pcie_find_dip_by_bdf()
70 if (bus_p && (bus_p->bus_bdf == bdf)) in pcie_find_dip_by_bdf()
72 if (bus_p) { in pcie_find_dip_by_bdf()
74 if ((bus_num >= bus_p->bus_bus_range.lo && in pcie_find_dip_by_bdf()
75 bus_num <= bus_p->bus_bus_range.hi) || in pcie_find_dip_by_bdf()
76 bus_p->bus_bus_range.hi == 0) in pcie_find_dip_by_bdf()
129 pcie_cache_domain_info(pcie_bus_t *bus_p) in pcie_cache_domain_info() argument
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H A Dpcieb.c485 pcie_bus_t *bus_p = PCIE_DIP2UPBUS(devi); in pcieb_attach() local
486 ddi_acc_handle_t config_handle = bus_p->bus_cfg_hdl; in pcieb_attach()
500 if (!(PCIE_IS_BDG(bus_p))) { in pcieb_attach()
511 if (PCIE_CAP_GET(16, bus_p, PCIE_LINKCTL) & PCIE_LINKCTL_LINK_DISABLE) in pcieb_attach()
573 if (PCIE_IS_PCI_BDG(bus_p)) in pcieb_attach()
585 PCIEB_IS_41210_BRIDGE(bus_p->bus_dev_ven_id)) in pcieb_attach()
609 if (PCIE_IS_RP(bus_p)) in pcieb_attach()
1047 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); in pcieb_is_pcie_device_type() local
1049 if (PCIE_IS_SW(bus_p) || PCIE_IS_RP(bus_p) || PCIE_IS_PCI2PCIE(bus_p)) in pcieb_is_pcie_device_type()
1128 pcie_bus_t *bus_p = PCIE_DIP2UPBUS(dip); in pcieb_intr_init() local
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H A Dpcie_pwr.c842 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); in pcie_is_pcie() local
843 ASSERT(bus_p); in pcie_is_pcie()
844 return (bus_p->bus_pcie_off != 0); in pcie_is_pcie()
/illumos-gate/usr/src/uts/common/sys/
H A Dpciev.h132 #define PCIE_ASSIGNED_TO_FMA_DOM(bus_p) \ argument
133 (!PCIE_IS_BDG(bus_p) && PCIE_BUS2DOM(bus_p)->fmadom_count > 0)
134 #define PCIE_ASSIGNED_TO_NFMA_DOM(bus_p) \ argument
135 (!PCIE_IS_BDG(bus_p) && PCIE_BUS2DOM(bus_p)->nfmadom_count > 0)
136 #define PCIE_ASSIGNED_TO_ROOT_DOM(bus_p) \ argument
137 (PCIE_IS_BDG(bus_p) || PCIE_BUS2DOM(bus_p)->rootdom_count > 0)
138 #define PCIE_BDG_HAS_CHILDREN_FMA_DOM(bus_p) \ argument
139 (PCIE_IS_BDG(bus_p) && PCIE_BUS2DOM(bus_p)->fmadom_count > 0)
140 #define PCIE_BDG_HAS_CHILDREN_NFMA_DOM(bus_p) \ argument
141 (PCIE_IS_BDG(bus_p) && PCIE_BUS2DOM(bus_p)->nfmadom_count > 0)
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H A Dpcie_impl.h62 #define PCIE_BUS2DIP(bus_p) bus_p->bus_dip argument
63 #define PCIE_BUS2PFD(bus_p) PCIE_DIP2PFD(PCIE_BUS2DIP(bus_p)) argument
64 #define PCIE_BUS2DOM(bus_p) bus_p->bus_dom argument
70 #define PCIE_IS_PCIE(bus_p) (bus_p->bus_pcie_off) argument
71 #define PCIE_IS_PCIX(bus_p) (bus_p->bus_pcix_off) argument
72 #define PCIE_IS_PCI(bus_p) (!PCIE_IS_PCIE(bus_p)) argument
73 #define PCIE_HAS_AER(bus_p) (bus_p->bus_aer_off) argument
75 #define PCIE_IS_ROOT(bus_p) (PCIE_IS_RC(bus_p) || PCIE_IS_RP(bus_p)) argument
89 #define PCIE_IS_RC(bus_p) \ argument
90 (bus_p->bus_dev_type == PCIE_PCIECAP_DEV_TYPE_RC_PSEUDO)
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/illumos-gate/usr/src/uts/intel/io/pciex/
H A Dpcieb_x86.c155 pcie_bus_t *bus_p = PCIE_DIP2UPBUS(dip); in pcieb_plat_msi_supported() local
157 vendor_id = bus_p->bus_dev_ven_id & 0xFFFF; in pcieb_plat_msi_supported()
158 device_id = bus_p->bus_dev_ven_id >> 16; in pcieb_plat_msi_supported()
208 pcie_bus_t *bus_p = PCIE_DIP2UPBUS(devi); in pcieb_init_osc() local
225 if (!pcie_is_osc(devi) && PCIE_IS_RP(bus_p) && PCIE_HAS_AER(bus_p)) in pcieb_init_osc()
468 pcie_bus_t *bus_p = PCIE_DIP2UPBUS(dip); in pcieb_intel_serr_workaround() local
469 ddi_acc_handle_t cfg_hdl = bus_p->bus_cfg_hdl; in pcieb_intel_serr_workaround()
470 uint16_t bdf = bus_p->bus_bdf; in pcieb_intel_serr_workaround()
475 vid = bus_p->bus_dev_ven_id & 0xFFFF; in pcieb_intel_serr_workaround()
476 did = bus_p->bus_dev_ven_id >> 16; in pcieb_intel_serr_workaround()
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H A Dpcie_acpi.c58 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); in pcie_acpi_osc() local
59 pcie_x86_priv_t *osc_p = (pcie_x86_priv_t *)bus_p->bus_plat_private; in pcie_acpi_osc()
222 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); in pcie_is_osc() local
223 pcie_x86_priv_t *osc_p = (pcie_x86_priv_t *)bus_p->bus_plat_private; in pcie_is_osc()
/illumos-gate/usr/src/uts/sparc/io/pciex/
H A Dpcie_sparc.c35 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); in pcie_init_plat() local
37 if (PCIE_IS_PCIE_BDG(bus_p)) { in pcie_init_plat()
38 bus_p->bus_pcie2pci_secbus = bus_p->bus_bdg_secbus; in pcie_init_plat()
47 bus_p->bus_pcie2pci_secbus = in pcie_init_plat()
60 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); in pcie_fini_plat() local
62 if (PCIE_IS_PCIE_BDG(bus_p)) in pcie_fini_plat()
63 bus_p->bus_pcie2pci_secbus = 0; in pcie_fini_plat()
H A Dpcieb_sparc.c201 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); in pcieb_attach_plx_workarounds() local
202 ddi_acc_handle_t config_handle = bus_p->bus_cfg_hdl; in pcieb_attach_plx_workarounds()
204 uint8_t dev_type = bus_p->bus_dev_type; in pcieb_attach_plx_workarounds()
205 uint16_t vendor_id = bus_p->bus_dev_ven_id & 0xFFFF; in pcieb_attach_plx_workarounds()
206 uint16_t device_id = bus_p->bus_dev_ven_id >> 16; in pcieb_attach_plx_workarounds()
213 (bus_p->bus_rev_id <= PXB_DEVICE_PLX_AA_REV)) in pcieb_attach_plx_workarounds()
215 bus_p->bus_hp_sup_modes = PCIE_NONE_HP_MODE; in pcieb_attach_plx_workarounds()
336 pcie_bus_t *bus_p = PCIE_DIP2BUS(pcieb->pcieb_dip); in plx_ro_disable() local
338 uint16_t device_id = bus_p->bus_dev_ven_id >> 16; in plx_ro_disable()
355 val = PCIE_CAP_GET(32, bus_p, PCIE_LINKCAP); in plx_ro_disable()
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/illumos-gate/usr/src/uts/common/io/pciex/hotplug/
H A Dpciehpc.c711 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); in pciehpc_intr() local
731 if (bus_p->bus_hp_curr_mode != PCIE_NATIVE_HP_MODE) { in pciehpc_intr()
740 bus_p->bus_pcie_off + PCIE_SLOTSTS); in pciehpc_intr()
754 bus_p->bus_pcie_off + PCIE_SLOTSTS, status); in pciehpc_intr()
785 bus_p->bus_pcie_off + PCIE_SLOTCTL); in pciehpc_intr()
791 pciehpc_reg_put16(ctrl_p, bus_p->bus_pcie_off + in pciehpc_intr()
845 bus_p->bus_pcie_off + PCIE_SLOTCTL); in pciehpc_intr()
848 pciehpc_reg_put16(ctrl_p, bus_p->bus_pcie_off + in pciehpc_intr()
980 pcie_bus_t *bus_p = PCIE_DIP2BUS(ctrl_p->hc_dip); in pciehpc_get_slot_state() local
988 bus_p->bus_pcie_off + PCIE_SLOTCTL); in pciehpc_get_slot_state()
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H A Dpcie_hp.c217 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); in pcie_hp_init() local
221 if (PCIE_IS_PCIE_HOTPLUG_CAPABLE(bus_p)) { in pcie_hp_init()
224 } else if (PCIE_IS_PCI_HOTPLUG_CAPABLE(bus_p)) { in pcie_hp_init()
264 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); in pcie_hp_uninit() local
292 if (PCIE_IS_PCIE_HOTPLUG_ENABLED(bus_p)) in pcie_hp_uninit()
294 else if (PCIE_IS_PCI_HOTPLUG_ENABLED(bus_p)) in pcie_hp_uninit()
306 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); in pcie_hp_intr() local
309 if (PCIE_IS_PCIE_HOTPLUG_ENABLED(bus_p)) in pcie_hp_intr()
311 else if (PCIE_IS_PCI_HOTPLUG_ENABLED(bus_p)) in pcie_hp_intr()
472 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); in pcie_hp_create_occupant_props() local
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H A Dpcishpc.c137 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); in pcishpc_init() local
174 pci_config_get32(bus_p->bus_cfg_hdl, i)); in pcishpc_init()
841 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); in pcishpc_create_controller() local
857 bus_p->bus_hp_curr_mode = PCIE_PCI_HP_MODE; in pcishpc_create_controller()
939 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); in pcishpc_destroy_controller() local
953 bus_p->bus_hp_curr_mode = PCIE_NONE_HP_MODE; in pcishpc_destroy_controller()
1887 pcie_bus_t *bus_p = PCIE_DIP2BUS(ctrl_p->hc_dip); in pcishpc_set_slot_name() local
1918 slot_p->hs_phy_slot_num = pci_config_get8(bus_p->bus_cfg_hdl, in pcishpc_set_slot_name()
2363 pcie_bus_t *bus_p = PCIE_DIP2BUS(ctrl_p->hc_dip); in pcishpc_read_reg() local
2366 pci_config_put8(bus_p->bus_cfg_hdl, in pcishpc_read_reg()
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/illumos-gate/usr/src/uts/sun4u/io/pciex/
H A Dpci_cfgacc_4u.c63 pcie_bus_t *bus_p; in pci_cfgacc_get() local
67 bus_p = PCIE_DIP2DOWNBUS(dip); in pci_cfgacc_get()
68 ASSERT(bus_p != NULL); in pci_cfgacc_get()
70 base_addr = bus_p->bus_cfgacc_base; in pci_cfgacc_get()
97 pcie_bus_t *bus_p; in pci_cfgacc_set() local
100 bus_p = PCIE_DIP2DOWNBUS(dip); in pci_cfgacc_set()
101 ASSERT(bus_p != NULL); in pci_cfgacc_set()
103 base_addr = bus_p->bus_cfgacc_base; in pci_cfgacc_set()
/illumos-gate/usr/src/uts/sun4v/io/pciex/
H A Dpci_cfgacc_4v.c68 pcie_bus_t *bus_p; in pci_cfgacc_get() local
73 bus_p = PCIE_DIP2DOWNBUS(dip); in pci_cfgacc_get()
74 ASSERT(bus_p != NULL); in pci_cfgacc_get()
76 devhdl = bus_p->bus_cfgacc_base; in pci_cfgacc_get()
89 pcie_bus_t *bus_p; in pci_cfgacc_set() local
94 bus_p = PCIE_DIP2DOWNBUS(dip); in pci_cfgacc_set()
95 ASSERT(bus_p != NULL); in pci_cfgacc_set()
97 devhdl = bus_p->bus_cfgacc_base; in pci_cfgacc_set()
/illumos-gate/usr/src/uts/common/sys/hotplug/pci/
H A Dpcie_hp.h95 #define PCIE_IS_PCIE_HOTPLUG_CAPABLE(bus_p) \ argument
96 ((bus_p->bus_hp_sup_modes & PCIE_ACPI_HP_MODE) || \
97 (bus_p->bus_hp_sup_modes & PCIE_NATIVE_HP_MODE))
99 #define PCIE_IS_PCI_HOTPLUG_CAPABLE(bus_p) \ argument
100 (bus_p->bus_hp_sup_modes & PCIE_PCI_HP_MODE)
102 #define PCIE_IS_PCIE_HOTPLUG_ENABLED(bus_p) \ argument
103 ((bus_p->bus_hp_curr_mode == PCIE_ACPI_HP_MODE) || \
104 (bus_p->bus_hp_curr_mode == PCIE_NATIVE_HP_MODE))
106 #define PCIE_IS_PCI_HOTPLUG_ENABLED(bus_p) \ argument
107 (bus_p->bus_hp_curr_mode & PCIE_PCI_HP_MODE)
/illumos-gate/usr/src/uts/i86pc/io/pciex/
H A Dpcie_x86.c44 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); in pcie_init_plat() local
45 bus_p->bus_plat_private = in pcie_init_plat()
52 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); in pcie_fini_plat() local
54 kmem_free(bus_p->bus_plat_private, sizeof (pcie_x86_priv_t)); in pcie_fini_plat()
H A Dnpe.c964 pcie_bus_t *bus_p; in npe_initchild() local
1062 bus_p = PCIE_DIP2BUS(child); in npe_initchild()
1063 if (bus_p) { in npe_initchild()
1064 uint16_t device_id = (uint16_t)(bus_p->bus_dev_ven_id >> 16); in npe_initchild()
1065 uint16_t vendor_id = (uint16_t)(bus_p->bus_dev_ven_id & 0xFFFF); in npe_initchild()
1066 uint16_t rev_id = bus_p->bus_rev_id; in npe_initchild()
1072 bus_p->bus_aer_off = 0; in npe_initchild()
H A Dnpe_misc.c87 pcie_bus_t *bus_p = PCIE_DIP2BUS(child); in npe_disable_empty_bridges_workaround() local
94 ddi_get_child(child) == NULL && bus_p->bus_hp_sup_modes == in npe_disable_empty_bridges_workaround()
/illumos-gate/usr/src/uts/intel/io/pciex/hotplug/
H A Dpciehpc_acpi.c98 pcie_bus_t *bus_p = PCIE_DIP2BUS(ctrl_p->hc_dip); in pciehpc_update_ops() local
102 bus_p->bus_hp_sup_modes |= PCIE_ACPI_HP_MODE; in pciehpc_update_ops()
103 bus_p->bus_hp_curr_mode = PCIE_ACPI_HP_MODE; in pciehpc_update_ops()
233 pcie_bus_t *bus_p = PCIE_DIP2BUS(ctrl_p->hc_dip); in pciehpc_acpi_slotinfo_init() local
250 bus_p->bus_pcie_off + PCIE_SLOTCAP); in pciehpc_acpi_slotinfo_init()
326 pcie_bus_t *bus_p = PCIE_DIP2BUS(ctrl_p->hc_dip); in pciehpc_acpi_slot_poweron() local
346 bus_p->bus_pcie_off + PCIE_SLOTSTS); in pciehpc_acpi_slot_poweron()
365 bus_p->bus_pcie_off + PCIE_SLOTCTL); in pciehpc_acpi_slot_poweron()
398 pcie_bus_t *bus_p = PCIE_DIP2BUS(ctrl_p->hc_dip); in pciehpc_acpi_slot_poweroff() local
418 bus_p->bus_pcie_off + PCIE_SLOTSTS); in pciehpc_acpi_slot_poweroff()
/illumos-gate/usr/src/cmd/mdb/common/modules/genunix/
H A Dpci.c26 pcie_bus_match(const struct dev_info *devi, uintptr_t *bus_p) in pcie_bus_match() argument
29 *bus_p = (uintptr_t)devi->devi_bus.port_up.priv_p; in pcie_bus_match()
32 *bus_p = (uintptr_t)devi->devi_bus.port_down.priv_p; in pcie_bus_match()
/illumos-gate/usr/src/uts/sun4/io/px/
H A Dpx_fm.c72 pcie_bus_t *bus_p; in px_fm_attach() local
99 bus_p = PCIE_DIP2BUS(dip); in px_fm_attach()
100 bus_p->bus_rp_bdf = px_p->px_bdf; in px_fm_attach()
101 bus_p->bus_rp_dip = dip; in px_fm_attach()
811 pcie_bus_t *bus_p; in px_err_cfg_hdl_check() local
816 bus_p = PCIE_DIP2BUS(dip); in px_err_cfg_hdl_check()
825 (bus_p->bus_bdf == bdf))) ? DDI_FM_NONFATAL : DDI_FM_FATAL; in px_err_cfg_hdl_check()
978 pcie_bus_t *bus_p, *root_bus_p; in px_guest_panic() local
990 bus_p = PCIE_PFD2BUS(pfd_p); in px_guest_panic()
993 if (!PCIE_BUS2DOM(bus_p)->nfma_panic) in px_guest_panic()
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H A Dpx.c229 pcie_bus_t *bus_p; in px_attach() local
317 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); in px_attach() local
319 bus_p->bus_hp_sup_modes |= PCIE_NATIVE_HP_MODE; in px_attach()
363 bus_p = PCIE_DIP2BUS(dip); in px_attach()
364 bus_p->bus_cfgacc_base = px_lib_get_cfgacc_base(dip); in px_attach()
455 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); in px_detach() local
479 if (PCIE_IS_PCIE_HOTPLUG_ENABLED(bus_p)) in px_detach()
1449 pcie_bus_t *bus_p; in px_set_mps() local
1453 bus_p = PCIE_DIP2BUS(dip); in px_set_mps()
1455 bus_p->bus_mps = -1; in px_set_mps()
[all …]
/illumos-gate/usr/src/uts/sun4u/io/px/
H A Dpx_lib4u.c2614 pcie_bus_t *bus_p = PCIE_DIP2BUS(px_p->px_dip); in px_hp_intr_redist() local
2616 if (px_p && PCIE_IS_PCIE_HOTPLUG_ENABLED(bus_p)) { in px_hp_intr_redist()