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Searched refs:NXGE_REG_RD64 (Results 1 – 19 of 19) sorted by relevance

/illumos-gate/usr/src/uts/common/io/nxge/npi/
H A Dnpi_espc.c85 NXGE_REG_RD64(handle, ESPC_REG_ADDR(ESPC_PIO_STATUS_REG), &val); in npi_espc_eeprom_entry()
98 NXGE_REG_RD64(handle, ESPC_REG_ADDR(ESPC_PIO_STATUS_REG), &val); in npi_espc_eeprom_entry()
117 NXGE_REG_RD64(handle, ESPC_MAC_ADDR_0, &mac0.value); in npi_espc_mac_addr_get()
123 NXGE_REG_RD64(handle, ESPC_MAC_ADDR_1, &mac1.value); in npi_espc_mac_addr_get()
135 NXGE_REG_RD64(handle, ESPC_NUM_PORTS_MACS, &val); in npi_espc_num_ports_get()
147 NXGE_REG_RD64(handle, ESPC_NUM_PORTS_MACS, &val); in npi_espc_num_macs_get()
162 NXGE_REG_RD64(handle, ESPC_MOD_STR_LEN, &val); in npi_espc_model_str_get()
179 NXGE_REG_RD64(handle, ESPC_MOD_STR(j), &val); in npi_espc_model_str_get()
198 NXGE_REG_RD64(handle, ESPC_BD_MOD_STR_LEN, &val); in npi_espc_bd_model_str_get()
216 NXGE_REG_RD64(handle, ESPC_BD_MOD_STR(j), &val); in npi_espc_bd_model_str_get()
[all …]
H A Dnpi_vir.c119 NXGE_REG_RD64(handle, pio_offset[i], &value); in npi_vir_dump_pio_fzc_regs_one()
128 NXGE_REG_RD64(handle, fzc_pio_offset[i], &value); in npi_vir_dump_pio_fzc_regs_one()
154 NXGE_REG_RD64(handle, offset, &value); in npi_vir_dump_ldgnum()
183 NXGE_REG_RD64(handle, offset, &value); in npi_vir_dump_ldsv()
212 NXGE_REG_RD64(handle, offset, in npi_vir_dump_imask0()
226 NXGE_REG_RD64(handle, offset, in npi_vir_dump_imask0()
256 NXGE_REG_RD64(handle, offset, in npi_vir_dump_sid()
293 NXGE_REG_RD64(handle, DEV_FUNC_SR_REG, &sr.value); in npi_dev_func_sr_init()
347 NXGE_REG_RD64(handle, DEV_FUNC_SR_REG, &sr.value); in npi_dev_func_sr_lock_enter()
420 NXGE_REG_RD64(handle, DEV_FUNC_SR_REG, &sr.value); in npi_dev_func_sr_lock_free()
[all …]
H A Dnpi_txc.c162 NXGE_REG_RD64(handle, offset, &value); in npi_txc_dump_tdc_fzc_regs()
196 NXGE_REG_RD64(handle, txc_fzc_offset[i], &value); in npi_txc_dump_fzc_regs()
234 NXGE_REG_RD64(handle, offset, &value); in npi_txc_dump_port_fzc_regs()
395 NXGE_REG_RD64(handle, TXC_CONTROL_REG, &txc_control_p->value); in npi_txc_control()
434 NXGE_REG_RD64(handle, TXC_CONTROL_REG, &val); in npi_txc_global_enable()
461 NXGE_REG_RD64(handle, TXC_CONTROL_REG, &val); in npi_txc_global_disable()
527 NXGE_REG_RD64(handle, (TXC_TRAINING_REG & TXC_TRAINING_VECTOR_MASK), in npi_txc_training_get()
555 NXGE_REG_RD64(handle, TXC_CONTROL_REG, &val); in npi_txc_port_enable()
582 NXGE_REG_RD64(handle, TXC_CONTROL_REG, &val); in npi_txc_port_disable()
727 NXGE_REG_RD64(handle, TXC_MAX_REORDER_REG, &val); in npi_txc_reorder_set()
[all …]
H A Dnpi_zcp.c49 NXGE_REG_RD64(handle, ZCP_CONFIG_REG, &val); in npi_zcp_config()
77 NXGE_REG_RD64(handle, ZCP_CONFIG_REG, &val); in npi_zcp_config()
129 NXGE_REG_RD64(handle, ZCP_INT_MASK_REG, &val); in npi_zcp_iconfig()
166 NXGE_REG_RD64(handle, ZCP_INT_STAT_REG, &val); in npi_zcp_get_istatus()
196 NXGE_REG_RD64(handle, ZCP_CONFIG_REG, &val); in npi_zcp_set_dma_thresh()
630 NXGE_REG_RD64(handle, offset, &cfifo_reg.value); in npi_zcp_rest_cfifo_port()
710 NXGE_REG_RD64(handle, ZCP_RAM_DATA0_REG, &val->w0); in zcp_mem_read()
711 NXGE_REG_RD64(handle, ZCP_RAM_DATA1_REG, &val->w1); in zcp_mem_read()
712 NXGE_REG_RD64(handle, ZCP_RAM_DATA2_REG, &val->w2); in zcp_mem_read()
713 NXGE_REG_RD64(handle, ZCP_RAM_DATA3_REG, &val->w3); in zcp_mem_read()
[all …]
H A Dnpi_rxdma.c196 NXGE_REG_RD64(handle, rx_fzc_offset[i], &value); in npi_rxdma_dump_fzc_regs()
239 NXGE_REG_RD64(handle, valid_offset, &page_vld.value); in npi_rxdma_cfg_logical_page_disable()
285 NXGE_REG_RD64(handle, valid_offset, &page_vld.value); in npi_rxdma_cfg_logical_page()
875 NXGE_REG_RD64(handle, offset, &cnt->value); in npi_rxdma_red_discard_stat_get()
920 NXGE_REG_RD64(handle, offset, &cnt.value); in npi_rxdma_red_discard_oflow_clear()
1047 NXGE_REG_RD64(handle, pre_offset, &pre_log->value); in npi_rxdma_ring_perr_stat_get()
1048 NXGE_REG_RD64(handle, sha_offset, &sha_log->value); in npi_rxdma_ring_perr_stat_get()
1115 NXGE_REG_RD64(handle, pre_offset, &clr.value); in npi_rxdma_ring_perr_stat_clear()
1138 NXGE_REG_RD64(handle, sha_offset, &clr.value); in npi_rxdma_ring_perr_stat_clear()
1217 NXGE_REG_RD64(handle, d4_offset, &d4.value); in npi_rxdma_rdmc_memory_io()
[all …]
H A Dnpi_mac.h281 NXGE_REG_RD64(handle, XMAC_REG_ADDR((portn), (reg)), (val_p))
287 NXGE_REG_RD64(handle, BMAC_REG_ADDR((portn), (reg)), (val_p))
293 NXGE_REG_RD64(handle, PCS_REG_ADDR((portn), (reg)), (val_p))
299 NXGE_REG_RD64(handle, XPCS_ADDR((portn), (reg)), (val_p))
305 NXGE_REG_RD64(handle, MIF_ADDR((reg)), (val_p))
324 NXGE_REG_RD64(handle, MIF_ADDR((reg)), (val_p))
331 NXGE_REG_RD64(handle, ESR_ADDR((reg)), (val_p))
H A Dnpi_txc.h66 NXGE_REG_RD64(handle, \
74 NXGE_REG_RD64(handle, \
H A Dnpi_espc.h40 NXGE_REG_RD64(handle, ESPC_REG_ADDR(ESPC_PIO_STATUS_REG),\
H A Dnpi_zcp.h115 NXGE_REG_RD64(handle, ZCP_RAM_ACC_REG, &val);\
H A Dnpi_ipp.h122 NXGE_REG_RD64(handle, IPP_REG_ADDR(portn, reg), val);\
H A Dnpi_ipp.c122 NXGE_REG_RD64(handle, offset, &value); in npi_ipp_dump_regs()
148 NXGE_REG_RD64(handle, offset, &value); in npi_ipp_read_regs()
H A Dnpi_txdma.h133 NXGE_REG_RD64(handle, NXGE_TXLOG_OFFSET(reg, channel), val_p)
H A Dnpi_txdma.c189 NXGE_REG_RD64(handle, tx_fzc_offset[i], &value); in npi_txdma_dump_fzc_regs()
1849 NXGE_REG_RD64(handle, TDMC_INJ_PAR_ERR_REG, &inj.value); in npi_txdma_inj_par_error_update()
1862 NXGE_REG_RD64(handle, TDMC_INJ_PAR_ERR_REG, &inj.value); in npi_txdma_inj_par_error_get()
/illumos-gate/usr/src/uts/common/sys/nxge/
H A Dnxge_common_impl.h314 #define NXGE_REG_RD64(handle, offset, val_p) {\ macro
324 #define NXGE_REG_RD64(handle, offset, val_p) {\ macro
329 #define NXGE_REG_RD64(handle, offset, val_p) {\ macro
H A Dnxge_fflp_hw.h1098 NXGE_REG_RD64((handle), (offset), (val_p))
/illumos-gate/usr/src/uts/common/io/nxge/
H A Dnxge_zcp.c331 NXGE_REG_RD64(nxgep->npi_handle, ZCP_INT_STAT_TEST_REG, in nxge_zcp_inject_err()
H A Dnxge_txc.c558 NXGE_REG_RD64(nxgep->npi_handle, TXC_INT_STAT_DBG_REG, in nxge_txc_inject_err()
H A Dnxge_intr.c1077 NXGE_REG_RD64(nxge->npi_handle, offset, value); in nxge_hio_ldsv_im()
H A Dnxge_main.c1840 NXGE_REG_RD64(nxgep->npi_handle, reg, &regdata); in nxge_get64()