16f45ec7bSml29623 /* 26f45ec7bSml29623 * CDDL HEADER START 36f45ec7bSml29623 * 46f45ec7bSml29623 * The contents of this file are subject to the terms of the 56f45ec7bSml29623 * Common Development and Distribution License (the "License"). 66f45ec7bSml29623 * You may not use this file except in compliance with the License. 76f45ec7bSml29623 * 86f45ec7bSml29623 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 96f45ec7bSml29623 * or http://www.opensolaris.org/os/licensing. 106f45ec7bSml29623 * See the License for the specific language governing permissions 116f45ec7bSml29623 * and limitations under the License. 126f45ec7bSml29623 * 136f45ec7bSml29623 * When distributing Covered Code, include this CDDL HEADER in each 146f45ec7bSml29623 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 156f45ec7bSml29623 * If applicable, add the following below this CDDL HEADER, with the 166f45ec7bSml29623 * fields enclosed by brackets "[]" replaced with your own identifying 176f45ec7bSml29623 * information: Portions Copyright [yyyy] [name of copyright owner] 186f45ec7bSml29623 * 196f45ec7bSml29623 * CDDL HEADER END 206f45ec7bSml29623 */ 216f45ec7bSml29623 /* 2256d930aeSspeer * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 236f45ec7bSml29623 * Use is subject to license terms. 246f45ec7bSml29623 */ 256f45ec7bSml29623 266f45ec7bSml29623 #ifndef _NPI_ESPC_H 276f45ec7bSml29623 #define _NPI_ESPC_H 286f45ec7bSml29623 296f45ec7bSml29623 #ifdef __cplusplus 306f45ec7bSml29623 extern "C" { 316f45ec7bSml29623 #endif 326f45ec7bSml29623 336f45ec7bSml29623 #include <npi.h> 346f45ec7bSml29623 #include <nxge_espc_hw.h> 356f45ec7bSml29623 366f45ec7bSml29623 #define EPC_WAIT_RW_COMP(handle, val_p, comp_bit) {\ 376f45ec7bSml29623 uint32_t cnt = MAX_PIO_RETRIES;\ 386f45ec7bSml29623 do {\ 396f45ec7bSml29623 NXGE_DELAY(EPC_RW_WAIT);\ 406f45ec7bSml29623 NXGE_REG_RD64(handle, ESPC_REG_ADDR(ESPC_PIO_STATUS_REG),\ 416f45ec7bSml29623 val_p); cnt--;\ 426f45ec7bSml29623 } while (((val & comp_bit) == 0) && (cnt > 0));\ 436f45ec7bSml29623 } 446f45ec7bSml29623 456f45ec7bSml29623 /* ESPC specific errors */ 466f45ec7bSml29623 476f45ec7bSml29623 #define ESPC_EEPROM_ADDR_INVALID 0x51 486f45ec7bSml29623 #define ESPC_STR_LEN_INVALID 0x91 496f45ec7bSml29623 506f45ec7bSml29623 /* ESPC error return macros */ 516f45ec7bSml29623 526f45ec7bSml29623 #define NPI_ESPC_EEPROM_ADDR_INVALID ((ESPC_BLK_ID << 8) |\ 536f45ec7bSml29623 ESPC_EEPROM_ADDR_INVALID) 546f45ec7bSml29623 #define NPI_ESPC_EEPROM_WRITE_FAILED ((ESPC_BLK_ID << 8) | WRITE_FAILED) 556f45ec7bSml29623 #define NPI_ESPC_EEPROM_READ_FAILED ((ESPC_BLK_ID << 8) | READ_FAILED) 566f45ec7bSml29623 #define NPI_ESPC_OPCODE_INVALID ((ESPC_BLK_ID << 8) | OPCODE_INVALID) 576f45ec7bSml29623 #define NPI_ESPC_STR_LEN_INVALID ((ESPC_BLK_ID << 8) |\ 586f45ec7bSml29623 ESPC_STR_LEN_INVALID) 596f45ec7bSml29623 #define NPI_ESPC_PORT_INVALID ((ESPC_BLK_ID << 8) | PORT_INVALID) 606f45ec7bSml29623 6156d930aeSspeer /* EEPROM size, Fcode and VPD definitions */ 6256d930aeSspeer 6356d930aeSspeer /* 6456d930aeSspeer * VPD information. 6556d930aeSspeer */ 6656d930aeSspeer #define NXGE_VPD_MOD_LEN 32 6756d930aeSspeer #define NXGE_VPD_BD_MOD_LEN 16 6856d930aeSspeer #define NXGE_VPD_PHY_LEN 5 6956d930aeSspeer #define NXGE_VPD_VER_LEN 60 7056d930aeSspeer typedef struct _npi_vpd_info_t { 7156d930aeSspeer uint8_t mac_addr[ETHERADDRL]; 7256d930aeSspeer uint8_t num_macs; 7356d930aeSspeer char model[NXGE_VPD_MOD_LEN]; 7456d930aeSspeer char bd_model[NXGE_VPD_BD_MOD_LEN]; 7556d930aeSspeer char phy_type[NXGE_VPD_PHY_LEN]; 7656d930aeSspeer char ver[NXGE_VPD_VER_LEN]; 7756d930aeSspeer boolean_t ver_valid; 78*2e59129aSraghus boolean_t present; 7956d930aeSspeer } npi_vpd_info_t, *p_npi_vpd_info_t; 8056d930aeSspeer 8156d930aeSspeer #define NXGE_FCODE_ID_STR "FCode " 8256d930aeSspeer #define NXGE_FCODE_VER_STR_LEN 5 8356d930aeSspeer #define NXGE_VPD_VALID_VER_W 3 8456d930aeSspeer #define NXGE_VPD_VALID_VER_F 4 8556d930aeSspeer #define EXPANSION_ROM_SIZE 65536 8656d930aeSspeer #define FD_MODEL 0x01 8756d930aeSspeer #define FD_BD_MODEL 0x02 8856d930aeSspeer #define FD_MAC_ADDR 0x04 8956d930aeSspeer #define FD_NUM_MACS 0x08 9056d930aeSspeer #define FD_PHY_TYPE 0x10 9156d930aeSspeer #define FD_FW_VERSION 0x20 9256d930aeSspeer #define FD_ALL 0x3f 9356d930aeSspeer 946f45ec7bSml29623 npi_status_t npi_espc_pio_enable(npi_handle_t); 956f45ec7bSml29623 npi_status_t npi_espc_pio_disable(npi_handle_t); 966f45ec7bSml29623 npi_status_t npi_espc_eeprom_entry(npi_handle_t, io_op_t, 976f45ec7bSml29623 uint32_t, uint8_t *); 986f45ec7bSml29623 npi_status_t npi_espc_mac_addr_get(npi_handle_t, uint8_t *); 996f45ec7bSml29623 npi_status_t npi_espc_num_ports_get(npi_handle_t, uint8_t *); 1006f45ec7bSml29623 npi_status_t npi_espc_num_macs_get(npi_handle_t, uint8_t *); 1016f45ec7bSml29623 npi_status_t npi_espc_model_str_get(npi_handle_t, char *); 1026f45ec7bSml29623 npi_status_t npi_espc_bd_model_str_get(npi_handle_t, char *); 1036f45ec7bSml29623 npi_status_t npi_espc_phy_type_get(npi_handle_t, uint8_t *); 1046f45ec7bSml29623 npi_status_t npi_espc_port_phy_type_get(npi_handle_t, uint8_t *, 1056f45ec7bSml29623 uint8_t); 1066f45ec7bSml29623 npi_status_t npi_espc_max_frame_get(npi_handle_t, uint16_t *); 1076f45ec7bSml29623 npi_status_t npi_espc_version_get(npi_handle_t, uint16_t *); 1086f45ec7bSml29623 npi_status_t npi_espc_img_sz_get(npi_handle_t, uint16_t *); 1096f45ec7bSml29623 npi_status_t npi_espc_chksum_get(npi_handle_t, uint8_t *); 1106f45ec7bSml29623 npi_status_t npi_espc_intr_num_get(npi_handle_t, uint8_t *); 1116f45ec7bSml29623 uint32_t npi_espc_reg_get(npi_handle_t, int); 1126f45ec7bSml29623 void npi_espc_dump(npi_handle_t); 11356d930aeSspeer npi_status_t npi_espc_vpd_info_get(npi_handle_t, p_npi_vpd_info_t, uint32_t); 1146f45ec7bSml29623 1156f45ec7bSml29623 #ifdef __cplusplus 1166f45ec7bSml29623 } 1176f45ec7bSml29623 #endif 1186f45ec7bSml29623 1196f45ec7bSml29623 #endif /* _NPI_ESPC_H */ 120