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Searched refs:DMA_CSR_SLL (Results 1 – 6 of 6) sorted by relevance

/illumos-gate/usr/src/uts/common/io/nxge/npi/
H A Dnpi_rx_rd32.h119 offset += (((channel << 1) + 1) << DMA_CSR_SLL); in RXDMA_REG_READ32()
121 offset += (channel << DMA_CSR_SLL); in RXDMA_REG_READ32()
H A Dnpi_rx_rd64.h231 offset += (((channel << 1) + 1) << DMA_CSR_SLL); in RXDMA_REG_READ64()
233 offset += (channel << DMA_CSR_SLL); in RXDMA_REG_READ64()
H A Dnpi_rx_wr64.h209 offset += (((channel << 1) + 1) << DMA_CSR_SLL); in RXDMA_REG_WRITE64()
211 offset += (channel << DMA_CSR_SLL); in RXDMA_REG_WRITE64()
H A Dnpi_tx_rd64.h131 offset += ((channel << 1) << DMA_CSR_SLL); in TXDMA_REG_READ64()
133 offset += (channel << DMA_CSR_SLL); in TXDMA_REG_READ64()
H A Dnpi_tx_wr64.h131 offset += ((channel << 1) << DMA_CSR_SLL); in TXDMA_REG_WRITE64()
133 offset += (channel << DMA_CSR_SLL); in TXDMA_REG_WRITE64()
/illumos-gate/usr/src/uts/common/sys/nxge/
H A Dnxge_defs.h199 #define DMA_CSR_SLL 9 /* Used to calculate VR addresses */ macro
200 #define DMA_CSR_SIZE (1 << DMA_CSR_SLL) /* 512 */