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Searched refs:CSR_BASE (Results 1 – 6 of 6) sorted by relevance

/illumos-gate/usr/src/uts/common/io/iwp/
H A Diwp_hw.h961 #define CSR_BASE (0x0) macro
969 #define CSR_SW_VER (CSR_BASE+0x000)
970 #define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */
971 #define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
972 #define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */
973 #define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */
974 #define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack */
975 #define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */
976 #define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc */
977 #define CSR_GP_CNTRL (CSR_BASE+0x024)
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H A Diwp_eeprom.h194 #define CSR_EEPROM_REG (CSR_BASE+0x02c)
195 #define CSR_EEPROM_GP (CSR_BASE+0x030)
/illumos-gate/usr/src/uts/common/io/iwh/
H A Diwh_hw.h965 #define CSR_BASE (0x0) macro
973 #define CSR_SW_VER (CSR_BASE+0x000)
974 #define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */
975 #define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
976 #define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */
977 #define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */
978 #define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack */
979 #define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */
980 #define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc */
981 #define CSR_GP_CNTRL (CSR_BASE+0x024)
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H A Diwh_eeprom.h197 #define CSR_EEPROM_REG (CSR_BASE+0x02c)
198 #define CSR_EEPROM_GP (CSR_BASE+0x030)
/illumos-gate/usr/src/uts/common/io/iwk/
H A Diwk_hw.h1007 #define CSR_BASE (0x0) macro
1015 #define CSR_SW_VER (CSR_BASE+0x000)
1016 #define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */
1017 #define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
1018 #define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */
1019 #define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */
1020 #define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack */
1021 #define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */
1022 #define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc */
1023 #define CSR_GP_CNTRL (CSR_BASE+0x024)
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H A Diwk_eeprom.h279 #define CSR_EEPROM_REG (CSR_BASE+0x02c)
280 #define CSR_EEPROM_GP (CSR_BASE+0x030)