| /freebsd/contrib/llvm-project/compiler-rt/lib/builtins/arm/ |
| H A D | subsf3vfp.S | 22 vsub.f32 s0, s0, s1 26 vsub.f32 s14, s14, s15
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| H A D | subdf3vfp.S | 21 vsub.f64 d0, d0, d1 25 vsub.f64 d6, d6, d7
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| /freebsd/sys/arm/nvidia/drm2/ |
| H A D | tegra_fb.c | 270 int hsub, vsub, i; in tegra_drm_fb_create() local 278 vsub = drm_format_vert_chroma_subsampling(cmd->pixel_format); in tegra_drm_fb_create() 286 height /= vsub; in tegra_drm_fb_create()
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| /freebsd/lib/libc/arm/aeabi/ |
| H A D | aeabi_vfp_float.S | 184 vsub.f32 s0, s0, s1
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| H A D | aeabi_vfp_double.S | 197 vsub.f64 d0, d0, d1
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| /freebsd/contrib/llvm-project/clang/include/clang/Basic/ |
| H A D | arm_fp16.td | 124 def VSUBHS : SInst<"vsub", "111", "Sh">;
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| H A D | arm_neon.td | 334 def VSUB : IOpInst<"vsub", "...", 821 def SUB : IOpInst<"vsub", "...", "dQd", OP_SUB>; 1317 def SCALAR_SUB : SInst<"vsub", "111", "SlSUl">; 1710 def VSUBH : SOpInst<"vsub", "...", "hQh", OP_SUB>;
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| H A D | riscv_vector.td | 760 defm vsub : RVVIntBinBuiltinSet;
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| /freebsd/sys/dev/drm2/ |
| H A D | drm_crtc.c | 2247 int ret, hsub, vsub, num_planes, i; in framebuffer_check() local 2256 vsub = drm_format_vert_chroma_subsampling(r->pixel_format); in framebuffer_check() 2264 if (r->height == 0 || r->height % vsub) { in framebuffer_check() 2271 unsigned int height = r->height / (i != 0 ? vsub : 1); in framebuffer_check()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonDepInstrInfo.td | 39145 "$Vd32.qf16 = vsub($Vu32.hf,$Vv32.hf)", 39158 "$Vdd32.hf = vsub($Vu32.f8,$Vv32.f8)", 39171 "$Vd32.hf = vsub($Vu32.hf,$Vv32.hf)", 39184 "$Vd32.qf16 = vsub($Vu32.qf16,$Vv32.qf16)", 39197 "$Vd32.qf16 = vsub($Vu32.qf16,$Vv32.hf)", 39210 "$Vd32.qf32 = vsub($Vu32.qf32,$Vv32.qf32)", 39223 "$Vd32.qf32 = vsub($Vu32.qf32,$Vv32.sf)", 39236 "$Vd32.qf32 = vsub($Vu32.sf,$Vv32.sf)", 39249 "$Vdd32.sf = vsub($Vu32.bf,$Vv32.bf)", 39262 "$Vdd32.sf = vsub($Vu32.hf,$Vv32.hf)", [all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMInstrVFP.td | 466 IIC_fpALU64, "vsub", ".f64\t$Dd, $Dn, $Dm", 473 IIC_fpALU32, "vsub", ".f32\t$Sd, $Sn, $Sm", 484 IIC_fpALU16, "vsub", ".f16\t$Sd, $Sn, $Sm",
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| H A D | ARMInstrMVE.td | 2059 : MVE_VADDSUB_m<"vsub", VTI, 0b1, sub, int_arm_mve_sub_predicated>; 3717 : MVE_VADDSUB_fp_m<"vsub", 1, VTI, fsub, int_arm_mve_sub_predicated, IdentityVec>; 5205 : MVE_VADDSUB_qr_m<"vsub", VTI, 0b1, sub, int_arm_mve_sub_predicated>; 5356 defm MVE_VSUB_qr_f32 : MVE_VADDSUB_qr_f<"vsub", MVE_v4f32, 0b1, fsub, 5358 defm MVE_VSUB_qr_f16 : MVE_VADDSUB_qr_f<"vsub", MVE_v8f16, 0b1, fsub,
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| H A D | ARMInstrNEON.td | 5082 "vsub", "i", sub, 0>; 5083 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32", 5085 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32", 5087 def VSUBhd : N3VD<0, 0, 0b11, 0b1101, 0, IIC_VBIND, "vsub", "f16", 5090 def VSUBhq : N3VQ<0, 0, 0b11, 0b1101, 0, IIC_VBINQ, "vsub", "f16", 9134 def : NEONMnemonicAlias<"vsubq", "vsub">;
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | IntrinsicsRISCV.td | 1385 defm vsub : RISCVBinaryAAX;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrAVX10.td | 1028 defm VSUBBF16 : avx10_fp_binop_bf16<0x5C, "vsub", fsub, SchedWriteFAddSizes, 0>;
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| H A D | X86InstrAVX512.td | 5488 defm VSUB : avx512_binop_s_round<0x5C, "vsub", any_fsub, X86fsubs, X86fsubRnds, 5693 defm VSUB : avx512_fp_binop_p<0x5C, "vsub", any_fsub, fsub, HasAVX512, 5695 avx512_fp_binop_ph<0x5C, "vsub", any_fsub, fsub, SchedWriteFAddSizes>, 5696 avx512_fp_binop_p_round<0x5C, "vsub", X86fsubRnd, SchedWriteFAddSizes>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfoV.td | 1136 defm VSUB_V : VALU_IV_V_X<"vsub", 0b000010>;
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| H A D | RISCVInstrInfoVPseudos.td | 6193 // Match vrsub with 2 vector operands to vsub.vv by swapping operands. This
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