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Searched refs:vs2 (Results 1 – 23 of 23) sorted by relevance

/freebsd/crypto/openssl/crypto/perlasm/
H A Driscv.pm423 my $vs2 = read_vreg shift;
426 return ".word ".($template | ($vm << 25) | ($vs2 << 20) | ($vs1 << 15) | ($vd << 7));
433 my $vs2 = read_vreg shift;
436 return ".word ".($template | ($vm << 25) | ($vs2 << 20) | ($rs1 << 15) | ($vd << 7));
443 my $vs2 = read_vreg shift;
446 return ".word ".($template | ($vm << 25) | ($vs2 << 20) | ($vs1 << 15) | ($vd << 7));
453 my $vs2 = read_vreg shift;
456 return ".word ".($template | ($vm << 25) | ($vs2 << 20) | ($rs1 << 15) | ($vd << 7));
470 my $vs2 = read_vreg shift;
472 return ".word ".($template | ($vm << 25) | ($vs2 << 20) | ($vd << 7));
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/freebsd/sys/net/
H A Dvnet.c522 struct vnet_sysinit *vs, *vs2; in vnet_register_sysinit() local
530 TAILQ_FOREACH(vs2, &vnet_constructors, link) { in vnet_register_sysinit()
531 if (vs2->subsystem > vs->subsystem) in vnet_register_sysinit()
533 if (vs2->subsystem == vs->subsystem && vs2->order > vs->order) in vnet_register_sysinit()
536 if (vs2 != NULL) in vnet_register_sysinit()
537 TAILQ_INSERT_BEFORE(vs2, vs, link); in vnet_register_sysinit()
571 struct vnet_sysinit *vs, *vs2; in vnet_register_sysuninit() local
577 TAILQ_FOREACH(vs2, &vnet_destructors, link) { in vnet_register_sysuninit()
578 if (vs2->subsystem > vs->subsystem) in vnet_register_sysuninit()
580 if (vs2->subsystem == vs->subsystem && vs2->order > vs->order) in vnet_register_sysuninit()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrFormatsV.td110 bits<5> vs2;
117 let Inst{24-20} = vs2;
130 bits<5> vs2;
137 let Inst{24-20} = vs2;
147 class RVInstV2<bits<6> funct6, bits<5> vs2, RISCVVFormat opv, dag outs, dag ins,
156 let Inst{24-20} = vs2;
169 bits<5> vs2;
176 let Inst{24-20} = vs2;
189 bits<5> vs2;
195 let Inst{24-20} = vs2;
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H A DRISCVInstrInfoV.td374 // indexed load vd, (rs1), vs2, vm
378 (ins GPRMemZeroOffset:$rs1, VR:$vs2, VMaskOp:$vm), opcodestr,
379 "$vd, $rs1, $vs2$vm">;
400 // indexed segment load vd, (rs1), vs2, vm
405 (ins GPRMemZeroOffset:$rs1, VR:$vs2, VMaskOp:$vm), opcodestr,
406 "$vd, $rs1, $vs2$vm">;
438 // indexed store vd, vs3, (rs1), vs2, vm
441 (ins VR:$vs3, GPRMemZeroOffset:$rs1, VR:$vs2, VMaskOp:$vm),
442 opcodestr, "$vs3, $rs1, $vs2$vm">;
456 // segment store vd, vs3, (rs1), vs2, vm
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H A DRISCVInstrInfoXSfmm.td102 bits<5> vs2;
108 let Inst{24-20} = vs2;
122 bits<5> vs2;
129 let Inst{24-20} = vs2;
153 bits<5> vs2;
161 let Inst{24-20} = vs2;
183 bits<5> vs2;
250 def SF_MM_F_F : SFInstMatmulF<(outs), (ins TRM2:$rd, VR:$vs2, VR:$vs1),
251 "sf.mm.f.f", "$rd, $vs2, $vs1">;
259 (outs), (ins TRM4:$rd, VR:$vs2, VR:$vs1),
[all …]
H A DRISCVInstrInfoXRivos.td38 bits<5> vs2;
44 let Inst{24-20} = vs2;
120 let vm = 0, vs2=0, Inst<6-0> = OPC_CUSTOM_2.Value,
130 (ins VR:$vs2, uimm5:$imm),
131 "ri.vextract.x.v", "$rd, $vs2, $imm">;
176 def : Pat<(XLenVT (ri_vextract (vti.Vector vti.RegClass:$vs2), uimm5:$imm)),
178 $vs2, uimm5:$imm, vti.Log2SEW)>;
H A DRISCVInstrInfoXAndes.td363 : RVInst<(outs VR:$vd), (ins VR:$vs2, FPR32:$rs1, VMaskOp:$vm),
364 opcodestr # "." # "vf", "$vd, $rs1, $vs2$vm", [], InstFormatR>,
366 bits<5> vs2;
373 let Inst{24-20} = vs2;
386 : RVInst<(outs VR:$vd), (ins VR:$vs1, VR:$vs2, VMaskOp:$vm),
387 opcodestr # "." # "vv", "$vd, $vs1, $vs2$vm", [], InstFormatR>,
389 bits<5> vs2;
396 let Inst{24-20} = vs2;
409 : RVInst<(outs VR:$vd), (ins VR:$vs2, VMaskOp:$vm),
410 opcodestr, "$vd, $vs2", [], InstFormatR> {
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H A DRISCVInstrInfoZvk.td35 bits<5> vs2;
43 let Inst{24-20} = vs2;
56 (ins VR:$vs2, uimm6:$imm, VMaskOp:$vm),
57 opcodestr # ".vi", "$vd, $vs2, $imm$vm">,
61 // op vd, vs2, vs1
67 // op vd, vs2, vs1
70 (ins VR:$vd, VR:$vs2, VR:$vs1),
71 opcodestr, "$vd, $vs2, $vs1"> {
77 // op vd, vs2, imm
84 // op vd, vs2, imm where vd is also a source regardless of tail policy
[all …]
H A DRISCVInstrInfoXTHead.td82 // op vd, vs1, vs2, vm (reverse the order of vs1 and vs2)
86 (ins VR:$vd, VR:$vs1, VR:$vs2, VMaskOp:$vm),
87 opcodestr, "$vd, $vs1, $vs2$vm"> {
92 // op vd, rs1, vs2, vm (reverse the order of rs1 and vs2)
96 (ins VR:$vd, GPR:$rs1, VR:$vs2, VMaskOp:$vm),
97 opcodestr, "$vd, $rs1, $vs2$vm"> {
/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt8183-kukui.dtsi381 vsys-vs2-supply = <&reg_vsys>;
383 vs2-ldo1-supply = <&mt6358_vdram1_reg>;
384 vs2-ldo2-supply = <&mt6358_vs2_reg>;
385 vs2-ldo3-supply = <&mt6358_vs2_reg>;
386 vs2-ldo4-supply = <&mt6358_vs2_reg>;
H A Dmt8186-corsola.dtsi1303 vsys-vs2-supply = <&pp4200_z2>;
1305 vs2-ldo1-supply = <&mt6366_vdram1_reg>;
1306 vs2-ldo2-supply = <&mt6366_vs2_reg>;
1307 vs2-ldo3-supply = <&mt6366_vs2_reg>;
1379 mt6366_vs2_reg: vs2 {
H A Dmt6359.dtsi64 regulator-name = "vs2";
H A Dmt6358.dtsi85 regulator-name = "vs2";
/freebsd/sys/contrib/device-tree/src/arm/qcom/
H A Dqcom-pm8941.dtsi224 interrupt-names = "ocp-5vs1", "ocp-5vs2";
243 pm8941_5vs2: 5vs2 {
/freebsd/sys/dev/ntb/test/
H A Dntb_tool.c457 bool vs1, vs2, vs3; in parse_mw_buf() local
460 vs1 = vs2 = vs3 = false; in parse_mw_buf()
472 vs2 = true; in parse_mw_buf()
481 } else if (!vs2 && !strcmp(op2, "nbytes")) { in parse_mw_buf()
483 vs2 = true; in parse_mw_buf()
491 } else if (!vs2 && !strcmp(op3, "nbytes")) { in parse_mw_buf()
/freebsd/sys/contrib/openzfs/module/zfs/
H A Dspa_stats.c429 vdev_get_stats(spa->spa_root_vdev, &ts->vs2); in spa_txg_history_fini_io()
434 ts->vs2.vs_bytes[ZIO_TYPE_READ] - ts->vs1.vs_bytes[ZIO_TYPE_READ], in spa_txg_history_fini_io()
435 ts->vs2.vs_bytes[ZIO_TYPE_WRITE] - ts->vs1.vs_bytes[ZIO_TYPE_WRITE], in spa_txg_history_fini_io()
436 ts->vs2.vs_ops[ZIO_TYPE_READ] - ts->vs1.vs_ops[ZIO_TYPE_READ], in spa_txg_history_fini_io()
437 ts->vs2.vs_ops[ZIO_TYPE_WRITE] - ts->vs1.vs_ops[ZIO_TYPE_WRITE], in spa_txg_history_fini_io()
/freebsd/contrib/llvm-project/lldb/source/Plugins/Process/Utility/
H A DRegisterInfos_ppc64le.h211 DEFINE_VSX(vs2, LLDB_INVALID_REGNUM), \
396 uint32_t vs2[4]; member
/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Dmt6358-regulator.txt82 regulator-name = "vs2";
H A Dqcom,smd-rpm-regulator.txt255 lvs3, 5vs1, 5vs2
H A Dqcom,spmi-regulator.txt212 5vs1, 5vs2
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrMMA.td1070 (INSERT_SUBREG (IMPLICIT_DEF), $vs2, sub_vsx1),
1088 def : Pat<(v512i1 (PPCAccBuild v4i32:$vs1, v4i32:$vs0, v4i32:$vs3, v4i32:$vs2)),
1091 v16i8:$vs3, v16i8:$vs2)),
1105 def : Pat<(v512i1 (PPCAccBuild v4i32:$vs1, v4i32:$vs0, v4i32:$vs3, v4i32:$vs2)),
1108 v16i8:$vs3, v16i8:$vs2)),
H A DPPCInstrP10.td1146 (v256i1 (REG_SEQUENCE VSRpRC, $vs2, sub_vsx1, $vs3, sub_vsx0));
/freebsd/sys/contrib/openzfs/include/sys/
H A Dspa.h955 vdev_stat_t vs2; member