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Searched refs:vs1 (Results 1 – 24 of 24) sorted by relevance

/freebsd/crypto/openssl/crypto/perlasm/
H A Driscv.pm424 my $vs1 = read_vreg shift;
426 return ".word ".($template | ($vm << 25) | ($vs2 << 20) | ($vs1 << 15) | ($vd << 7));
444 my $vs1 = read_vreg shift;
446 return ".word ".($template | ($vm << 25) | ($vs2 << 20) | ($vs1 << 15) | ($vd << 7));
554 my $vs1 = read_vreg shift;
555 return ".word ".($template | ($vs2 << 20) | ($vs1 << 15) | ($vd << 7))
562 my $vs1 = read_vreg shift;
564 return ".word ".($template | ($vs1 << 20) | ($imm << 15) | ($vd << 7))
597 my $vs1 = read_vreg shift;
598 return ".word ".($template | ($vs1 << 15) | ($vd << 7));
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoXSfmm.td103 bits<5> vs1;
109 let Inst{19-15} = vs1;
123 bits<5> vs1;
130 let Inst{19-15} = vs1;
154 bits<5> vs1;
162 let Inst{19-15} = vs1;
184 bits<5> vs1;
250 def SF_MM_F_F : SFInstMatmulF<(outs), (ins TRM2:$rd, VR:$vs2, VR:$vs1),
251 "sf.mm.f.f", "$rd, $vs2, $vs1">;
259 (outs), (ins TRM4:$rd, VR:$vs2, VR:$vs1),
[all …]
H A DRISCVInstrInfoV.td465 // op vd, vs2, vs1, vm
468 (ins VR:$vs2, VR:$vs1, VMaskOp:$vm),
469 opcodestr, "$vd, $vs2, $vs1$vm">;
471 // op vd, vs2, vs1, v0 (without mask, use v0 as carry input)
474 (ins VR:$vs2, VR:$vs1, VMaskCarryInOp:$vm),
475 opcodestr, "$vd, $vs2, $vs1, $vm">;
477 // op vd, vs1, vs2, vm (reverse the order of vs1 and vs2)
481 (ins VR:$vd, VR:$vs1, VR:$vs2, VMaskOp:$vm),
482 opcodestr, "$vd, $vs1, $vs2$vm"> {
487 // op vd, vs2, vs1
[all …]
H A DRISCVInstrFormatsV.td111 bits<5> vs1;
118 let Inst{19-15} = vs1;
186 class RVInstV<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, dag outs,
196 let Inst{19-15} = vs1;
H A DRISCVInstrInfoXAndes.td386 : RVInst<(outs VR:$vd), (ins VR:$vs1, VR:$vs2, VMaskOp:$vm),
387 opcodestr # "." # "vv", "$vd, $vs1, $vs2$vm", [], InstFormatR>,
390 bits<5> vs1;
397 let Inst{19-15} = vs1;
408 class NDSRVInstVBFHCvt<bits<5> vs1, string opcodestr>
416 let Inst{19-15} = vs1;
H A DRISCVInstrInfoZvk.td61 // op vd, vs2, vs1
67 // op vd, vs2, vs1
70 (ins VR:$vd, VR:$vs2, VR:$vs1),
71 opcodestr, "$vd, $vs2, $vs1"> {
95 // op vd, vs2 (use vs1 as instruction encoding) where vd is also a source
97 class PALUVs2NoVmBinary<bits<6> funct6, bits<5> vs1, RISCVVFormat opv,
99 : RVInstV<funct6, vs1, opv, (outs VR:$vd_wb), (ins VR:$vd, VR:$vs2),
106 multiclass VAES_MV_V_S<bits<6> funct6_vv, bits<6> funct6_vs, bits<5> vs1,
109 def NAME # _VV : PALUVs2NoVmBinary<funct6_vv, vs1, opv, opcodestr # ".vv">,
112 def NAME # _VS : PALUVs2NoVmBinary<funct6_vs, vs1, opv, opcodestr # ".vs">,
H A DRISCVInstrInfoXTHead.td82 // op vd, vs1, vs2, vm (reverse the order of vs1 and vs2)
86 (ins VR:$vd, VR:$vs1, VR:$vs2, VMaskOp:$vm),
87 opcodestr, "$vd, $vs1, $vs2$vm"> {
/freebsd/sys/contrib/device-tree/src/arm/qcom/
H A Dqcom-pm8941.dtsi224 interrupt-names = "ocp-5vs1", "ocp-5vs2";
233 pm8941_5vs1: 5vs1 {
H A Dqcom-msm8974pro-samsung-klte-common.dtsi647 pma8084_5vs1: 5vs1 {};
H A Dqcom-apq8084.dtsi847 pma8084_5vs1: 5vs1 {};
/freebsd/sys/dev/ntb/test/
H A Dntb_tool.c457 bool vs1, vs2, vs3; in parse_mw_buf() local
460 vs1 = vs2 = vs3 = false; in parse_mw_buf()
469 vs1 = true; in parse_mw_buf()
478 if (!vs1 && !strcmp(op2, "offset")) { in parse_mw_buf()
480 vs1 = true; in parse_mw_buf()
489 if (!vs1 && !strcmp(op3, "offset")) { in parse_mw_buf()
/freebsd/sys/contrib/openzfs/module/zfs/
H A Dspa_stats.c411 vdev_get_stats(spa->spa_root_vdev, &ts->vs1); in spa_txg_history_init_io()
439 ts->vs2.vs_bytes[ZIO_TYPE_READ] - ts->vs1.vs_bytes[ZIO_TYPE_READ], in spa_txg_history_fini_io()
440 ts->vs2.vs_bytes[ZIO_TYPE_WRITE] - ts->vs1.vs_bytes[ZIO_TYPE_WRITE], in spa_txg_history_fini_io()
441 ts->vs2.vs_ops[ZIO_TYPE_READ] - ts->vs1.vs_ops[ZIO_TYPE_READ], in spa_txg_history_fini_io()
442 ts->vs2.vs_ops[ZIO_TYPE_WRITE] - ts->vs1.vs_ops[ZIO_TYPE_WRITE], in spa_txg_history_fini_io()
/freebsd/sys/contrib/device-tree/src/arm64/mediatek/
H A Dmt6357.dtsi45 mt6357_vs1_reg: buck-vs1 {
46 regulator-name = "vs1";
H A Dmt8183-kukui.dtsi403 vsys-vs1-supply = <&reg_vsys>;
405 vs1-ldo1-supply = <&mt6358_vs1_reg>;
H A Dmt6359.dtsi26 regulator-name = "vs1";
H A Dmt6358.dtsi104 regulator-name = "vs1";
H A Dmt8186-corsola.dtsi1302 vsys-vs1-supply = <&pp4200_z2>;
1304 vs1-ldo1-supply = <&mt6366_vs1_reg>;
1370 mt6366_vs1_reg: vs1 {
/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Dqcom,smd-rpm-regulator.txt255 lvs3, 5vs1, 5vs2
270 l21, l22, l23, l24, l25, l26, l27, lvs1, lvs2, lvs3, lvs4, 5vs1
H A Dmt6358-regulator.txt100 regulator-name = "vs1";
H A Dqcom,spmi-regulator.txt212 5vs1, 5vs2
/freebsd/contrib/llvm-project/lldb/source/Plugins/Process/Utility/
H A DRegisterInfos_ppc64le.h210 DEFINE_VSX(vs1, LLDB_INVALID_REGNUM), \
395 uint32_t vs1[4]; member
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrMMA.td1067 $vs1, sub_vsx0));
1088 def : Pat<(v512i1 (PPCAccBuild v4i32:$vs1, v4i32:$vs0, v4i32:$vs3, v4i32:$vs2)),
1090 def : Pat<(v512i1 (int_ppc_mma_assemble_acc v16i8:$vs1, v16i8:$vs0,
1105 def : Pat<(v512i1 (PPCAccBuild v4i32:$vs1, v4i32:$vs0, v4i32:$vs3, v4i32:$vs2)),
1107 def : Pat<(v512i1 (int_ppc_mma_assemble_acc v16i8:$vs1, v16i8:$vs0,
H A DPPCInstrP10.td1144 (v256i1 (REG_SEQUENCE VSRpRC, $vs0, sub_vsx1, $vs1, sub_vsx0));
1150 def : Pat<(v256i1 (PPCPairBuild v4i32:$vs1, v4i32:$vs0)),
1152 def : Pat<(v256i1 (int_ppc_vsx_assemble_pair v16i8:$vs1, v16i8:$vs0)),
/freebsd/sys/contrib/openzfs/include/sys/
H A Dspa.h959 vdev_stat_t vs1; member