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Searched refs:uxtw (Results 1 – 9 of 9) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMAddressingModes.h34 uxtw enumerator
52 case ARM_AM::uxtw: return "uxtw"; in getShiftOpcStr()
H A DARMInstPrinter.cpp674 printRegImmShift(O, ARM_AM::uxtw, shift, *this); in printMveAddrModeRQOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SVEInstrInfo.td629 defm UXTW_ZPmZ : sve_int_un_pred_arit_0_d<0b101, "uxtw", AArch64uxt_mt>;
1156 // ld1h z0.s, p0/z, [x0, z0.s, uxtw]
1169 // ld1h z0.s, p0/z, [x0, z0.s, uxtw #1]
1241 // ld1h z0.d, p0/z, [x0, z0.d, uxtw]
1258 // ld1h z0.d, p0/z, [x0, z0.d, uxtw #1]
1452 // st1h z0.d, p0, [x0, z0.d, uxtw]
1459 // st1h z0.s, p0, [x0, z0.s, uxtw]
1465 // st1h z0.s, p0, [x0, z0.s, uxtw #1]
1470 // st1h z0.d, p0, [x0, z0.d, uxtw #1]
1674 // prfh pldl1keep, p0, [x0, z0.s, uxtw #1]
[all …]
H A DSVEInstrFormats.td7963 // bit lsl is '0' if the offsets are extended (uxtw/sxtw), '1' if shifted (lsl)
8095 // bit lsl is '0' if the offsets are extended (uxtw/sxtw), '1' if shifted (lsl)
H A DAArch64InstrFormats.td3822 // Asm-level Operand covering the valid "uxtw #3" style syntax.
H A DAArch64InstrInfo.td2950 def : InstAlias<"uxtw $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
/freebsd/contrib/llvm-project/openmp/runtime/src/
H A Dz_Linux_asm.S1356 sub sp, sp, w9, uxtw #4
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsAArch64.td2264 // 32 bit unscaled offsets, sign (sxtw) or zero (uxtw) extended to 64 bits
2268 // 32 bit scaled offsets, sign (sxtw) or zero (uxtw) extended to 64 bits
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp1920 (Memory.ShiftType != ARM_AM::uxtw || Memory.ShiftImm != shift)) in isMemRegRQOffset()
6143 St = ARM_AM::uxtw; in parseMemRegOffsetShift()