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/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetPfmCounters.td24 // The name of the ProcResource on which uops are issued. This is used by
64 // Processors can define how to measure uops by defining a UopsCounter.
66 // Processors can define how to measure issued uops by defining IssueCounters.
H A DTargetItinerary.td111 list<Bypass> bypasses = [], int uops = 1> {
113 int NumMicroOps = uops;
/freebsd/usr.sbin/pmcstudy/
H A Dpmcstudy.c546 struct counters *uops; in br_mispredictib() local
566 uops = find_counter(cpu, "UOPS_RETIRED.RETIRE_SLOTS"); in br_mispredictib()
574 uo = uops->vals[pos] * 1.0; in br_mispredictib()
583 uo = uops->sum * 1.0; in br_mispredictib()
600 struct counters *uops; in br_mispredict_broad() local
611 uops = find_counter(cpu, "UOPS_ISSUED.ANY"); in br_mispredict_broad()
619 uo = uops->vals[pos] * 1.0; in br_mispredict_broad()
626 uo = uops->sum * 1.0; in br_mispredict_broad()
1592 struct counters *uops; in efficiency1() local
1599 uops = find_counter(cpu, "UOPS_RETIRED.RETIRE_SLOTS"); in efficiency1()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedKryo.td16 // uops. Now, the latency spreadsheet has information based on fragmented uops,
20 let IssueWidth = 5; // 5-wide issue for expanded uops
H A DAArch64SchedFalkor.td19 let IssueWidth = 8; // 8 uops are dispatched per cycle.
H A DAArch64SchedOryon.td286 // these instructions are broken down to three uops
1258 // ASIMD store, 1 element, multiple, 1 reg, Q-form 1 uops
1584 // TBL 3-reg/4-reg, 3uops, throughtput=4/3=1.33 latency=4
H A DAArch64SchedAmpere1.td17 // decoded into internal micro-ops (uops).
571 // across Unit A or B for both uops.
H A DAArch64SchedAmpere1B.td17 // decoded into internal micro-ops (uops).
527 // across Unit A or B for both uops.
H A DAArch64SchedExynosM3.td20 let IssueWidth = 6; // Up to 6 uops per cycle.
H A DAArch64SchedExynosM4.td20 let IssueWidth = 6; // Up to 6 uops per cycle.
H A DAArch64SchedExynosM5.td20 let IssueWidth = 6; // Up to 6 uops per cycle.
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleA8.td154 [1, 1, 1, 1, 3], [], -1>, // dynamic uops
159 [2, 1, 1, 1, 3], [], -1>, // dynamic uops
165 [1, 2, 1, 1, 3], [], -1>, // dynamic uops
170 [1, 1, 3], [], -1>, // dynamic uops
176 [1, 1, 3], [], -1>, // dynamic uops
232 [], [], -1>, // dynamic uops
237 [2], [], -1>, // dynamic uops
399 [1, 1, 1, 2], [], -1>, // dynamic uops
407 [2, 1, 1, 1, 2], [], -1>, // dynamic uops
427 [1, 1, 1, 1], [], -1>, // dynamic uops
[all …]
H A DARMScheduleA9.td287 -1>, // dynamic uops
296 -1>, // dynamic uops
306 -1>, // dynamic uops
315 -1>, // dynamic uops
325 -1>, // dynamic uops
420 [], [], -1>, // dynamic uops
427 [2], [], -1>, // dynamic uops
725 [1, 1, 1, 1], [], -1>, // dynamic uops
735 [2, 1, 1, 1], [], -1>, // dynamic uops
763 [1, 1, 1, 1], [], -1>, // dynamic uops
[all...]
H A DARMSchedule.td194 class BranchWriteRes<int lat, int uops, list<ProcResourceKind> resl,
199 let NumMicroOps = !add(wr.NumMicroOps, uops);
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86SchedSkylakeServer.td2115 let NumMicroOps = 5; // 2 uops perform multiple loads
2124 let NumMicroOps = 5; // 2 uops perform multiple loads
2134 let NumMicroOps = 5; // 2 uops perform multiple loads
2144 let NumMicroOps = 5; // 2 uops perform multiple loads
2172 let NumMicroOps = 5; // 2 uops perform multiple loads
2181 let NumMicroOps = 5; // 2 uops peform multiple loads
2191 let NumMicroOps = 5; // 2 uops perform multiple loads
2371 // echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
2372 // echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
H A DX86SchedIceLake.td2132 let NumMicroOps = 5; // 2 uops perform multiple loads
2141 let NumMicroOps = 5; // 2 uops perform multiple loads
2151 let NumMicroOps = 5; // 2 uops perform multiple loads
2161 let NumMicroOps = 5; // 2 uops perform multiple loads
2189 let NumMicroOps = 5; // 2 uops perform multiple loads
2198 let NumMicroOps = 5; // 2 uops peform multiple loads
2208 let NumMicroOps = 5; // 2 uops perform multiple loads
2388 // echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
2389 // echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
H A DX86SchedSkylakeClient.td1451 let NumMicroOps = 5; // 2 uops perform multiple loads
1460 let NumMicroOps = 5; // 2 uops peform multiple loads
1470 let NumMicroOps = 5; // 2 uops perform multiple loads
1605 // echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
1606 // echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
H A DX86SchedSandyBridge.td1145 // echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
1146 // echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
H A DX86ScheduleZnver1.td329 defm : ZnWriteResFpuPair<WriteFRnd, [ZnFPU3], 4, [1], 1, 7, 1>; // FIXME: Should folds require 1 extra uops?
330 defm : ZnWriteResFpuPair<WriteFRndY, [ZnFPU3], 4, [1], 1, 7, 1>; // FIXME: Should folds require 1 extra uops?
H A DX86SchedBroadwell.td1535 // echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
1536 // echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
H A DX86SchedHaswell.td1774 // echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
1775 // echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
H A DX86ScheduleZnver3.td684 // FIXME: uops for 8-bit division measures as 2. for others it's a guess.
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DVLIWMachineScheduler.cpp365 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr()); in checkHazard() local
366 if (IssueCount + uops > SchedModel->getIssueWidth()) in checkHazard()
H A DMachineScheduler.cpp2463 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr()); in checkHazard() local
2464 if ((CurrMOps > 0) && (CurrMOps + uops > SchedModel->getIssueWidth())) { in checkHazard()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsScheduleP5600.td530 // These instructions are split across multiple uops (in different pipelines)

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