| /freebsd/sys/contrib/ncsw/Peripherals/FM/MAC/ |
| H A D | fman_memac_mii_acc.c | 39 uint32_t tmp_reg; in write_phy_reg_10g() local
41 tmp_reg = ioread32be(&mii_regs->mdio_cfg); in write_phy_reg_10g()
43 tmp_reg &= MDIO_CFG_CLK_DIV_MASK; in write_phy_reg_10g()
46 tmp_reg |= MDIO_CFG_HOLD_MASK; in write_phy_reg_10g()
48 tmp_reg |= MDIO_CFG_ENC45; in write_phy_reg_10g()
49 iowrite32be(tmp_reg, &mii_regs->mdio_cfg); in write_phy_reg_10g()
75 uint32_t tmp_reg; in read_phy_reg_10g() local
77 tmp_reg = ioread32be(&mii_regs->mdio_cfg); in read_phy_reg_10g()
79 tmp_reg &= MDIO_CFG_CLK_DIV_MASK; in read_phy_reg_10g()
82 tmp_reg |= MDIO_CFG_HOLD_MASK; in read_phy_reg_10g()
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| /freebsd/sys/contrib/ncsw/Peripherals/FM/ |
| H A D | fman_ncsw.c | 291 uint32_t tmp_reg; in fman_set_qmi_enq_th() local
293 tmp_reg = ioread32be(&qmi_rg->fmqm_gc); in fman_set_qmi_enq_th()
294 tmp_reg &= ~QMI_CFG_ENQ_MASK; in fman_set_qmi_enq_th()
295 tmp_reg |= ((uint32_t)val << 8); in fman_set_qmi_enq_th()
296 iowrite32be(tmp_reg, &qmi_rg->fmqm_gc); in fman_set_qmi_enq_th()
301 uint32_t tmp_reg; in fman_set_qmi_deq_th() local
303 tmp_reg = ioread32be(&qmi_rg->fmqm_gc); in fman_set_qmi_deq_th()
304 tmp_reg &= ~QMI_CFG_DEQ_MASK; in fman_set_qmi_deq_th()
305 tmp_reg |= (uint32_t)val; in fman_set_qmi_deq_th()
306 iowrite32be(tmp_reg, &qmi_rg->fmqm_gc); in fman_set_qmi_deq_th()
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| /freebsd/sys/contrib/ncsw/Peripherals/FM/SP/ |
| H A D | fman_sp.c | 90 uint32_t tmp_reg, vector; in fman_vsp_init() local
107 tmp_reg = FMAN_SP_EXT_BUF_POOL_VALID | in fman_vsp_init()
109 tmp_reg |= ((uint32_t)ext_buf_pools->ext_buf_pool[i].id << in fman_vsp_init()
111 tmp_reg |= ext_buf_pools->ext_buf_pool[i].size; in fman_vsp_init()
117 tmp_reg |= FMAN_SP_EXT_BUF_POOL_BACKUP; in fman_vsp_init()
120 iowrite32be(tmp_reg, &sp_regs->fm_sp_ebmpi[i]); in fman_vsp_init()
129 tmp_reg = 0; in fman_vsp_init()
136 tmp_reg |= (((uint32_t)buf_pool_depletion->num_pools - 1) << in fman_vsp_init()
138 tmp_reg |= vector; in fman_vsp_init()
148 tmp_reg |= vector; in fman_vsp_init()
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| /freebsd/sys/contrib/ncsw/Peripherals/FM/Pcd/ |
| H A D | fman_kg.c | 454 uint32_t tmp_reg, i, select, mask, fqb; in fman_kg_build_scheme() local
461 tmp_reg = fm_kg_build_nia(params->next_engine, in fman_kg_build_scheme()
463 if (tmp_reg == KG_NIA_INVALID) { in fman_kg_build_scheme()
468 tmp_reg |= FMAN_KG_SCH_MODE_NIA_PLCR; in fman_kg_build_scheme()
471 tmp_reg |= (uint32_t)params->cc_params.base_offset << in fman_kg_build_scheme()
475 tmp_reg |= FMAN_KG_SCH_MODE_EN; in fman_kg_build_scheme()
476 scheme_regs->kgse_mode = tmp_reg; in fman_kg_build_scheme()
491 tmp_reg = 0; in fman_kg_build_scheme()
492 tmp_reg |= extract_params->known_fields_def.mac_addr << in fman_kg_build_scheme()
494 tmp_reg |= extract_params->known_fields_def.vlan_tci << in fman_kg_build_scheme()
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| /freebsd/sys/contrib/ncsw/Peripherals/FM/Rtc/ |
| H A D | fman_rtc.c | 256 uint32_t tmp_reg; in fman_rtc_clear_periodic_pulse() local
258 tmp_reg = FMAN_RTC_TMR_TEVENT_PP1; in fman_rtc_clear_periodic_pulse()
260 tmp_reg = FMAN_RTC_TMR_TEVENT_PP2; in fman_rtc_clear_periodic_pulse()
261 fman_rtc_disable_interupt(regs, tmp_reg); in fman_rtc_clear_periodic_pulse()
263 tmp_reg = fman_rtc_get_timer_ctrl(regs); in fman_rtc_clear_periodic_pulse()
264 if (tmp_reg & FMAN_RTC_TMR_CTRL_FS) in fman_rtc_clear_periodic_pulse()
265 fman_rtc_set_timer_ctrl(regs, tmp_reg & ~FMAN_RTC_TMR_CTRL_FS); in fman_rtc_clear_periodic_pulse()
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| /freebsd/sys/dev/ath/ath_hal/ar5416/ |
| H A D | ar2133.c | 90 uint32_t tmp_reg; in ar2133ForceBias() local
107 tmp_reg = ath_hal_reverseBits(new_bias, 3); in ar2133ForceBias()
113 ar5416ModifyRfBuffer(priv->Bank6Data, tmp_reg, 3, 181, 3); in ar2133ForceBias()
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| /freebsd/sys/contrib/dev/rtw89/ |
| H A D | rtw8852a_rfk.c | 257 u32 tmp = 0, tmp_offset, tmp_reg; in _dack_reload_by_path() local
276 tmp_reg = 0x5e14 + tmp_offset; in _dack_reload_by_path()
277 rtw89_phy_write32(rtwdev, tmp_reg, tmp); in _dack_reload_by_path()
278 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", tmp_reg, in _dack_reload_by_path()
279 rtw89_phy_read32_mask(rtwdev, tmp_reg, MASKDWORD)); in _dack_reload_by_path()
284 tmp_reg = 0x5e18 + tmp_offset; in _dack_reload_by_path()
285 rtw89_phy_write32(rtwdev, tmp_reg, tmp); in _dack_reload_by_path()
286 rtw89_debug(rtwdev, RTW89_DBG_RFK, "[DACK]0x%x=0x%x\n", tmp_reg, in _dack_reload_by_path()
287 rtw89_phy_read32_mask(rtwdev, tmp_reg, MASKDWORD)); in _dack_reload_by_path()
292 tmp_reg = 0x5e1c + tmp_offset; in _dack_reload_by_path()
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| /freebsd/sys/contrib/dev/ath/ath_hal/ar9300/ |
| H A D | ar9300_reset.c | 1684 u_int32_t tmp_reg; in ar9300_set_reset() local
1700 tmp_reg = OS_REG_READ(ah, AR_HOSTIF_REG(ah, AR_INTR_SYNC_CAUSE)); in ar9300_set_reset()
1702 if (tmp_reg & (AR9340_INTR_SYNC_LOCAL_TIMEOUT)) { in ar9300_set_reset()
1707 if (tmp_reg & (AR9300_INTR_SYNC_LOCAL_TIMEOUT | AR9300_INTR_SYNC_RADM_CPL_TIMEOUT)) { in ar9300_set_reset()
1748 tmp_reg = REG_READ(AR_SOC_BOOT_STRAP); in ar9300_set_reset()
1749 if ((tmp_reg & 0x10) == 0) { in ar9300_set_reset()
4536 u_int32_t save_force_val, tmp_reg; in ar9300_reset() local
4992 tmp_reg = OS_REG_READ(ah, AR_PHY_TIMING2) & in ar9300_reset()
4994 OS_REG_WRITE(ah, AR_PHY_TIMING2, tmp_reg | save_force_val); in ar9300_reset()
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| /freebsd/sys/dev/bxe/ |
| H A D | bxe.c | 15518 uint32_t tmp_reg = REG_RD(sc, BXE_PREV_UNDI_PROD_ADDR(port)); in bxe_prev_unload_undi_inc() local
15520 rcq = BXE_PREV_UNDI_RCQ(tmp_reg) + inc; in bxe_prev_unload_undi_inc()
15521 bd = BXE_PREV_UNDI_BD(tmp_reg) + inc; in bxe_prev_unload_undi_inc()
15523 tmp_reg = BXE_PREV_UNDI_PROD(rcq, bd); in bxe_prev_unload_undi_inc()
15524 REG_WR(sc, BXE_PREV_UNDI_PROD_ADDR(port), tmp_reg); in bxe_prev_unload_undi_inc()
15534 uint32_t reset_reg, tmp_reg = 0, rc; in bxe_prev_unload_common() local
15568 tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST); in bxe_prev_unload_common()
15569 if (tmp_reg == 0x7) { in bxe_prev_unload_common()
15580 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS); in bxe_prev_unload_common()
15582 prev_brb = tmp_reg; in bxe_prev_unload_common()
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