291 	uint32_t tmp_reg;  in fman_set_qmi_enq_th()  local
293 	tmp_reg = ioread32be(&qmi_rg->fmqm_gc);  in fman_set_qmi_enq_th()
294 	tmp_reg &= ~QMI_CFG_ENQ_MASK;  in fman_set_qmi_enq_th()
295 	tmp_reg |= ((uint32_t)val << 8);  in fman_set_qmi_enq_th()
296 	iowrite32be(tmp_reg, &qmi_rg->fmqm_gc);  in fman_set_qmi_enq_th()
301 	uint32_t tmp_reg;  in fman_set_qmi_deq_th()  local
303 	tmp_reg = ioread32be(&qmi_rg->fmqm_gc);  in fman_set_qmi_deq_th()
304 	tmp_reg &= ~QMI_CFG_DEQ_MASK;  in fman_set_qmi_deq_th()
305 	tmp_reg |= (uint32_t)val;  in fman_set_qmi_deq_th()
306 	iowrite32be(tmp_reg, &qmi_rg->fmqm_gc);  in fman_set_qmi_deq_th()
409 	uint32_t tmp_reg;  in fman_get_size_of_fifo()  local
414 	tmp_reg = ioread32be(&bmi_rg->fmbm_pfs[port_id - 1]);  in fman_get_size_of_fifo()
415 	return (uint16_t)((tmp_reg & BMI_FIFO_SIZE_MASK) + 1);  in fman_get_size_of_fifo()
430 	uint32_t tmp_reg;  in fman_get_size_of_extra_fifo()  local
435 	tmp_reg = ioread32be(&bmi_rg->fmbm_pfs[port_id-1]);  in fman_get_size_of_extra_fifo()
436 	return (uint16_t)((tmp_reg & BMI_EXTRA_FIFO_SIZE_MASK) >>  in fman_get_size_of_extra_fifo()
630 	uint32_t tmp_reg;  in fman_regconfig()  local
635     tmp_reg = ioread32be(&fman_rg->bmi_rg->fmbm_cfg1);  in fman_regconfig()
637 …    (((tmp_reg & BMI_TOTAL_FIFO_SIZE_MASK) >> BMI_CFG1_FIFO_SIZE_SHIFT) + 1) * FMAN_BMI_FIFO_UNITS;  in fman_regconfig()
639     tmp_reg = ioread32be(&fman_rg->bmi_rg->fmbm_cfg2);  in fman_regconfig()
641         (uint8_t)(((tmp_reg & BMI_TOTAL_NUM_OF_TASKS_MASK) >> BMI_CFG2_TASKS_SHIFT) + 1);  in fman_regconfig()
643     tmp_reg = ioread32be(&fman_rg->dma_rg->fmdmtr);  in fman_regconfig()
644     cfg->dma_comm_qtsh_asrt_emer = (uint8_t)(tmp_reg >> DMA_THRESH_COMMQ_SHIFT);  in fman_regconfig()
646     tmp_reg = ioread32be(&fman_rg->dma_rg->fmdmhy);  in fman_regconfig()
647     cfg->dma_comm_qtsh_clr_emer  = (uint8_t)(tmp_reg >> DMA_THRESH_COMMQ_SHIFT);  in fman_regconfig()
649     tmp_reg = ioread32be(&fman_rg->dma_rg->fmdmmr);  in fman_regconfig()
650 …cfg->dma_cache_override      = (enum fman_dma_cache_override)((tmp_reg & DMA_MODE_CACHE_OR_MASK) >…  in fman_regconfig()
651 …cfg->dma_cam_num_of_entries  = (uint8_t)((((tmp_reg & DMA_MODE_CEN_MASK) >> DMA_MODE_CEN_SHIFT) +1…  in fman_regconfig()
652     cfg->dma_aid_override        = (bool)((tmp_reg & DMA_MODE_AID_OR)? TRUE:FALSE);  in fman_regconfig()
653 …cfg->dma_dbg_cnt_mode        = (enum fman_dma_dbg_cnt_mode)((tmp_reg & DMA_MODE_DBG_MASK) >> DMA_M…  in fman_regconfig()
654     cfg->dma_en_emergency        = (bool)((tmp_reg & DMA_MODE_EB)? TRUE : FALSE);  in fman_regconfig()
656     tmp_reg = ioread32be(&fman_rg->fpm_rg->fmfp_mxd);  in fman_regconfig()
657 … cfg->disp_limit_tsh          = (uint8_t)((tmp_reg & FPM_DISP_LIMIT_MASK) >> FPM_DISP_LIMIT_SHIFT);  in fman_regconfig()
659     tmp_reg = ioread32be(&fman_rg->fpm_rg->fmfp_dist1);  in fman_regconfig()
660     cfg->prs_disp_tsh            = (uint8_t)((tmp_reg & FPM_THR1_PRS_MASK ) >> FPM_THR1_PRS_SHIFT);  in fman_regconfig()
661     cfg->plcr_disp_tsh           = (uint8_t)((tmp_reg & FPM_THR1_KG_MASK ) >> FPM_THR1_KG_SHIFT);  in fman_regconfig()
662 …  cfg->kg_disp_tsh             = (uint8_t)((tmp_reg & FPM_THR1_PLCR_MASK ) >> FPM_THR1_PLCR_SHIFT);  in fman_regconfig()
663     cfg->bmi_disp_tsh            = (uint8_t)((tmp_reg & FPM_THR1_BMI_MASK ) >> FPM_THR1_BMI_SHIFT);  in fman_regconfig()
665     tmp_reg = ioread32be(&fman_rg->fpm_rg->fmfp_dist2);  in fman_regconfig()
666 …cfg->qmi_enq_disp_tsh        = (uint8_t)((tmp_reg & FPM_THR2_QMI_ENQ_MASK ) >> FPM_THR2_QMI_ENQ_SH…  in fman_regconfig()
667 …cfg->qmi_deq_disp_tsh        = (uint8_t)((tmp_reg & FPM_THR2_QMI_DEQ_MASK ) >> FPM_THR2_QMI_DEQ_SH…  in fman_regconfig()
668 …cfg->fm_ctl1_disp_tsh        = (uint8_t)((tmp_reg & FPM_THR2_FM_CTL1_MASK ) >> FPM_THR2_FM_CTL1_SH…  in fman_regconfig()
669 …cfg->fm_ctl2_disp_tsh        = (uint8_t)((tmp_reg & FPM_THR2_FM_CTL2_MASK ) >> FPM_THR2_FM_CTL2_SH…  in fman_regconfig()
671     tmp_reg = ioread32be(&fman_rg->dma_rg->fmdmsetr);  in fman_regconfig()
672     cfg->dma_sos_emergency       = tmp_reg;  in fman_regconfig()
674     tmp_reg = ioread32be(&fman_rg->dma_rg->fmdmwcr);  in fman_regconfig()
675     cfg->dma_watchdog            = tmp_reg/cfg->clk_freq;  in fman_regconfig()
677     tmp_reg = ioread32be(&fman_rg->dma_rg->fmdmemsr);  in fman_regconfig()
678     cfg->dma_en_emergency_smoother = (bool)((tmp_reg & DMA_EMSR_EMSTR_MASK)? TRUE : FALSE);  in fman_regconfig()
679     cfg->dma_emergency_switch_counter = (tmp_reg & DMA_EMSR_EMSTR_MASK);  in fman_regconfig()
698 	uint32_t    tmp_reg;  in fman_dma_init()  local
705 	tmp_reg = (DMA_STATUS_BUS_ERR | DMA_STATUS_READ_ECC |  in fman_dma_init()
707 	iowrite32be(ioread32be(&dma_rg->fmdmsr) | tmp_reg,  in fman_dma_init()
711 	tmp_reg = 0;  in fman_dma_init()
712 	tmp_reg |= cfg->dma_cache_override << DMA_MODE_CACHE_OR_SHIFT;  in fman_dma_init()
714 		tmp_reg |= DMA_MODE_AID_OR;  in fman_dma_init()
716 		tmp_reg |= DMA_MODE_BER;  in fman_dma_init()
720 		tmp_reg |= DMA_MODE_ECC;  in fman_dma_init()
722 		tmp_reg |= DMA_MODE_SBER;  in fman_dma_init()
724 	    tmp_reg |= (uint32_t)(DMA_MODE_AXI_DBG_MASK &  in fman_dma_init()
728 		tmp_reg |= cfg->dma_emergency_bus_select;  in fman_dma_init()
729 		tmp_reg |= cfg->dma_emergency_level << DMA_MODE_EMER_LVL_SHIFT;  in fman_dma_init()
734 	tmp_reg |= ((cfg->dma_cam_num_of_entries / DMA_CAM_UNITS) - 1) <<  in fman_dma_init()
736 	tmp_reg |= DMA_MODE_SECURE_PROT;  in fman_dma_init()
737 	tmp_reg |= cfg->dma_dbg_cnt_mode << DMA_MODE_DBG_SHIFT;  in fman_dma_init()
738 	tmp_reg |= cfg->dma_aid_mode << DMA_MODE_AID_MODE_SHIFT;  in fman_dma_init()
741 		tmp_reg |= DMA_MODE_EMER_READ;  in fman_dma_init()
743 	iowrite32be(tmp_reg, &dma_rg->fmdmmr);  in fman_dma_init()
746 	tmp_reg = ((uint32_t)cfg->dma_comm_qtsh_asrt_emer <<  in fman_dma_init()
752 	iowrite32be(tmp_reg, &dma_rg->fmdmtr);  in fman_dma_init()
755 	tmp_reg = ((uint32_t)cfg->dma_comm_qtsh_clr_emer <<  in fman_dma_init()
761 	iowrite32be(tmp_reg, &dma_rg->fmdmhy);  in fman_dma_init()
777 	uint32_t tmp_reg;  in fman_fpm_init()  local
783 	tmp_reg = (uint32_t)(cfg->disp_limit_tsh << FPM_DISP_LIMIT_SHIFT);  in fman_fpm_init()
784 	iowrite32be(tmp_reg, &fpm_rg->fmfp_mxd);  in fman_fpm_init()
786 	tmp_reg = (((uint32_t)cfg->prs_disp_tsh << FPM_THR1_PRS_SHIFT) |  in fman_fpm_init()
790 	iowrite32be(tmp_reg, &fpm_rg->fmfp_dist1);  in fman_fpm_init()
792 	tmp_reg = (((uint32_t)cfg->qmi_enq_disp_tsh << FPM_THR2_QMI_ENQ_SHIFT) |  in fman_fpm_init()
796 	iowrite32be(tmp_reg, &fpm_rg->fmfp_dist2);  in fman_fpm_init()
799 	tmp_reg = 0;  in fman_fpm_init()
801 	tmp_reg |= (FPM_EV_MASK_STALL | FPM_EV_MASK_DOUBLE_ECC |  in fman_fpm_init()
805 		tmp_reg |= FPM_EV_MASK_STALL_EN;  in fman_fpm_init()
807 		tmp_reg |= FPM_EV_MASK_SINGLE_ECC_EN;  in fman_fpm_init()
809 		tmp_reg |= FPM_EV_MASK_DOUBLE_ECC_EN;  in fman_fpm_init()
810 	tmp_reg |= (cfg->catastrophic_err  << FPM_EV_MASK_CAT_ERR_SHIFT);  in fman_fpm_init()
811 	tmp_reg |= (cfg->dma_err << FPM_EV_MASK_DMA_ERR_SHIFT);  in fman_fpm_init()
813 		tmp_reg |= FPM_EV_MASK_EXTERNAL_HALT;  in fman_fpm_init()
815 		tmp_reg |= FPM_EV_MASK_ECC_ERR_HALT;  in fman_fpm_init()
816 	iowrite32be(tmp_reg, &fpm_rg->fmfp_ee);  in fman_fpm_init()
826 	tmp_reg = (FPM_RAM_MURAM_ECC | FPM_RAM_IRAM_ECC);  in fman_fpm_init()
829 		tmp_reg |= FPM_RAM_RAMS_ECC_EN_SRC_SEL;  in fman_fpm_init()
833 		tmp_reg |= FPM_RAM_MURAM_TEST_ECC;  in fman_fpm_init()
835 		tmp_reg |= FPM_RAM_IRAM_TEST_ECC;  in fman_fpm_init()
836 	iowrite32be(tmp_reg, &fpm_rg->fm_rcr);  in fman_fpm_init()
838 	tmp_reg = 0;  in fman_fpm_init()
840 		tmp_reg |= FPM_IRAM_ECC_ERR_EX_EN;  in fman_fpm_init()
844 		tmp_reg |= FPM_MURAM_ECC_ERR_EX_EN;  in fman_fpm_init()
847 	iowrite32be(tmp_reg, &fpm_rg->fm_rie);  in fman_fpm_init()
854 	uint32_t tmp_reg;  in fman_bmi_init()  local
861 	tmp_reg = cfg->fifo_base_addr;  in fman_bmi_init()
862 	tmp_reg = tmp_reg / BMI_FIFO_ALIGN;  in fman_bmi_init()
864 	tmp_reg |= ((cfg->total_fifo_size / FMAN_BMI_FIFO_UNITS - 1) <<  in fman_bmi_init()
866 	iowrite32be(tmp_reg, &bmi_rg->fmbm_cfg1);  in fman_bmi_init()
868 	tmp_reg = ((uint32_t)(cfg->total_num_of_tasks - 1) <<  in fman_bmi_init()
871 	iowrite32be(tmp_reg, &bmi_rg->fmbm_cfg2);  in fman_bmi_init()
874 	tmp_reg = 0;  in fman_bmi_init()
882 		tmp_reg |= BMI_ERR_INTR_EN_LIST_RAM_ECC;  in fman_bmi_init()
884 		tmp_reg |= BMI_ERR_INTR_EN_STORAGE_PROFILE_ECC;  in fman_bmi_init()
886 		tmp_reg |= BMI_ERR_INTR_EN_STATISTICS_RAM_ECC;  in fman_bmi_init()
888 		tmp_reg |= BMI_ERR_INTR_EN_DISPATCH_RAM_ECC;  in fman_bmi_init()
889 	iowrite32be(tmp_reg, &bmi_rg->fmbm_ier);  in fman_bmi_init()
896 	uint32_t tmp_reg;  in fman_qmi_init()  local
906 	tmp_reg = 0;  in fman_qmi_init()
908 		tmp_reg |= QMI_ERR_INTR_EN_DEQ_FROM_DEF;  in fman_qmi_init()
910 		tmp_reg |= QMI_ERR_INTR_EN_DOUBLE_ECC;  in fman_qmi_init()
912 	iowrite32be(tmp_reg, &qmi_rg->fmqm_eien);  in fman_qmi_init()
921 			tmp_reg = (uint32_t)((period_in_fm_clocks / 64) + 1);  in fman_qmi_init()
923 			tmp_reg = (uint32_t)(period_in_fm_clocks / 64);  in fman_qmi_init()
924 			if (!tmp_reg)  in fman_qmi_init()
925 				tmp_reg = 1;  in fman_qmi_init()
927 		tmp_reg <<= QMI_TAPC_TAP;  in fman_qmi_init()
928 		iowrite32be(tmp_reg, &qmi_rg->fmqm_tapc);  in fman_qmi_init()
930 	tmp_reg = 0;  in fman_qmi_init()
934 		tmp_reg |= QMI_INTR_EN_SINGLE_ECC;  in fman_qmi_init()
936 	iowrite32be(tmp_reg, &qmi_rg->fmqm_ien);  in fman_qmi_init()