| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZShortenInst.cpp | 71 MI.tieOperands(0, 1); in tieOpsIfNeeded()
366 MI.tieOperands(0, 1); in processBlock()
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| H A D | SystemZPostRewrite.cpp | 217 MI.tieOperands(0, 1); in selectMI()
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| H A D | SystemZInstrInfo.cpp | 186 MI.tieOperands(0, 1); in expandRIEPseudo()
750 UseMI.tieOperands(0, 1); in foldImmediate()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86CompressEVEX.cpp | 273 MI.tieOperands(0, 1); in CompressEVEXImpl()
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| H A D | X86ExpandPseudo.cpp | 595 MI.tieOperands(0, 1); in expandMI()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVVectorPeephole.cpp | 191 MI.tieOperands(0, 1); // Tie false to dest in convertVMergeToVMv()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIShrinkInstructions.cpp | 396 MI.tieOperands( in shrinkMIMG()
567 MI.tieOperands(0, 2); in shrinkScalarLogicOp()
871 MI.tieOperands(0, 1); in runOnMachineFunction()
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| H A D | SIPeepholeSDWA.cpp | 529 MI.tieOperands(AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdst), in convertToSDWA()
1164 SDWAInst->tieOperands(PreserveDstIdx, SDWAInst->getNumOperands() - 1); in convertToSDWA()
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| H A D | SIRegisterInfo.cpp | 1715 MIB->tieOperands(0, MIB->getNumOperands() - 1); in buildSpillLoadStore()
2329 MI->tieOperands(NewVDst, NewVDstIn); in eliminateFrameIndex()
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| H A D | SIInstrInfo.cpp | 1024 MIB->tieOperands(0, MIB->getNumOperands() - 1); in copyPhysReg()
2364 MIB->tieOperands(ImpDefIdx, ImpUseIdx); in expandPostRAPseudo()
2403 MIB->tieOperands(ImpDefIdx, ImpUseIdx); in expandPostRAPseudo()
6187 Inst.tieOperands(NewVDst, NewVDstIn); in moveFlatAddrToVGPR()
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| H A D | AMDGPUInstructionSelector.cpp | 2253 MovSDWA->tieOperands(0, MovSDWA->getNumOperands() - 1); in selectG_TRUNC()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | FixupStatepointCallerSaved.cpp | 534 MIB->tieOperands(NewIndices[OldDef], MIB->getNumOperands() - 1); in rewriteStatepoint()
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| H A D | MachineInstr.cpp | 282 tieOperands(DefIdx, OpNo); in addOperand()
1162 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) { in tieOperands() function in MachineInstr
2603 tieOperands(Tie1, Tie2); in insert()
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| H A D | InlineSpiller.cpp | 974 MI->tieOperands(Tied.first, Tied.second); in foldMemoryOperand()
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| H A D | TargetInstrInfo.cpp | 561 NewMI->tieOperands(TiedTo, NewMI->getNumOperands() - 1); in foldPatchpoint()
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| H A D | TargetLoweringBase.cpp | 1170 MIB->tieOperands(TiedTo, MIB->getNumOperands() - 1); in emitPatchPoint()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | InlineAsmLowering.cpp | 422 Inst->tieOperands(DefRegIdx, Inst->getNumOperands() - 1); in lowerInlineAsm()
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| H A D | Utils.cpp | 195 I.tieOperands(DefIdx, OpI); in constrainSelectedInstRegOperands()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.cpp | 1216 MI->tieOperands(Def++, Use); in EmitMachineNode()
1393 MIB->tieOperands(DefIdx + j, UseIdx + j); in EmitSpecialNode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 533 NewMI->tieOperands(0, NewMI->getNumOperands() - 1); in optimizeSelect()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterInfo.cpp | 878 MI.tieOperands(1, 3); in createScratchRegisterForInstruction()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstr.h | 1641 void tieOperands(unsigned DefIdx, unsigned UseIdx);
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonExpandCondsets.cpp | 524 DefI->tieOperands(DefIdx, DefI->getNumOperands()-1); in updateDeadsInRange()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/MIRParser/ |
| H A D | MIParser.cpp | 1733 MI.tieOperands(TiedPair.first, TiedPair.second); in assignRegisterTies()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 2393 NewMI->tieOperands(0, NewMI->getNumOperands() - 1); in optimizeSelect()
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