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Searched refs:subreg (Results 1 – 17 of 17) sorted by relevance

/freebsd/contrib/llvm-project/lldb/source/Plugins/ABI/X86/
H A DABIX86.cpp74 for (const RegData *subreg : subregs) { in addPartialRegisters() local
75 assert(subreg); in addPartialRegisters()
76 uint32_t base_index = *subreg->base_index; in addPartialRegisters()
82 lldb_private::ConstString(subreg->subreg_name), in addPartialRegisters()
233 for (const auto &subreg : x.second) in AugmentRegisterInfo() local
234 subreg_name_set.insert(subreg.subreg_name); in AugmentRegisterInfo()
248 for (auto &subreg : found->second) { in AugmentRegisterInfo() local
250 subreg.base_index = x.index(); in AugmentRegisterInfo()
252 subreg_by_kind[static_cast<size_t>(subreg.subreg_kind)].push_back( in AugmentRegisterInfo()
253 &subreg); in AugmentRegisterInfo()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchRegisterInfo.td34 class LoongArchReg64<LoongArchReg32 subreg>
35 : LoongArchRegWithSubRegs<subreg.HWEncoding, subreg.AsmName, [subreg],
36 subreg.AltNames> {
41 class LoongArchReg128<LoongArchReg64 subreg, string n>
42 : LoongArchRegWithSubRegs<subreg.HWEncoding, n, [subreg]> {
47 class LoongArchReg256<LoongArchReg128 subreg, string n>
48 : LoongArchRegWithSubRegs<subreg.HWEncoding, n, [subreg]> {
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYRegisterInfo.td32 class CSKYFReg64<CSKYFReg32 subreg> : Register<""> {
33 let HWEncoding{4 - 0} = subreg.HWEncoding{4 - 0};
34 let SubRegs = [subreg];
36 let AsmName = subreg.AsmName;
37 let AltNames = subreg.AltNames;
40 class CSKYFReg128<CSKYFReg64 subreg> : Register<""> {
41 let HWEncoding{4 - 0} = subreg.HWEncoding{4 - 0};
42 let SubRegs = [subreg];
44 let AsmName = subreg.AsmName;
45 let AltNames = subreg.AltNames;
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.td32 class RISCVReg32<RISCVReg16 subreg>
33 : RISCVRegWithSubRegs<subreg.HWEncoding{4-0}, subreg.AsmName, [subreg],
34 subreg.AltNames> {
42 class RISCVReg64<RISCVReg32 subreg>
43 : RISCVRegWithSubRegs<subreg.HWEncoding{4-0}, subreg.AsmName, [subreg],
44 subreg.AltNames> {
/freebsd/usr.sbin/pciconf/
H A Dpciconf.c308 print_bus_range(int fd, struct pci_conf *p, int secreg, int subreg) in print_bus_range() argument
313 subbus = read_config(fd, &p->pc_sel, subreg, 1); in print_bus_range()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrVector.td44 // subreg of the result.
1794 // vector register. Scalar to vector conversion is just a subreg and
1797 SubRegIndex subreg> {
1799 (INSERT_SUBREG (vt (IMPLICIT_DEF)), cls:$scalar, subreg)>;
1802 subreg), 0)>;
1820 // than 0) and then taking a high subreg. The AddedComplexity counters the
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrGISel.td515 // Match stores from lane 0 to the appropriate subreg's store.
H A DAArch64InstrInfo.td4150 // Match stores from lane 0 to the appropriate subreg's store.
4292 // Match stores from lane 0 to the appropriate subreg's store.
4443 // Match stores from lane 0 to the appropriate subreg's store.
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86RegisterInfo.td622 // that support 8-bit subreg operations. On x86-64, GR16_ABCD, GR32_ABCD,
H A DX86InstrAVX512.td4011 SubRegIndex subreg> {
4018 … (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), MaskRC:$mask, subreg)), VK1WM),
4030 SubRegIndex subreg> {
4038 … (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), MaskRC:$mask, subreg)), VK1WM),
4044 … (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), MaskRC:$mask, subreg)), VK1WM),
4074 SubRegIndex subreg> {
4081 … (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), MaskRC:$mask, subreg)), VK1WM),
4091 … (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), MaskRC:$mask, subreg)), VK1WM),
4103 SubRegIndex subreg> {
4110 … (COPY_TO_REGCLASS (i32 (INSERT_SUBREG (IMPLICIT_DEF), MaskRC:$mask, subreg)), VK1WM),
[all …]
H A DX86InstrCompiler.td1575 // Depositing value to 8/16 bit subreg:
/freebsd/contrib/llvm-project/llvm/include/llvm/Support/
H A DTargetOpcodes.def100 // the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFeatures.td285 def FeatureSlowLoadDSubreg : SubtargetFeature<"slow-load-D-subreg",
H A DARMInstrInfo.td480 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
485 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
490 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
495 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
502 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
509 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstructions.td797 (outs rc:$vdst), (ins rc:$vsrc, val_ty:$val, i32imm:$subreg)> {
860 (outs rc:$vdst), (ins rc:$vsrc, VSrc_b32:$val, SSrc_b32:$idx, i32imm:$subreg)> {
881 (outs VGPR_32:$vdst), (ins rc:$vsrc, SSrc_b32:$idx, i32imm:$subreg)> {
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTarget.td673 bit isExtractSubreg = false; // Is this instruction a kind of extract subreg?
676 bit isInsertSubreg = false; // Is this instruction a kind of insert subreg?
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMips64InstrInfo.td814 // lower subreg would not be replicated into the upper half.