/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | EvergreenInstructions.td | 311 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), $data, sub0), $ptr), sub1)>; 322 $ptr), sub1)>; 439 (BFI_INT_eg (i32 (EXTRACT_SUBREG R600_Reg64:$x, sub1)), 440 (i32 (EXTRACT_SUBREG R600_Reg64:$y, sub1)), 441 (i32 (EXTRACT_SUBREG R600_Reg64:$z, sub1))), sub1) 458 (BFI_INT_eg (i32 (EXTRACT_SUBREG R600_Reg64:$x, sub1)), 459 (i32 (EXTRACT_SUBREG R600_Reg64:$y, sub1)), 460 (i32 (EXTRACT_SUBREG R600_Reg64:$z, sub1))), sub1) 471 (i32 (EXTRACT_SUBREG R600_Reg64:$src1, sub1))) 479 (i32 (EXTRACT_SUBREG R600_Reg64:$src0, sub1)), [all …]
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H A D | SIInstructions.td | 1271 (V_BCNT_U32_B32_e64 (i32 (EXTRACT_SUBREG i64:$src, sub1)), 1273 (i32 (V_MOV_B32_e32 (i32 0))), sub1) 1285 (REG_SEQUENCE RC, $elem, sub0, (elem_type (EXTRACT_SUBREG $vec, sub1)), sub1) 1290 (REG_SEQUENCE RC, (elem_type (EXTRACT_SUBREG $vec, sub0)), sub0, $elem, sub1) 1958 (f32 (COPY_TO_REGCLASS (S_XOR_B32 (i32 (EXTRACT_SUBREG $src, sub1)), 1960 SReg_32)), sub1)) 1969 (f32 (COPY_TO_REGCLASS (S_AND_B32 (i32 (EXTRACT_SUBREG $src, sub1)), 1971 SReg_32)), sub1)) 1980 (f32 (COPY_TO_REGCLASS (S_OR_B32 (i32 (EXTRACT_SUBREG $src, sub1)), 1982 SReg_32)), sub1)) [all …]
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H A D | SIRegisterInfo.td | 44 list<SubRegIndex> ret2 = [sub0, sub1]; 45 list<SubRegIndex> ret3 = [sub0, sub1, sub2]; 46 list<SubRegIndex> ret4 = [sub0, sub1, sub2, sub3]; 47 list<SubRegIndex> ret5 = [sub0, sub1, sub2, sub3, sub4]; 48 list<SubRegIndex> ret6 = [sub0, sub1, sub2, sub3, sub4, sub5]; 49 list<SubRegIndex> ret7 = [sub0, sub1, sub2, sub3, sub4, sub5, sub6]; 50 list<SubRegIndex> ret8 = [sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7]; 51 list<SubRegIndex> ret9 = [sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7, sub8]; 52 list<SubRegIndex> ret10 = [sub0, sub1, sub2, sub3, 55 list<SubRegIndex> ret11 = [sub0, sub1, sub2, sub3, [all …]
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H A D | R600RegisterInfo.cpp | 26 R600::sub0, R600::sub1, R600::sub2, R600::sub3, in getSubRegFromChannel()
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H A D | R600RegisterInfo.td | 23 let SubRegIndices = [sub0, sub1, sub2, sub3]; 32 let SubRegIndices = [sub0, sub1];
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H A D | GCNPreRAOptimizations.cpp | 164 case AMDGPU::sub1: in processReg()
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H A D | SIInstrInfo.cpp | 2187 Register DstHi = RI.getSubReg(Dst, AMDGPU::sub1); in expandPostRAPseudo() 2240 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1)) in expandPostRAPseudo() 2262 Register DstHi = RI.getSubReg(Dst, AMDGPU::sub1); in expandPostRAPseudo() 2452 Register RegHi = RI.getSubReg(Reg, AMDGPU::sub1); in expandPostRAPseudo() 2548 Register DstHi = RI.getSubReg(Dst, AMDGPU::sub1); in expandPostRAPseudo() 2665 for (auto Sub : { AMDGPU::sub0, AMDGPU::sub1 }) { in expandMovDPP64() 2704 .addImm(AMDGPU::sub1); in expandMovDPP64() 2918 .addReg(PCReg, RegState::Define, AMDGPU::sub1) in insertIndirectBranch() 2919 .addReg(PCReg, 0, AMDGPU::sub1) in insertIndirectBranch() 3305 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, in insertSelect() [all …]
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H A D | AMDGPUInstructionSelector.cpp | 272 case AMDGPU::sub1: in getSubOperand64() 367 MachineOperand Hi1(getSubOperand64(I.getOperand(1), HalfRC, AMDGPU::sub1)); in selectG_ADD_SUB() 368 MachineOperand Hi2(getSubOperand64(I.getOperand(2), HalfRC, AMDGPU::sub1)); in selectG_ADD_SUB() 404 .addImm(AMDGPU::sub1); in selectG_ADD_SUB() 1431 .addImm(AMDGPU::sub1); in selectBallot() 2239 .addReg(SrcReg, 0, AMDGPU::sub1); in selectG_TRUNC() 2376 .addImm(AMDGPU::sub1); in selectG_SZA_EXT() 2440 .addImm(AMDGPU::sub1); in selectG_SZA_EXT() 2461 .addImm(AMDGPU::sub1); in selectG_SZA_EXT() 2596 .addImm(AMDGPU::sub1); in selectG_CONSTANT() [all …]
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H A D | R600Instructions.td | 1738 def : Extract_Element <f32, v4f32, 1, sub1>; 1743 def : Insert_Element <f32, v4f32, 1, sub1>; 1748 def : Extract_Element <i32, v4i32, 1, sub1>; 1753 def : Insert_Element <i32, v4i32, 1, sub1>; 1758 def : Extract_Element <f32, v2f32, 1, sub1>; 1761 def : Insert_Element <f32, v2f32, 1, sub1>; 1764 def : Extract_Element <i32, v2i32, 1, sub1>; 1767 def : Insert_Element <i32, v2i32, 1, sub1>;
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H A D | SIFrameLowering.cpp | 185 Register TargetHi = TRI->getSubReg(TargetReg, AMDGPU::sub1); in buildGitPtr() 427 FlatScrInitHi = TRI->getSubReg(FlatScrInit, AMDGPU::sub1); in emitEntryFunctionFlatScratchInit() 466 FlatScrInitHi = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub1); in emitEntryFunctionFlatScratchInit() 820 Register Rsrc1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1); in emitEntryFunctionScratchRsrcRegSetup() 857 Register ScratchRsrcSub1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1); in emitEntryFunctionScratchRsrcRegSetup() 1693 SavedRegs.set(TRI->getSubReg(RetAddrReg, AMDGPU::sub1)); in determineCalleeSavesSGPR()
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H A D | VOP2Instructions.td | 880 (i32 (EXTRACT_SUBREG $src0, sub1)), 881 (i32 (EXTRACT_SUBREG $src1, sub1)) 882 ), sub1 895 (InstHi $src0, $src1), sub1) 1049 (i32 (EXTRACT_SUBREG $src0, sub1)), 1050 (i32 (EXTRACT_SUBREG $src1, sub1)))), sub1) 1059 (i32 (EXTRACT_SUBREG $src0, sub1)), 1060 (i32 (EXTRACT_SUBREG $src1, sub1)))), sub1) 1155 (V_MOV_B32_e32 (i32 0)), sub1)
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H A D | VOP3Instructions.td | 404 ), VGPR_32)), sub1) 753 (V_OR3_B32_e64 (i32 (EXTRACT_SUBREG $src0, sub1)), 754 (i32 (EXTRACT_SUBREG $src1, sub1)), 755 (i32 (EXTRACT_SUBREG $src2, sub1))), sub1)>; 775 (i32 (IMPLICIT_DEF)), sub1), 787 (i32 (IMPLICIT_DEF)), sub1),
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H A D | R600MachineScheduler.cpp | 253 case R600::sub1: in getAluKind()
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H A D | AMDGPUISelDAGToDAG.cpp | 436 SDValue(Hi, 0), CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32)}; in buildSMovImm64() 579 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32); in Select() 855 SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32); in SelectADD_SUB_I64() 1060 SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, SL, MVT::i32); in SelectMUL_LOHI() 1696 SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32); in SelectFlatOffsetImpl() 2109 CurDAG->getTargetConstant(AMDGPU::sub1, SL, MVT::i32), in Expand32BitAddress() 3053 Undef, CurDAG->getTargetConstant(AMDGPU::sub1, SL, MVT::i32) }; in SelectVOP3PMods()
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H A D | BUFInstructions.td | 1374 (REG_SEQUENCE VReg_64, VGPR_32:$vindex, sub0, VGPR_32:$voffset, sub1), 1483 (REG_SEQUENCE VReg_64, VGPR_32:$vindex, sub0, VGPR_32:$voffset, sub1), 1706 (REG_SEQUENCE VReg_64, VGPR_32:$vindex, sub0, VGPR_32:$voffset, sub1), 1814 (REG_SEQUENCE VReg_64, VGPR_32:$vindex, sub0, VGPR_32:$voffset, sub1), 1861 defvar SubHi = !if(!eq(vt, i32), sub1, sub2_sub3); 1905 (REG_SEQUENCE VReg_64, VGPR_32:$vindex, sub0, VGPR_32:$voffset, sub1), 2203 (REG_SEQUENCE VReg_64, VGPR_32:$vindex, sub0, VGPR_32:$voffset, sub1), 2276 (REG_SEQUENCE VReg_64, VGPR_32:$vindex, sub0, VGPR_32:$voffset, sub1),
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H A D | SIISelLowering.cpp | 5016 MI, MRI, Src0, BoolRC, AMDGPU::sub1, &AMDGPU::SReg_32RegClass); in EmitInstrWithCustomInserter() 5021 MI, MRI, Src1, BoolRC, AMDGPU::sub1, &AMDGPU::SReg_32RegClass); in EmitInstrWithCustomInserter() 5035 .addImm(AMDGPU::sub1); in EmitInstrWithCustomInserter() 5082 TRI->getSubRegisterClass(Src1RC, AMDGPU::sub1); in EmitInstrWithCustomInserter() 5090 MI, MRI, Src0, Src0RC, AMDGPU::sub1, Src0SubRC); in EmitInstrWithCustomInserter() 5092 MI, MRI, Src1, Src1RC, AMDGPU::sub1, Src1SubRC); in EmitInstrWithCustomInserter() 5114 .addImm(AMDGPU::sub1); in EmitInstrWithCustomInserter() 5172 MII, MRI, Src2, Src2RC, AMDGPU::sub1, SubRC); in EmitInstrWithCustomInserter() 5254 .addImm(AMDGPU::sub1); in EmitInstrWithCustomInserter() 5309 TRI->getSubRegisterClass(Src1RC, AMDGPU::sub1); in EmitInstrWithCustomInserter() [all …]
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H A D | SILoadStoreOptimizer.cpp | 1834 {AMDGPU::sub1, AMDGPU::sub1_sub2, AMDGPU::sub1_sub2_sub3, AMDGPU::sub1_sub2_sub3_sub4}, in getSubRegIdxs() 1986 .addImm(AMDGPU::sub1); in computeBase()
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H A D | SMInstructions.td | 1103 (S_MOV_B32 (i32 0)), sub1)> { 1143 (i64 (REG_SEQUENCE SReg_64, $sbase, sub0, (i32 (S_MOV_B32 (i32 0))), sub1)),
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H A D | SOPInstructions.td | 1804 (S_MOV_B32 (i32 0)), sub1)) 1933 (S_MOV_B32 (i32 0)), sub1) 1939 … (COPY_TO_REGCLASS (S_ASHR_I32 (i32 (S_SEXT_I32_I16 $src)), (S_MOV_B32 (i32 31))), SGPR_32)), sub1)
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/freebsd/sys/contrib/device-tree/Bindings/net/wireless/ |
H A D | marvell-8xxx.txt | 28 "marvell,caldata-txpwrlimit-5g-sub1" (length = 688).
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/freebsd/contrib/llvm-project/llvm/include/llvm/Target/GlobalISel/ |
H A D | Combine.td | 1720 (match (G_SUB $sub1, $A, $B), 1722 (G_ADD $root, $sub1, $sub2)), 1728 (match (G_SUB $sub1, $A, $B), 1730 (G_ADD $root, $sub1, $sub2)), 1737 (G_SUB $sub1, $B, $add1), 1738 (G_ADD $root, $A, $sub1)), 1745 (G_SUB $sub1, $B, $add1), 1746 (G_ADD $root, $A, $sub1)),
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/freebsd/contrib/file/magic/Magdir/ |
H A D | icc | 71 # Profile version major.4bit-minor.sub1.sub2 like 4.3.0.0 (04300000h)
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/freebsd/usr.bin/vgrind/ |
H A D | vgrindefs.src | 91 stjoin sub1 t times tnull tokno ttype:
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/freebsd/contrib/googletest/googlemock/test/ |
H A D | gmock-matchers-comparisons_test.cc | 2230 AmbiguousCastTypes::DerivedSub1 sub1; in TEST() local 2244 as_base_ptr = &sub1; in TEST()
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/freebsd/sys/contrib/device-tree/src/arm/rockchip/ |
H A D | rk3288-veyron-jerry.dts | 121 marvell,caldata-txpwrlimit-5g-sub1 = /bits/ 8 <
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