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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DEvergreenInstructions.td311 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), $data, sub0), $ptr), sub1)>;
321 $data, sub0),
436 (BFI_INT_eg (i32 (EXTRACT_SUBREG R600_Reg64:$x, sub0)),
437 (i32 (EXTRACT_SUBREG R600_Reg64:$y, sub0)),
438 (i32 (EXTRACT_SUBREG R600_Reg64:$z, sub0))), sub0,
455 (BFI_INT_eg (i32 (EXTRACT_SUBREG R600_Reg64:$x, sub0)),
456 (i32 (EXTRACT_SUBREG R600_Reg64:$y, sub0)),
457 (i32 (EXTRACT_SUBREG R600_Reg64:$z, sub0))), sub0,
477 (i32 (EXTRACT_SUBREG $src0, sub0)), sub0,
486 (i32 (EXTRACT_SUBREG $src0, sub0)), sub0,
[all …]
H A DSIInstructions.td1272 (i32 (V_BCNT_U32_B32_e64 (i32 (EXTRACT_SUBREG i64:$src, sub0)), (i32 0)))), sub0,
1285 (REG_SEQUENCE RC, $elem, sub0, (elem_type (EXTRACT_SUBREG $vec, sub1)), sub1)
1290 (REG_SEQUENCE RC, (elem_type (EXTRACT_SUBREG $vec, sub0)), sub0, $elem, sub1)
1955 (f32 (COPY_TO_REGCLASS (S_XOR_B32 (i32 (EXTRACT_SUBREG $src, sub0)),
1957 SReg_32)), sub0,
1966 (f32 (COPY_TO_REGCLASS (S_AND_B32 (i32 (EXTRACT_SUBREG $src, sub0)),
1968 SReg_32)), sub0,
1977 (f32 (COPY_TO_REGCLASS (S_OR_B32 (i32 (EXTRACT_SUBREG $src, sub0)),
1979 SReg_32)), sub0,
1989 (i32 (EXTRACT_SUBREG SReg_64:$src, sub0)),
[all …]
H A DSIMachineFunctionInfo.cpp194 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SGPR_128RegClass)); in addPrivateSegmentBuffer()
201 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass)); in addDispatchPtr()
208 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass)); in addQueuePtr()
216 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass)); in addKernargSegmentPtr()
223 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass)); in addDispatchID()
230 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass)); in addFlatScratchInit()
243 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass)); in addImplicitBufferPtr()
264 TRI.getMatchingSuperReg(getNextUserSGPR(), AMDGPU::sub0, RC); in addPreloadedKernArg()
H A DSIRegisterInfo.td44 list<SubRegIndex> ret2 = [sub0, sub1];
45 list<SubRegIndex> ret3 = [sub0, sub1, sub2];
46 list<SubRegIndex> ret4 = [sub0, sub1, sub2, sub3];
47 list<SubRegIndex> ret5 = [sub0, sub1, sub2, sub3, sub4];
48 list<SubRegIndex> ret6 = [sub0, sub1, sub2, sub3, sub4, sub5];
49 list<SubRegIndex> ret7 = [sub0, sub1, sub2, sub3, sub4, sub5, sub6];
50 list<SubRegIndex> ret8 = [sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7];
51 list<SubRegIndex> ret9 = [sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7, sub8];
52 list<SubRegIndex> ret10 = [sub0, sub1, sub2, sub3,
55 list<SubRegIndex> ret11 = [sub0, sub1, sub2, sub3,
[all …]
H A DSIInstrInfo.cpp2186 Register DstLo = RI.getSubReg(Dst, AMDGPU::sub0); in expandPostRAPseudo()
2237 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0)) in expandPostRAPseudo()
2261 Register DstLo = RI.getSubReg(Dst, AMDGPU::sub0); in expandPostRAPseudo()
2451 Register RegLo = RI.getSubReg(Reg, AMDGPU::sub0); in expandPostRAPseudo()
2665 for (auto Sub : { AMDGPU::sub0, AMDGPU::sub1 }) { in expandMovDPP64()
2702 .addImm(AMDGPU::sub0) in expandMovDPP64()
2914 .addReg(PCReg, RegState::Define, AMDGPU::sub0) in insertIndirectBranch()
2915 .addReg(PCReg, 0, AMDGPU::sub0) in insertIndirectBranch()
3305 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, in insertSelect()
3434 case AMDGPU::sub0: in foldImmediate()
[all …]
H A DR600RegisterInfo.cpp26 R600::sub0, R600::sub1, R600::sub2, R600::sub3, in getSubRegFromChannel()
H A DAMDGPUInstructionSelector.cpp270 case AMDGPU::sub0: in getSubOperand64()
365 MachineOperand Lo1(getSubOperand64(I.getOperand(1), HalfRC, AMDGPU::sub0)); in selectG_ADD_SUB()
366 MachineOperand Lo2(getSubOperand64(I.getOperand(2), HalfRC, AMDGPU::sub0)); in selectG_ADD_SUB()
402 .addImm(AMDGPU::sub0) in selectG_ADD_SUB()
1429 .addImm(AMDGPU::sub0) in selectBallot()
1979 unsigned SubReg = Is64 ? AMDGPU::sub0_sub1 : AMDGPU::sub0; in selectImageIntrinsic()
2175 return AMDGPU::sub0; in sizeToSubRegIndex()
2186 return AMDGPU::sub0; in sizeToSubRegIndex()
2237 .addReg(SrcReg, 0, AMDGPU::sub0); in selectG_TRUNC()
2374 .addImm(AMDGPU::sub0) in selectG_SZA_EXT()
[all …]
H A DR600RegisterInfo.td23 let SubRegIndices = [sub0, sub1, sub2, sub3];
32 let SubRegIndices = [sub0, sub1];
H A DGCNPreRAOptimizations.cpp158 case AMDGPU::sub0: in processReg()
H A DVOP3Instructions.td401 (i32 (V_BFE_I32_e64 $src, (S_MOV_B32 (i32 0)), (S_MOV_B32 (i32 0x10)))), sub0,
750 (V_OR3_B32_e64 (i32 (EXTRACT_SUBREG $src0, sub0)),
751 (i32 (EXTRACT_SUBREG $src1, sub0)),
752 (i32 (EXTRACT_SUBREG $src2, sub0))), sub0,
774 $src2, sub0,
777 sub0)
786 $src2, sub0,
789 sub0)
796 (EXTRACT_SUBREG (inst i32:$src0, i32:$src1, (i64 (as_i64imm $src2)), 0 /* clamp */), sub0)
H A DR600Instructions.td1737 def : Extract_Element <f32, v4f32, 0, sub0>;
1742 def : Insert_Element <f32, v4f32, 0, sub0>;
1747 def : Extract_Element <i32, v4i32, 0, sub0>;
1752 def : Insert_Element <i32, v4i32, 0, sub0>;
1757 def : Extract_Element <f32, v2f32, 0, sub0>;
1760 def : Insert_Element <f32, v2f32, 0, sub0>;
1763 def : Extract_Element <i32, v2i32, 0, sub0>;
1766 def : Insert_Element <i32, v2i32, 0, sub0>;
H A DSIFrameLowering.cpp184 Register TargetLo = TRI->getSubReg(TargetReg, AMDGPU::sub0); in buildGitPtr()
426 FlatScrInitLo = TRI->getSubReg(FlatScrInit, AMDGPU::sub0); in emitEntryFunctionFlatScratchInit()
465 FlatScrInitLo = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub0); in emitEntryFunctionFlatScratchInit()
819 Register Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0); in emitEntryFunctionScratchRsrcRegSetup()
856 Register ScratchRsrcSub0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0); in emitEntryFunctionScratchRsrcRegSetup()
1692 SavedRegs.set(TRI->getSubReg(RetAddrReg, AMDGPU::sub0)); in determineCalleeSavesSGPR()
H A DVOP2Instructions.td876 (i32 (EXTRACT_SUBREG $src0, sub0)),
877 (i32 (EXTRACT_SUBREG $src1, sub0))
878 ), sub0,
894 (InstLo $src0, $src1), sub0,
1046 (i32 (EXTRACT_SUBREG $src0, sub0)),
1047 (i32 (EXTRACT_SUBREG $src1, sub0)))), sub0,
1056 (i32 (EXTRACT_SUBREG $src0, sub0)),
1057 (i32 (EXTRACT_SUBREG $src1, sub0)))), sub0,
1154 (inst $src0, $src1), sub0,
H A DAMDGPUISelDAGToDAG.cpp435 SDValue(Lo, 0), CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32), in buildSMovImm64()
578 SubReg0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32); in Select()
854 SDValue Sub0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32); in SelectADD_SUB_I64()
1054 SDValue Sub0 = CurDAG->getTargetConstant(AMDGPU::sub0, SL, MVT::i32); in SelectMUL_LOHI()
1695 SDValue Sub0 = CurDAG->getTargetConstant(AMDGPU::sub0, DL, MVT::i32); in SelectFlatOffsetImpl()
2106 CurDAG->getTargetConstant(AMDGPU::sub0, SL, MVT::i32), in Expand32BitAddress()
3022 (VecSize > 32) ? AMDGPU::sub0_sub1 : AMDGPU::sub0, SDLoc(In), in SelectVOP3PMods()
3028 (VecSize > 32) ? AMDGPU::sub0_sub1 : AMDGPU::sub0, SDLoc(In), in SelectVOP3PMods()
3052 Lo, CurDAG->getTargetConstant(AMDGPU::sub0, SL, MVT::i32), in SelectVOP3PMods()
H A DR600MachineScheduler.cpp251 case R600::sub0: in getAluKind()
H A DBUFInstructions.td1374 (REG_SEQUENCE VReg_64, VGPR_32:$vindex, sub0, VGPR_32:$voffset, sub1),
1483 (REG_SEQUENCE VReg_64, VGPR_32:$vindex, sub0, VGPR_32:$voffset, sub1),
1605 !if(!eq(vt, i32), sub0, sub0_sub1)),
1617 !if(!eq(vt, i32), sub0, sub0_sub1)),
1706 (REG_SEQUENCE VReg_64, VGPR_32:$vindex, sub0, VGPR_32:$voffset, sub1),
1814 (REG_SEQUENCE VReg_64, VGPR_32:$vindex, sub0, VGPR_32:$voffset, sub1),
1860 defvar SubLo = !if(!eq(vt, i32), sub0, sub0_sub1);
1905 (REG_SEQUENCE VReg_64, VGPR_32:$vindex, sub0, VGPR_32:$voffset, sub1),
2203 (REG_SEQUENCE VReg_64, VGPR_32:$vindex, sub0, VGPR_32:$voffset, sub1),
2276 (REG_SEQUENCE VReg_64, VGPR_32:$vindex, sub0, VGPR_32:$voffset, sub1),
H A DSIRegisterInfo.cpp325 assert(getSubRegIndexLaneMask(AMDGPU::sub0).getAsInteger() == 3 && in SIRegisterInfo()
329 getSubRegIndexLaneMask(AMDGPU::sub0).getAsInteger() && in SIRegisterInfo()
556 return getMatchingSuperReg(BaseReg, AMDGPU::sub0, RC); in getAlignedHighSGPRForRC()
2507 ConstOffsetReg = getSubReg(MIB.getReg(1), AMDGPU::sub0); in eliminateFrameIndex()
H A DSIISelLowering.cpp4610 return std::pair(AMDGPU::sub0, Offset); in computeIndirectRegAndOffset()
5014 MI, MRI, Src0, BoolRC, AMDGPU::sub0, &AMDGPU::SReg_32RegClass); in EmitInstrWithCustomInserter()
5019 MI, MRI, Src1, BoolRC, AMDGPU::sub0, &AMDGPU::SReg_32RegClass); in EmitInstrWithCustomInserter()
5033 .addImm(AMDGPU::sub0) in EmitInstrWithCustomInserter()
5080 TRI->getSubRegisterClass(Src0RC, AMDGPU::sub0); in EmitInstrWithCustomInserter()
5085 MI, MRI, Src0, Src0RC, AMDGPU::sub0, Src0SubRC); in EmitInstrWithCustomInserter()
5087 MI, MRI, Src1, Src1RC, AMDGPU::sub0, Src1SubRC); in EmitInstrWithCustomInserter()
5112 .addImm(AMDGPU::sub0) in EmitInstrWithCustomInserter()
5168 TRI->getSubRegisterClass(Src2RC, AMDGPU::sub0); in EmitInstrWithCustomInserter()
5170 MII, MRI, Src2, Src2RC, AMDGPU::sub0, SubRC); in EmitInstrWithCustomInserter()
[all …]
H A DDSInstructions.td861 (inst $ptr, (i32 (EXTRACT_SUBREG VReg_64:$value, sub0)),
1164 sub0)
1178 sub0)
H A DSILoadStoreOptimizer.cpp1833 {AMDGPU::sub0, AMDGPU::sub0_sub1, AMDGPU::sub0_sub1_sub2, AMDGPU::sub0_sub1_sub2_sub3}, in getSubRegIdxs()
1984 .addImm(AMDGPU::sub0) in computeBase()
/freebsd/sys/contrib/device-tree/Bindings/net/wireless/
H A Dmarvell-8xxx.txt27 "marvell,caldata-txpwrlimit-5g-sub0" (length = 502).
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp385 unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0); in IsAGPROperand()
1042 unsigned VdataSub0 = MRI.getSubReg(Vdata0, AMDGPU::sub0); in convertMIMGInst()
1045 NewVdata = MRI.getMatchingSuperReg(Vdata0, AMDGPU::sub0, in convertMIMGInst()
1061 unsigned VAddrSubSA = MRI.getSubReg(VAddrSA, AMDGPU::sub0); in convertMIMGInst()
1065 NewVAddrSA = MRI.getMatchingSuperReg(VAddrSA, AMDGPU::sub0, in convertMIMGInst()
/freebsd/contrib/one-true-awk/
H A DChangeLog195 * regdir/t.sub0: Renamed from regdir/t.sub.
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ExpandPseudoInsts.cpp769 unsigned sub0 = (Opc == AArch64::LDR_ZXI || Opc == AArch64::STR_ZXI) in expandSVESpillFill() local
781 .addReg(TRI->getSubReg(MI.getOperand(0).getReg(), sub0 + Offset), in expandSVESpillFill()
/freebsd/sys/contrib/device-tree/src/arm/rockchip/
H A Drk3288-veyron-jerry.dts87 marvell,caldata-txpwrlimit-5g-sub0 = /bits/ 8 <

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