Home
last modified time | relevance | path

Searched refs:src2 (Results 1 – 25 of 159) sorted by relevance

1234567

/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonDepMapAsm2Intrin.td20 def: Pat<(int_hexagon_A2_add IntRegs:$src1, IntRegs:$src2),
21 (A2_add IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
22 def: Pat<(int_hexagon_A2_addh_h16_hh IntRegs:$src1, IntRegs:$src2),
23 (A2_addh_h16_hh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
24 def: Pat<(int_hexagon_A2_addh_h16_hl IntRegs:$src1, IntRegs:$src2),
25 (A2_addh_h16_hl IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
26 def: Pat<(int_hexagon_A2_addh_h16_lh IntRegs:$src1, IntRegs:$src2),
27 (A2_addh_h16_lh IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
28 def: Pat<(int_hexagon_A2_addh_h16_ll IntRegs:$src1, IntRegs:$src2),
29 (A2_addh_h16_ll IntRegs:$src1, IntRegs:$src2)>, Requires<[HasV5]>;
[all …]
H A DHexagonMapAsm2IntrinV62.gen.td10 def: Pat<(IntID HvxVR:$src1, IntRegs:$src2),
11 (MI HvxVR:$src1, IntRegs:$src2)>;
12 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, IntRegs:$src2),
13 (MI HvxVR:$src1, IntRegs:$src2)>;
17 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3),
18 (MI HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>;
19 def: Pat<(!cast<Intrinsic>(IntID#"_128B") HvxVR:$src1, HvxVR:$src2,
21 (MI HvxVR:$src1, HvxVR:$src2, IntRegsLow8:$src3)>;
25 def: Pat<(IntID HvxVR:$src1, HvxVR:$src2),
26 (MI HvxVR:$src1, HvxVR:$src2)>;
[all …]
H A DHexagonIntrinsicsV60.td115 def: Pat<(IntID HvxWR:$src1, IntRegs:$src2),
116 (MI HvxWR:$src1, IntRegs:$src2)>;
118 def: Pat<(!cast<Intrinsic>(IntID#"_128B")HvxWR:$src1, IntRegs:$src2),
119 (MI HvxWR:$src1, IntRegs:$src2)>;
123 def: Pat<(IntID HvxVR:$src1, IntRegs:$src2),
124 (MI HvxVR:$src1, IntRegs:$src2)>;
126 def: Pat<(!cast<Intrinsic>(IntID#"_128B")HvxVR:$src1, IntRegs:$src2),
127 (MI HvxVR:$src1, IntRegs:$src2)>;
131 def: Pat<(IntID HvxWR:$src1, HvxVR:$src2),
132 (MI HvxWR:$src1, HvxVR:$src2)>;
[all …]
H A DHexagonIntrinsics.td127 def : Pat <(int_hexagon_C2_cmpgei I32:$src1, s32_0ImmPred_timm:$src2),
128 (C2_tfrpr (C2_cmpgti I32:$src1, (SDEC1 s32_0ImmPred:$src2)))>;
130 def : Pat <(int_hexagon_C2_cmpgeui I32:$src1, u32_0ImmPred_timm:$src2),
131 (C2_tfrpr (C2_cmpgtui I32:$src1, (UDEC1 u32_0ImmPred:$src2)))>;
135 def : Pat <(int_hexagon_C2_cmplt I32:$src1, I32:$src2),
136 (C2_tfrpr (C2_cmpgt I32:$src2, I32:$src1))>;
137 def : Pat <(int_hexagon_C2_cmpltu I32:$src1, I32:$src2),
138 (C2_tfrpr (C2_cmpgtu I32:$src2, I32:$src1))>;
145 : Pat <(IntID I32:$src1, I32:$src2, u4_0ImmPred_timm:$src3, u5_0ImmPred_timm:$src4),
146 (OutputInst I32:$src1, I32:$src2, u4_0ImmPred:$src3,
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrXOP.td97 (ins VR128:$src1, VR128:$src2),
98 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
100 (vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2))))]>,
103 (ins VR128:$src1, i128mem:$src2),
104 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
107 (vt128 (load addr:$src2)))))]>,
110 (ins i128mem:$src1, VR128:$src2),
111 !strconcat(OpcodeStr, "\t{$src2,
[all...]
H A DX86InstrAMX.td66 GR16:$src2,
70 GR16:$src2,
74 GR16:$src2, opaquemem:$src3,
78 def PTILEZEROV : PseudoI<(outs TILE:$dst), (ins GR16:$src1, GR16:$src2),
80 GR16:$src1, GR16:$src2))]>;
86 def PTILELOADD : PseudoI<(outs), (ins u8imm:$src1, sibmem:$src2), []>;
89 sibmem:$src2), []>;
102 (ins TILE:$src1, TILE:$src2, TILE:$src3),
103 "tdpbssd\t{$src3, $src2, $dst|$dst, $src2, $src3}", []>,
106 (ins TILE:$src1, TILE:$src2, TILE:$src3),
[all …]
H A DX86InstrShiftRotate.td304 def : Pat<(rotl GR8:$src1, (i8 relocImm:$src2)),
305 (ROL8ri GR8:$src1, relocImm:$src2)>;
306 def : Pat<(rotl GR16:$src1, (i8 relocImm:$src2)),
307 (ROL16ri GR16:$src1, relocImm:$src2)>;
308 def : Pat<(rotl GR32:$src1, (i8 relocImm:$src2)),
309 (ROL32ri GR32:$src1, relocImm:$src2)>;
310 def : Pat<(rotl GR64:$src1, (i8 relocImm:$src2)),
311 (ROL64ri GR64:$src1, relocImm:$src2)>;
313 def : Pat<(rotr GR8:$src1, (i8 relocImm:$src2)),
314 (ROR8ri GR8:$src1, relocImm:$src2)>;
[all...]
H A DX86InstrFMA.td40 (ins RC:$src1, RC:$src2, RC:$src3),
42 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
43 [(set RC:$dst, (VT (Op RC:$src2, RC:$src1, RC:$src3)))]>,
48 (ins RC:$src1, RC:$src2, x86memop:$src3),
50 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
51 [(set RC:$dst, (VT (Op RC:$src2, RC:$src1,
61 (ins RC:$src1, RC:$src2, RC:$src3),
63 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
68 (ins RC:$src1, RC:$src2, x86memop:$src3),
70 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
[all …]
H A DX86InstrSSE.td26 def rr : SI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
28 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
29 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
30 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], d>,
33 def rm : SI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
35 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
36 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
37 [(set RC:$dst, (OpNode RC:$src1, (load addr:$src2)))], d>,
49 def rr_Int : SI_Int<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
51 !strconcat(asm, "\t{$src2, $dst|$dst, $src2}"),
[all …]
H A DX86InstrConditionalCompare.td14 : ITy<o, f, t, (outs), (ins op1:$src1, op2:$src2, cflags:$dcf, ccode:$cond),
15 … m#"${cond}", "$dcf\t{$src2, $src1|$src1, $src2}" , []>, T_MAP4, EVEX, Requires<[In64BitMode]> {
81 def : Pat<(X86ccmp GR8:$src1, GR8:$src2, timm:$dcf, timm:$cond, EFLAGS),
82 (CCMP8rr GR8:$src1, GR8:$src2, timm:$dcf, timm:$cond)>;
83 def : Pat<(X86ccmp GR16:$src1, GR16:$src2, timm:$dcf, timm:$cond, EFLAGS),
84 (CCMP16rr GR16:$src1, GR16:$src2, timm:$dcf, timm:$cond)>;
85 def : Pat<(X86ccmp GR32:$src1, GR32:$src2, timm:$dcf, timm:$cond, EFLAGS),
86 (CCMP32rr GR32:$src1, GR32:$src2, timm:$dcf, timm:$cond)>;
87 def : Pat<(X86ccmp GR64:$src1, GR64:$src2, timm:$dcf, timm:$cond, EFLAGS),
88 (CCMP64rr GR64:$src1, GR64:$src2, timm:$dcf, timm:$cond)>;
[all …]
H A DX86InstrKL.td23 (ins VR128:$src1, opaquemem:$src2),
24 "aesenc128kl\t{$src2, $src1|$src1, $src2}",
25 [(set VR128:$dst, EFLAGS, (X86aesenc128kl VR128:$src1, addr:$src2))]>,
28 (ins VR128:$src1, opaquemem:$src2),
29 "aesdec128kl\t{$src2, $src1|$src1, $src2}",
30 [(set VR128:$dst, EFLAGS, (X86aesdec128kl VR128:$src1, addr:$src2))]>,
33 (ins VR128:$src1, opaquemem:$src2),
34 "aesenc256kl\t{$src2, $src1|$src1, $src2}",
35 [(set VR128:$dst, EFLAGS, (X86aesenc256kl VR128:$src1, addr:$src2))]>,
38 (ins VR128:$src1, opaquemem:$src2),
[all …]
H A DX86InstrAsmAlias.td70 def : InstAlias<"ccmp"#Cond#"{b} $dcf\t{$src2, $src1|$src1, $src2}",
71 (CCMP8rr GR8:$src1, GR8:$src2, cflags:$dcf, CC), 0>;
72 def : InstAlias<"ccmp"#Cond#"{w} $dcf\t{$src2, $src1|$src1, $src2}",
73 (CCMP16rr GR16:$src1, GR16:$src2, cflags:$dcf, CC), 0>;
74 def : InstAlias<"ccmp"#Cond#"{l} $dcf\t{$src2, $src1|$src1, $src2}",
75 (CCMP32rr GR32:$src1, GR32:$src2, cflags:$dcf, CC), 0>;
76 def : InstAlias<"ccmp"#Cond#"{q} $dcf\t{$src2, $src1|$src1, $src2}",
77 (CCMP64rr GR64:$src1, GR64:$src2, cflags:$dcf, CC), 0>;
78 def : InstAlias<"ccmp"#Cond#"{b} $dcf\t{$src2, $src1|$src1, $src2}",
79 (CCMP8rm GR8:$src1, i8mem:$src2, cflags:$dcf, CC), 0>;
[all …]
H A DX86InstrCMovSetCC.td19 (ins t.RegClass:$src1, t.RegClass:$src2, ccode:$cond),
22 … t.RegClass:$src2, timm:$cond, EFLAGS))]>, UseEFLAGS, NDD<ndd>;
25 (ins t.RegClass:$src1, t.MemOperand:$src2, ccode:$cond),
28 … (t.LoadNode addr:$src2), timm:$cond, EFLAGS))]>, UseEFLAGS, NDD<ndd>;
46 (ins t.RegClass:$src1, t.RegClass:$src2, ccode:$cond),
56 (ins t.RegClass:$src1, t.MemOperand:$src2, ccode:$cond),
93 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, timm:$cond, EFLAGS),
94 (CMOV16rm GR16:$src2, addr:$src1, (inv_cond_XFORM timm:$cond))>;
95 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, timm:$cond, EFLAGS),
96 (CMOV32rm GR32:$src2, addr:$src1, (inv_cond_XFORM timm:$cond))>;
[all …]
H A DX86InstrVMX.td19 def INVEPT32 : I<0x80, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
20 "invept\t{$src2, $src1|$src1, $src2}", []>, T8, PD,
22 def INVEPT64 : I<0x80, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
23 "invept\t{$src2, $src1|$src1, $src2}", []>, T8, PD,
25 def INVEPT64_EVEX : I<0xF0, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
26 "invept\t{$src2, $src1|$src1, $src2}", []>,
30 def INVVPID32 : I<0x81, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
31 "invvpid\t{$src2, $src1|$src1, $src2}", []>, T8, PD,
33 def INVVPID64 : I<0x81, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
34 "invvpid\t{$src2, $src1|$src1, $src2}", []>, T8, PD,
[all …]
H A DX86InstrMMX.td38 (ins VR64:$src1, VR64:$src2),
39 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
40 [(set VR64:$dst, (IntId VR64:$src1, VR64:$src2))]>,
45 (ins VR64:$src1, OType:$src2),
46 !strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
47 [(set VR64:$dst, (IntId VR64:$src1, (load_mmx addr:$src2)))]>,
56 (ins VR64:$src1, VR64:$src2),
57 !strconcat(OpcodeStr, "\t{$src2,
[all...]
H A DX86InstrAVX512.td372 (ins To.RC:$src1, From.RC:$src2, u8imm:$src3),
374 "$src3, $src2, $src1", "$src1, $src2, $src3",
376 (From.VT From.RC:$src2),
379 (From.VT From.RC:$src2),
384 (ins To.RC:$src1, From.MemOp:$src2, u8imm:$src3),
386 "$src3, $src2, $src1", "$src1, $src2, $src3",
388 (From.VT (From.LdFrag addr:$src2)),
391 (From.VT (From.LdFrag addr:$src2)),
410 (To.VT To.RC:$src1), (From.VT From.RC:$src2), (iPTR imm)),
412 To.RC:$src1, From.RC:$src2,
[all …]
H A DX86InstrCompiler.td706 MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
708 "{$src2, $dst|$dst, $src2}"),
709 [(set EFLAGS, (Op addr:$dst, GR8:$src2))]>, LOCK;
713 MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
715 "{$src2, $dst|$dst, $src2}"),
716 [(set EFLAGS, (Op addr:$dst, GR16:$src2))]>,
721 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
723 "{$src2, $dst|$dst, $src2}"),
724 [(set EFLAGS, (Op addr:$dst, GR32:$src2))]>,
729 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
[all …]
H A DX86InstrMisc.td617 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
618 "bt{w}\t{$src2, $src1|$src1, $src2}",
619 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>,
621 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
622 "bt{l}\t{$src2, $src1|$src1, $src2}",
623 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>,
625 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
626 "bt{q}\t{$src2, $src1|$src1, $src2}",
627 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))]>, TB;
637 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
[all …]
/freebsd/contrib/arm-optimized-routines/string/arm/
H A Dstrcmp.S62 #define src2 r1 macro
139 ldrb r3, [src2]
149 orr tmp1, src1, src2
158 eor tmp1, src1, src2
167 bic src2, src2, #7
171 ldrd data2a, data2b, [src2], #16
190 ldrd data2a, data2b, [src2], #16
202 ldrd data2a, data2b, [src2, #-8]
234 ldr data2, [src2], #8
241 ldr data2, [src2, #-4]
[all …]
/freebsd/contrib/arm-optimized-routines/string/aarch64/
H A Dmemcmp.S15 #define src2 x1 macro
36 ldp data2, data4, [src2]
42 add src2end, src2, limit
52 ldp data2, data4, [src2, 16]
60 ldp data2, data4, [src2, 32]
65 add src2, src2, 32
93 add src2end, src2, limit
96 ldr data2, [src2]
105 ldr data2w, [src2]
113 ldrh data2w, [src2]
[all …]
H A Dstrncmp.S21 #define src2 x1 macro
59 eor tmp1, src1, src2
72 ldr data2, [src2], #8
161 bic src2, src2, #7
164 ldr data2, [src2], #8
183 ldrb data2w, [src2], #1
202 ldrb data2w, [src2], #1
229 lsl offset, src2, #3
230 bic src2, src2, #0xf
234 ldp tmp1, tmp2, [src2], #16
[all …]
/freebsd/sys/arm64/arm64/
H A Dmemcmp.S20 #define src2 x1 macro
39 ldr data2, [src2], 8
47 ldr data2, [src2, limit]
52 ldr data2, [src2], 8
70 sub src2, src2, tmp1
78 ldp data2, data2h, [src2], 16
94 add src2, src2, limit
96 ldp data2, data2h, [src2]
121 ldr data2w, [src2], 4
130 ldrb data2w, [src2], 1
H A Dstrncmp.S25 #define src2 x1 macro
63 eor tmp1, src1, src2
76 ldr data2, [src2], #8
165 bic src2, src2, #7
168 ldr data2, [src2], #8
187 ldrb data2w, [src2], #1
206 ldrb data2w, [src2], #1
233 lsl offset, src2, #3
234 bic src2, src2, #0xf
238 ldp tmp1, tmp2, [src2], #16
[all …]
/freebsd/contrib/sendmail/libsm/
H A Db-strcmp.c56 char src1[SIZE], src2[SIZE]; local
88 (void) sm_strlcpy(src2, "1234567890", SIZE);
92 (void) sm_strlcpy(src2, "1234567891", SIZE);
96 (void) sm_strlcpy(src2, "1234567891", SIZE);
100 k, src1, src2);
108 j += strcasecmp(src1, src2);
119 j += sm_strcasecmp(src1, src2);
/freebsd/contrib/llvm-project/clang/lib/Headers/
H A Damxintrin.h255 _tile1024i dst, _tile1024i src1, _tile1024i src2) { in _tile_dpbssd_internal() argument
256 return __builtin_ia32_tdpbssd_internal(m, n, k, dst, src1, src2); in _tile_dpbssd_internal()
262 _tile1024i dst, _tile1024i src1, _tile1024i src2) { in _tile_dpbsud_internal() argument
263 return __builtin_ia32_tdpbsud_internal(m, n, k, dst, src1, src2); in _tile_dpbsud_internal()
269 _tile1024i dst, _tile1024i src1, _tile1024i src2) { in _tile_dpbusd_internal() argument
270 return __builtin_ia32_tdpbusd_internal(m, n, k, dst, src1, src2); in _tile_dpbusd_internal()
276 _tile1024i dst, _tile1024i src1, _tile1024i src2) { in _tile_dpbuud_internal() argument
277 return __builtin_ia32_tdpbuud_internal(m, n, k, dst, src1, src2); in _tile_dpbuud_internal()
291 _tile1024i dst, _tile1024i src1, _tile1024i src2) { in _tile_dpbf16ps_internal() argument
292 return __builtin_ia32_tdpbf16ps_internal(m, n, k, dst, src1, src2); in _tile_dpbf16ps_internal()
[all …]

1234567