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/freebsd/sys/contrib/device-tree/Bindings/powerpc/fsl/
H A Dcache_sram.txt10 - compatible : should be "fsl,p2020-cache-sram"
11 - fsl,cache-sram-ctlr-handle : points to the L2 controller
12 - reg : offset and length of the cache-sram.
16 cache-sram@fff00000 {
17 fsl,cache-sram-ctlr-handle = <&L2>;
19 compatible = "fsl,p2020-cache-sram";
/freebsd/sys/contrib/device-tree/src/arm/nxp/lpc/
H A Dlpc4350.dtsi24 sram0: sram@10000000 {
25 compatible = "mmio-sram";
29 sram1: sram@10080000 {
30 compatible = "mmio-sram";
34 sram2: sram@20000000 {
35 compatible = "mmio-sram";
H A Dlpc4357.dtsi24 sram0: sram@10000000 {
25 compatible = "mmio-sram";
29 sram1: sram@10080000 {
30 compatible = "mmio-sram";
34 sram2: sram@20000000 {
35 compatible = "mmio-sram";
/freebsd/sys/contrib/dev/ath/ath_hal/ar9300/
H A Dar9300_aic.c45 struct ath_aic_sram_info sram; member
426 aic_sram[i].sram.vga_dir_sign = (aic_sram[i].dir_path_gain_lin >= 0) in ar9300_aic_cal_post_process()
428 aic_sram[i].sram.vga_quad_sign= (aic_sram[i].quad_path_gain_lin >= 0) in ar9300_aic_cal_post_process()
438 aic_sram[i].sram.com_att_6db = ar9300_aic_find_index(1, in ar9300_aic_cal_post_process()
441 aic_sram[i].sram.valid = 1; in ar9300_aic_cal_post_process()
442 aic_sram[i].sram.rot_dir_att_db = in ar9300_aic_cal_post_process()
445 aic_sram[i].sram.rot_quad_att_db = in ar9300_aic_cal_post_process()
453 ahp->ah_aic_sram[i] = (SM(aic_sram[i].sram.vga_dir_sign, in ar9300_aic_cal_post_process()
455 SM(aic_sram[i].sram.vga_quad_sign, in ar9300_aic_cal_post_process()
457 SM(aic_sram[i].sram.com_att_6db, in ar9300_aic_cal_post_process()
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/arm/
H A Djuno-scmi.dtsi200 &sram {
201 /delete-node/ scp-sram@0;
202 /delete-node/ scp-sram@200;
204 cpu_scp_lpri0: scp-sram@0 {
209 cpu_scp_lpri1: scp-sram@80 {
214 cpu_scp_hpri0: scp-sram@100 {
219 cpu_scp_hpri1: scp-sram@180 {
/freebsd/sys/contrib/device-tree/Bindings/arm/omap/
H A Dmpu.txt14 - sram: Phandle to the ocmcram node
17 - pm-sram: Phandles to ocmcram nodes to be used for power management.
20 data region for code. See Documentation/devicetree/bindings/sram/sram.yaml
52 pm-sram = <&pm_sram_code
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dhi6220-clock.txt28 - hisilicon,hi6220-clk-sram: phandle to the syscon managing the SoC internal sram;
29 the driver need use the sram to pass parameters for frequency change.
44 hisilicon,hi6220-clk-sram = <&sram>;
/freebsd/sys/contrib/device-tree/src/arm/microchip/
H A Dat91sam9xe.dtsi15 sram0: sram@2ff000 {
19 sram1: sram@300000 {
20 compatible = "mmio-sram";
H A Dat91sam9g20.dtsi18 sram0: sram@2ff000 {
22 sram1: sram@2fc000 {
23 compatible = "mmio-sram";
/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dallegro.txt14 length of the memory mapped sram
15 - reg-names: must include "regs" and "sram"
26 reg-names = "regs", "sram";
37 reg-names = "regs", "sram";
/freebsd/sys/contrib/device-tree/src/arm/allwinner/
H A Dsun5i.dtsi140 sram_a: sram@0 {
141 compatible = "mmio-sram";
147 emac_sram: sram-section@8000 {
148 compatible = "allwinner,sun5i-a13-sram-a3-a4",
149 "allwinner,sun4i-a10-sram-a3-a4";
155 sram_d: sram@10000 {
156 compatible = "mmio-sram";
162 otg_sram: sram-section@0 {
163 compatible = "allwinner,sun5i-a13-sram-d",
164 "allwinner,sun4i-a10-sram-d";
[all …]
H A Dsuniv-f1c100s.dtsi48 sram-controller@1c00000 {
56 sram_d: sram@10000 {
57 compatible = "mmio-sram";
63 otg_sram: sram-section@0 {
64 compatible = "allwinner,suniv-f1c100s-sram-d",
65 "allwinner,sun4i-a10-sram-d";
146 allwinner,sram = <&otg_sram 1>;
/freebsd/sys/contrib/device-tree/src/arm/socionext/
H A Dmilbeaut-m10v.dtsi93 sram@0 {
94 compatible = "mmio-sram";
99 smp-sram@f100 {
100 compatible = "socionext,milbeaut-smp-sram";
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6qp.dtsi9 ocram2: sram@940000 {
10 compatible = "mmio-sram";
18 ocram3: sram@960000 {
19 compatible = "mmio-sram";
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ti/
H A Demif.txt32 - sram : Phandles for generic sram driver nodes,
35 data region for code. See Documentation/devicetree/bindings/sram/sram.yaml
76 sram = <&pm_sram_code
/freebsd/sys/contrib/device-tree/Bindings/mailbox/
H A Dmailbox.txt41 sram: sram@50000000 {
42 compatible = "mmio-sram";
/freebsd/sys/contrib/device-tree/Bindings/fsi/
H A Dfsi-master-ast-cf.txt19 - aspeed,sram = <phandle>; : Reference to the SRAM node.
34 aspeed,sram = <&sram>;
/freebsd/sys/contrib/device-tree/Bindings/crypto/
H A Dmv_cesa.txt12 - reg-names: "regs". Can contain an "sram" entry, but this representation
20 - marvell,crypto-sram-size: SRAM size reserved for crypto operations, if not
31 marvell,crypto-sram-size = <0x600>;
H A Dmarvell-cesa.txt16 - reg-names: "regs". Can contain an "sram" entry, but this representation
29 - marvell,crypto-sram-size: SRAM size reserved for crypto operations, if not
43 marvell,crypto-sram-size = <0x600>;
/freebsd/sys/contrib/device-tree/src/arm64/allwinner/
H A Dsun50i-h5.dtsi89 sram_c1: sram@18000 {
90 compatible = "mmio-sram";
96 ve_sram: sram-section@0 {
97 compatible = "allwinner,sun50i-h5-sram-c1",
98 "allwinner,sun4i-a10-sram-c1";
112 allwinner,sram = <&ve_sram 1>;
/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dstm32mp15-scmi.dtsi
/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dmarvell-orion-net.txt43 - marvell,tx-sram-addr: address of transmit descriptor buffer located in SRAM.
44 - marvell,tx-sram-size: size of transmit descriptor buffer located in SRAM.
46 - marvell,rx-sram-addr: address of receive descriptor buffer located in SRAM.
47 - marvell,rx-sram-size: size of receive descriptor buffer located in SRAM.
/freebsd/sys/contrib/device-tree/src/arm/nspire/
H A Dnspire.dtsi26 sram: sram@a4000000 { label
27 compatible = "mmio-sram";
33 sram@0 {
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dpcm030.dts76 sram@8000 {
77 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";
H A Dmotionpro.dts78 sram@8000 {
79 compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram";

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