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Searched refs:shamt (Results 1 – 18 of 18) sorted by relevance

/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/
H A DRISCVCInstructions.h230 uint16_t shamt = ((inst >> 7) & 0x20) | ((inst >> 2) & 0x1f); in DecodeC_SLLI() local
231 if (rd == 0 || shamt == 0) in DecodeC_SLLI()
233 return SLLI{rd, rd, uint8_t(shamt)}; in DecodeC_SLLI()
238 uint16_t shamt = ((inst >> 7) & 0x20) | ((inst >> 2) & 0x1f); in DecodeC_SRLI() local
239 if (shamt == 0) in DecodeC_SRLI()
241 return SRLI{rd, rd, uint8_t(shamt)}; in DecodeC_SRLI()
246 uint16_t shamt = ((inst >> 7) & 0x20) | ((inst >> 2) & 0x1f); in DecodeC_SRAI() local
247 if (shamt == 0) in DecodeC_SRAI()
249 return SRAI{rd, rd, uint8_t(shamt)}; in DecodeC_SRAI()
H A DEmulateInstructionRISCV.cpp880 return inst.rd.Write(m_emu, rs1 << inst.shamt); in operator ()()
887 return inst.rd.Write(m_emu, rs1 >> inst.shamt); in operator ()()
894 return inst.rd.Write(m_emu, rs1 >> inst.shamt); in operator ()()
910 SextW(rs1 << inst.shamt)); in operator ()()
918 SextW(rs1 >> inst.shamt)); in operator ()()
926 SextW(rs1 >> inst.shamt)); in operator ()()
H A DRISCVInstructions.h76 uint32_t shamt; \
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoZb.td261 (ins GPR:$rs1, uimmlog2xlen:$shamt), opcodestr,
262 "$rd, $rs1, $shamt">;
268 (ins GPR:$rs1, uimm5:$shamt), opcodestr,
269 "$rd, $rs1, $shamt">;
464 def : InstAlias<"ror $rd, $rs1, $shamt",
465 (RORI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>;
469 def : InstAlias<"rorw $rd, $rs1, $shamt",
470 (RORIW GPR:$rd, GPR:$rs1, uimm5:$shamt), 0>;
474 def : InstAlias<"bset $rd, $rs1, $shamt",
475 (BSETI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>;
[all …]
H A DRISCVInstrInfo.td198 // TODO: should ensure invalid shamt is rejected when decoding.
554 (ins GPR:$rs1, uimmlog2xlen:$shamt), opcodestr,
555 "$rd, $rs1, $shamt">,
582 (ins GPR:$rs1, uimm5:$shamt), opcodestr,
583 "$rd, $rs1, $shamt">,
1029 def : InstAlias<"sll $rd, $rs1, $shamt",
1030 (SLLI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt)>;
1031 def : InstAlias<"srl $rd, $rs1, $shamt",
1032 (SRLI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt)>;
1033 def : InstAlias<"sra $rd, $rs1, $shamt",
[all …]
H A DRISCVInstrInfoXTHead.td94 (ins GPR:$rs1, uimmlog2xlen:$shamt),
95 opcodestr, "$rd, $rs1, $shamt">;
116 (ins GPR:$rs1, uimm5:$shamt),
117 opcodestr, "$rd, $rs1, $shamt">;
566 def : Pat<(rotl (XLenVT GPR:$rs1), uimmlog2xlen:$shamt),
567 (TH_SRRI GPR:$rs1, (ImmSubFromXLen uimmlog2xlen:$shamt))>;
590 def : Pat<(and (srl (XLenVT GPR:$rs1), uimmlog2xlen:$shamt), 1),
591 (TH_TST GPR:$rs1, uimmlog2xlen:$shamt)>;
H A DRISCVInstrFormats.td393 bits<6> shamt;
397 let Inst{25-20} = shamt;
403 bits<5> shamt;
406 let Inst{24-20} = shamt;
H A DRISCVInstrInfoC.td27 // TODO: should ensure invalid shamt is rejected when decoding.
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrShiftRotate.td511 (ins GR32:$src1, u8imm:$shamt), "",
512 [(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$shamt)))]>;
514 (ins GR64:$src1, u8imm:$shamt), "",
515 [(set GR64:$dst, (rotl GR64:$src1, (i8 imm:$shamt)))]>;
518 (ins GR32:$src1, u8imm:$shamt), "",
519 [(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$shamt)))]>;
521 (ins GR64:$src1, u8imm:$shamt), "",
522 [(set GR64:$dst, (rotr GR64:$src1, (i8 imm:$shamt)))]>;
530 // Convert a ROTL shamt to a ROTR shamt o
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstrFormats.td18 // shamt - only used on shift instructions, contains the shift amount.
148 // Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
158 bits<5> shamt;
167 let Inst{10-6} = shamt;
247 bits<5> shamt;
256 let Inst{10-6} = shamt;
H A DMicroMipsInstrFormats.td98 bits<3> shamt;
105 let Inst{3-1} = shamt;
365 bits<5> shamt;
372 let Inst{15-11} = shamt;
H A DMicroMipsInstrInfo.td336 MicroMipsInst16<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
337 !strconcat(opstr, "\t$rd, $rt, $shamt"), [], Itin, FrmR>;
793 (rotr GPR32Opnd:$rt, immZExt5:$shamt))];
1380 def : MipsInstAlias<"sll $rd, $shamt",
1381 (SLL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
1382 def : MipsInstAlias<"sra $rd, $shamt",
1383 (SRA_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
1384 def : MipsInstAlias<"srl $rd, $shamt",
1385 (SRL_MM GPR32Opnd:$rd, GPR32Opnd:$rd, uimm5:$shamt), 0>;
H A DMicroMips32r6InstrFormats.td530 bits<5> shamt;
537 let Inst{15-11} = shamt;
H A DMipsDSPInstrInfo.td1370 DSPPat<(Node ValTy:$a, Imm:$shamt), (Inst ValTy:$a, Imm:$shamt), Pred>;
H A DMips64InstrInfo.td17 // shamt must fit in 6 bits.
414 let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
H A DMipsInstrInfo.td1252 // shamt field must fit in 5 bits.
1364 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
1365 !strconcat(opstr, "\t$rd, $rt, $shamt"),
1366 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
H A DMips16InstrInfo.td498 bits<5> shamt = 0;
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsRISCV.td67 // ptr addr, ixlen oparg, ixlen mask, ixlen shamt, ixlenimm ordering)