| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 174 setTargetDAGCombine(ISD::SETCC); in WebAssemblyTargetLowering()
177 setTargetDAGCombine(ISD::BITCAST); in WebAssemblyTargetLowering()
180 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); in WebAssemblyTargetLowering()
183 setTargetDAGCombine({ISD::SIGN_EXTEND, ISD::ZERO_EXTEND}); in WebAssemblyTargetLowering()
187 setTargetDAGCombine({ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_EXTEND, in WebAssemblyTargetLowering()
192 setTargetDAGCombine({ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT, in WebAssemblyTargetLowering()
195 setTargetDAGCombine(ISD::TRUNCATE); in WebAssemblyTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 914 setTargetDAGCombine(ISD::TRUNCATE); in VETargetLowering()
915 setTargetDAGCombine(ISD::SELECT); in VETargetLowering()
916 setTargetDAGCombine(ISD::SELECT_CC); in VETargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 336 setTargetDAGCombine(ISD::AND); in LoongArchTargetLowering()
337 setTargetDAGCombine(ISD::OR); in LoongArchTargetLowering()
338 setTargetDAGCombine(ISD::SRL); in LoongArchTargetLowering()
339 setTargetDAGCombine(ISD::SETCC); in LoongArchTargetLowering()
344 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN); in LoongArchTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1079 setTargetDAGCombine(ISD::OR); in AArch64TargetLowering()
1081 setTargetDAGCombine(ISD::AND); in AArch64TargetLowering()
1089 setTargetDAGCombine({ISD::ADD, ISD::ABS, ISD::SUB, ISD::XOR, ISD::SINT_TO_FP, in AArch64TargetLowering()
1092 setTargetDAGCombine({ISD::FP_TO_SINT, ISD::FP_TO_UINT, ISD::FP_TO_SINT_SAT, in AArch64TargetLowering()
1096 setTargetDAGCombine(ISD::SETCC); in AArch64TargetLowering()
1098 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN); in AArch64TargetLowering()
1100 setTargetDAGCombine({ISD::ANY_EXTEND, ISD::ZERO_EXTEND, ISD::SIGN_EXTEND, in AArch64TargetLowering()
1104 setTargetDAGCombine(ISD::TRUNCATE); in AArch64TargetLowering()
1105 setTargetDAGCombine(ISD::LOAD); in AArch64TargetLowering()
1107 setTargetDAGCombine(ISD::MSTORE); in AArch64TargetLowering()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1844 setTargetDAGCombine(ISD::OR); in HexagonTargetLowering()
1845 setTargetDAGCombine(ISD::TRUNCATE); in HexagonTargetLowering()
1846 setTargetDAGCombine(ISD::VSELECT); in HexagonTargetLowering()
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| H A D | HexagonISelLoweringHVX.cpp | 439 setTargetDAGCombine({ISD::CONCAT_VECTORS, ISD::TRUNCATE, ISD::VSELECT}); in initializeHVXLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 101 setTargetDAGCombine( in MipsSETargetLowering()
160 setTargetDAGCombine({ISD::AND, ISD::OR, ISD::SRA, ISD::VSELECT, ISD::XOR}); in MipsSETargetLowering()
208 setTargetDAGCombine(ISD::MUL); in MipsSETargetLowering()
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| H A D | MipsISelLowering.cpp | 517 setTargetDAGCombine({ISD::SDIVREM, ISD::UDIVREM, ISD::SELECT, ISD::AND, in MipsTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 141 setTargetDAGCombine({ISD::ADD, ISD::SUB, ISD::AND, ISD::OR, ISD::XOR}); in LanaiTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 1470 setTargetDAGCombine({ISD::INTRINSIC_VOID, ISD::INTRINSIC_W_CHAIN, in RISCVTargetLowering()
1474 setTargetDAGCombine(ISD::SRA); in RISCVTargetLowering()
1477 setTargetDAGCombine({ISD::FADD, ISD::FMAXNUM, ISD::FMINNUM}); in RISCVTargetLowering()
1480 setTargetDAGCombine({ISD::UMAX, ISD::UMIN, ISD::SMAX, ISD::SMIN}); in RISCVTargetLowering()
1484 setTargetDAGCombine(ISD::TRUNCATE); in RISCVTargetLowering()
1487 setTargetDAGCombine(ISD::BITREVERSE); in RISCVTargetLowering()
1489 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG); in RISCVTargetLowering()
1491 setTargetDAGCombine({ISD::ZERO_EXTEND, ISD::FP_TO_SINT, ISD::FP_TO_UINT, in RISCVTargetLowering()
1494 setTargetDAGCombine({ISD::FCOPYSIGN, ISD::MGATHER, ISD::MSCATTER, in RISCVTargetLowering()
1502 setTargetDAGCombine({IS in RISCVTargetLowering()
[all...] |
| /freebsd/contrib/llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 164 setTargetDAGCombine( in XCoreTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 1390 setTargetDAGCombine({ISD::AND, ISD::ADD, ISD::SHL, ISD::SRA, ISD::SRL, in PPCTargetLowering()
1393 setTargetDAGCombine(ISD::UINT_TO_FP); in PPCTargetLowering()
1394 setTargetDAGCombine({ISD::LOAD, ISD::STORE, ISD::BR_CC}); in PPCTargetLowering()
1396 setTargetDAGCombine(ISD::BRCOND); in PPCTargetLowering()
1397 setTargetDAGCombine({ISD::BSWAP, ISD::INTRINSIC_WO_CHAIN, in PPCTargetLowering()
1400 setTargetDAGCombine({ISD::SIGN_EXTEND, ISD::ZERO_EXTEND, ISD::ANY_EXTEND}); in PPCTargetLowering()
1402 setTargetDAGCombine({ISD::TRUNCATE, ISD::VECTOR_SHUFFLE}); in PPCTargetLowering()
1405 setTargetDAGCombine({ISD::TRUNCATE, ISD::SETCC, ISD::SELECT_CC}); in PPCTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 831 setTargetDAGCombine({ISD::BRCOND, ISD::BR_CC}); in ARMTargetLowering()
1009 setTargetDAGCombine({ISD::SHL, ISD::SRL, ISD::SRA, ISD::FP_TO_SINT, in ARMTargetLowering()
1032 setTargetDAGCombine( in ARMTargetLowering()
1040 setTargetDAGCombine({ISD::SMIN, ISD::UMIN, ISD::SMAX, ISD::UMAX, in ARMTargetLowering()
1045 setTargetDAGCombine(ISD::FADD); in ARMTargetLowering()
1599 setTargetDAGCombine( in ARMTargetLowering()
1603 setTargetDAGCombine(ISD::VSELECT); in ARMTargetLowering()
1606 setTargetDAGCombine(ISD::SRL); in ARMTargetLowering()
1608 setTargetDAGCombine(ISD::SHL); in ARMTargetLowering()
1612 setTargetDAGCombine({ISD::SMIN, ISD::SMAX}); in ARMTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.cpp | 201 setTargetDAGCombine({ISD::FP_ROUND, ISD::FP_TO_SINT, ISD::EXTRACT_VECTOR_ELT, in R600TargetLowering()
|
| H A D | SIISelLowering.cpp | 892 setTargetDAGCombine({ISD::ADD, in SITargetLowering()
926 setTargetDAGCombine(ISD::FP_ROUND); in SITargetLowering()
930 setTargetDAGCombine({ISD::LOAD, in SITargetLowering()
|
| H A D | AMDGPUISelLowering.cpp | 613 setTargetDAGCombine({ISD::BITCAST, ISD::SHL, in AMDGPUTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 2705 void setTargetDAGCombine(ArrayRef<ISD::NodeType> NTs) { in setTargetDAGCombine() function
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 731 setTargetDAGCombine({ISD::ADD, ISD::AND, ISD::EXTRACT_VECTOR_ELT, ISD::FADD, in NVPTXTargetLowering()
738 setTargetDAGCombine(ISD::SETCC); in NVPTXTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1985 setTargetDAGCombine(ISD::BITCAST); in SparcTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 716 setTargetDAGCombine({ISD::ZERO_EXTEND, in SystemZTargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 2507 setTargetDAGCombine({ISD::VECTOR_SHUFFLE, in X86TargetLowering()
|