| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 186 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN); in WebAssemblyTargetLowering()
189 setTargetDAGCombine(ISD::MUL); in WebAssemblyTargetLowering()
192 setTargetDAGCombine(ISD::SETCC); in WebAssemblyTargetLowering()
195 setTargetDAGCombine(ISD::BITCAST); in WebAssemblyTargetLowering()
198 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); in WebAssemblyTargetLowering()
201 setTargetDAGCombine({ISD::SIGN_EXTEND, ISD::ZERO_EXTEND}); in WebAssemblyTargetLowering()
205 setTargetDAGCombine({ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_EXTEND, in WebAssemblyTargetLowering()
210 setTargetDAGCombine({ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT, in WebAssemblyTargetLowering()
213 setTargetDAGCombine(ISD::TRUNCATE); in WebAssemblyTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 904 setTargetDAGCombine(ISD::TRUNCATE); in VETargetLowering()
905 setTargetDAGCombine(ISD::SELECT); in VETargetLowering()
906 setTargetDAGCombine(ISD::SELECT_CC); in VETargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 140 setTargetDAGCombine( in MipsSETargetLowering()
199 setTargetDAGCombine({ISD::AND, ISD::OR, ISD::SRA, ISD::VSELECT, ISD::XOR}); in MipsSETargetLowering()
247 setTargetDAGCombine(ISD::MUL); in MipsSETargetLowering()
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| H A D | MipsISelLowering.cpp | 525 setTargetDAGCombine({ISD::SDIVREM, ISD::UDIVREM, ISD::SELECT, ISD::AND, in MipsTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1918 setTargetDAGCombine(ISD::OR); in HexagonTargetLowering()
1919 setTargetDAGCombine(ISD::TRUNCATE); in HexagonTargetLowering()
1920 setTargetDAGCombine(ISD::VSELECT); in HexagonTargetLowering()
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| H A D | HexagonISelLoweringHVX.cpp | 449 setTargetDAGCombine({ISD::CONCAT_VECTORS, ISD::TRUNCATE, ISD::VSELECT}); in initializeHVXLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 1121 setTargetDAGCombine(ISD::OR); in AArch64TargetLowering()
1123 setTargetDAGCombine(ISD::AND); in AArch64TargetLowering()
1131 setTargetDAGCombine({ISD::ADD, ISD::ABS, ISD::SUB, ISD::XOR, ISD::SINT_TO_FP, in AArch64TargetLowering()
1134 setTargetDAGCombine({ISD::FP_TO_SINT, ISD::FP_TO_UINT, ISD::FP_TO_SINT_SAT, in AArch64TargetLowering()
1138 setTargetDAGCombine(ISD::SETCC); in AArch64TargetLowering()
1140 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN); in AArch64TargetLowering()
1142 setTargetDAGCombine({ISD::ANY_EXTEND, ISD::ZERO_EXTEND, ISD::SIGN_EXTEND, in AArch64TargetLowering()
1146 setTargetDAGCombine(ISD::TRUNCATE); in AArch64TargetLowering()
1147 setTargetDAGCombine(ISD::LOAD); in AArch64TargetLowering()
1149 setTargetDAGCombine(ISD::MSTORE); in AArch64TargetLowering()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 403 setTargetDAGCombine(ISD::AND); in LoongArchTargetLowering()
404 setTargetDAGCombine(ISD::OR); in LoongArchTargetLowering()
405 setTargetDAGCombine(ISD::SRL); in LoongArchTargetLowering()
406 setTargetDAGCombine(ISD::SETCC); in LoongArchTargetLowering()
411 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN); in LoongArchTargetLowering()
412 setTargetDAGCombine(ISD::BITCAST); in LoongArchTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 139 setTargetDAGCombine({ISD::ADD, ISD::SUB, ISD::AND, ISD::OR, ISD::XOR}); in LanaiTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 136 setTargetDAGCombine( in XCoreTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 821 setTargetDAGCombine({ISD::BRCOND, ISD::BR_CC}); in ARMTargetLowering()
1007 setTargetDAGCombine({ISD::SHL, ISD::SRL, ISD::SRA, ISD::FP_TO_SINT, in ARMTargetLowering()
1030 setTargetDAGCombine( in ARMTargetLowering()
1038 setTargetDAGCombine({ISD::SMIN, ISD::UMIN, ISD::SMAX, ISD::UMAX, in ARMTargetLowering()
1043 setTargetDAGCombine(ISD::FADD); in ARMTargetLowering()
1592 setTargetDAGCombine( in ARMTargetLowering()
1596 setTargetDAGCombine(ISD::VSELECT); in ARMTargetLowering()
1599 setTargetDAGCombine(ISD::SRL); in ARMTargetLowering()
1601 setTargetDAGCombine(ISD::SHL); in ARMTargetLowering()
1605 setTargetDAGCombine({ISD::SMIN, ISD::SMAX}); in ARMTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600ISelLowering.cpp | 205 setTargetDAGCombine({ISD::FP_ROUND, ISD::FP_TO_SINT, ISD::EXTRACT_VECTOR_ELT, in R600TargetLowering()
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| H A D | SIISelLowering.cpp | 947 setTargetDAGCombine({ISD::ADD, in SITargetLowering()
994 setTargetDAGCombine(ISD::FP_ROUND); in SITargetLowering()
998 setTargetDAGCombine({ISD::LOAD, in SITargetLowering()
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| H A D | AMDGPUISelLowering.cpp | 626 setTargetDAGCombine({ISD::BITCAST, ISD::SHL, in AMDGPUTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 1625 setTargetDAGCombine({ISD::INTRINSIC_VOID, ISD::INTRINSIC_W_CHAIN, in RISCVTargetLowering()
1628 setTargetDAGCombine(ISD::SRA); in RISCVTargetLowering()
1629 setTargetDAGCombine(ISD::SIGN_EXTEND_INREG); in RISCVTargetLowering()
1632 setTargetDAGCombine({ISD::FADD, ISD::FMAXNUM, ISD::FMINNUM, ISD::FMUL}); in RISCVTargetLowering()
1635 setTargetDAGCombine({ISD::UMAX, ISD::UMIN, ISD::SMAX, ISD::SMIN}); in RISCVTargetLowering()
1639 setTargetDAGCombine(ISD::TRUNCATE); in RISCVTargetLowering()
1642 setTargetDAGCombine(ISD::BITREVERSE); in RISCVTargetLowering()
1645 setTargetDAGCombine({ISD::ZERO_EXTEND, ISD::FP_TO_SINT, ISD::FP_TO_UINT, in RISCVTargetLowering()
1648 setTargetDAGCombine( in RISCVTargetLowering()
1660 setTargetDAGCombine({ISD::LOAD, ISD::STORE}); in RISCVTargetLowering()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 1415 setTargetDAGCombine({ISD::AND, ISD::ADD, ISD::SHL, ISD::SRA, ISD::SRL, in PPCTargetLowering()
1418 setTargetDAGCombine(ISD::UINT_TO_FP); in PPCTargetLowering()
1419 setTargetDAGCombine({ISD::LOAD, ISD::STORE, ISD::BR_CC}); in PPCTargetLowering()
1421 setTargetDAGCombine(ISD::BRCOND); in PPCTargetLowering()
1422 setTargetDAGCombine({ISD::BSWAP, ISD::INTRINSIC_WO_CHAIN, in PPCTargetLowering()
1425 setTargetDAGCombine({ISD::SIGN_EXTEND, ISD::ZERO_EXTEND, ISD::ANY_EXTEND}); in PPCTargetLowering()
1427 setTargetDAGCombine({ISD::TRUNCATE, ISD::VECTOR_SHUFFLE}); in PPCTargetLowering()
1430 setTargetDAGCombine({ISD::TRUNCATE, ISD::SETCC, ISD::SELECT_CC}); in PPCTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 2798 void setTargetDAGCombine(ArrayRef<ISD::NodeType> NTs) { in setTargetDAGCombine() function
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 841 setTargetDAGCombine({ISD::ADD, ISD::AND, ISD::EXTRACT_VECTOR_ELT, ISD::FADD, in NVPTXTargetLowering()
849 setTargetDAGCombine(ISD::SETCC); in NVPTXTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 1958 setTargetDAGCombine(ISD::BITCAST); in SparcTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 782 setTargetDAGCombine({ISD::ZERO_EXTEND, in SystemZTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 2637 setTargetDAGCombine({ISD::VECTOR_SHUFFLE, in X86TargetLowering()
|