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Searched refs:setReg (Results 1 – 25 of 173) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineLoopUtils.cpp55 MO.setReg(R); in PeelSingleBlockLoop()
71 Use->setReg(R); in PeelSingleBlockLoop()
80 MO.setReg(Remaps[MO.getReg()]); in PeelSingleBlockLoop()
95 OrigPhi.getOperand(InitRegIdx).setReg(R); in PeelSingleBlockLoop()
102 MI.getOperand(LoopRegIdx).setReg(LoopReg); in PeelSingleBlockLoop()
H A DInitUndef.cpp191 UseMO.setReg(LatestReg); in handleSubReg()
209 MO.setReg(NewReg); in fixupIllOperand()
235 UseMO.setReg(NewDest); in processBasicBlock()
H A DTailDuplicator.cpp243 UseMO->setReg( in tailDuplicateAndUpdate()
414 MO.setReg(NewReg); in duplicateInstruction()
451 MO.setReg(VI->second.Reg); in duplicateInstruction()
466 MO.setReg(NewReg); in duplicateInstruction()
537 MI.getOperand(Idx).setReg(SrcReg); in updateSuccessorsPHIs()
548 MI.getOperand(Idx).setReg(Reg); in updateSuccessorsPHIs()
H A DModuloSchedule.cpp351 O.setReg(ToReg); in replaceRegUsesAfterLoop()
1043 MO.setReg(NewReg); in updateInstruction()
1059 MO.setReg(VRMap[StageNum][reg]); in updateInstruction()
1192 UseOp.setReg(ReplaceReg); in rewriteScheduledInstr()
1198 UseOp.setReg(SplitReg); in rewriteScheduledInstr()
1341 MO.setReg(Reg); in rewrite()
1495 MI->getOperand(1).setReg(*InitReg); in phi()
1686 MI.getOperand(0).setReg(PhiReg); in moveStageBetweenBlocks()
1700 NewMI->getOperand(0).setReg(R); in moveStageBetweenBlocks()
1701 NewMI->getOperand(1).setReg(OrigR); in moveStageBetweenBlocks()
[all …]
H A DBreakFalseDeps.cpp148 MO.setReg(CurrMO.getReg()); in pickBestRegisterForUndef()
170 MO.setReg(MaxClearanceReg); in pickBestRegisterForUndef()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCVSXFMAMutate.cpp246 MI.getOperand(0).setReg(KilledProdReg); in processBlock()
247 MI.getOperand(1).setReg(KilledProdReg); in processBlock()
248 MI.getOperand(3).setReg(AddendSrcReg); in processBlock()
265 MI.getOperand(2).setReg(AddendSrcReg); in processBlock()
270 MI.getOperand(2).setReg(OtherProdReg); in processBlock()
H A DPPCVSXCopy.cpp114 SrcMO.setReg(NewVReg); in processBlock()
133 SrcMO.setReg(NewVReg); in processBlock()
H A DPPCMIPeephole.cpp526 MO.setReg(PPC::NoRegister); in simplifyCode()
725 MI.getOperand(1).setReg(DefReg1); in simplifyCode()
726 MI.getOperand(2).setReg(DefReg2); in simplifyCode()
765 DefMI->getOperand(0).setReg(MI.getOperand(0).getReg()); in simplifyCode()
865 MI.getOperand(OpNo).setReg(ShiftOp1); in simplifyCode()
908 Use.getOperand(i).setReg(ConvReg1); in simplifyCode()
977 SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg()); in simplifyCode()
1049 SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg()); in simplifyCode()
1272 MI.getOperand(1).setReg(SrcMI->getOperand(1).getReg()); in simplifyCode()
1833 CMPI2->getOperand(1).setReg(Op2); in eliminateRedundantCompare()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonTfrCleanup.cpp73 void setReg(unsigned R32, uint32_t V32, ImmediateMap &IMap);
94 void HexagonTfrCleanup::setReg(unsigned R32, uint32_t V32, ImmediateMap &IMap) { in setReg() function in HexagonTfrCleanup
160 setReg(TRI->getSubReg(DefR, isub_lo), VL, IMap); in updateImmMap()
161 setReg(TRI->getSubReg(DefR, isub_hi), VH, IMap); in updateImmMap()
163 setReg(DefR, Val, IMap); in updateImmMap()
H A DHexagonAsmPrinter.cpp384 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
395 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
407 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
419 Rs.setReg(getHexagonRegisterPair(Rs.getReg(), RI)); in HexagonProcessInstruction()
545 MO.setReg(High); in HexagonProcessInstruction()
557 MO.setReg(High); in HexagonProcessInstruction()
571 MO.setReg(High); in HexagonProcessInstruction()
604 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyDebugValueManager.cpp372 Clone->getOperand(0).setReg(NewReg); in cloneSink()
390 MO.setReg(NewReg); in cloneSink()
398 MO.setReg(Reg); in updateReg()
400 Def->getOperand(0).setReg(Reg); in updateReg()
H A DWebAssemblyPeephole.cpp68 MO.setReg(NewReg); in maybeRewriteToDrop()
103 MO.setReg(NewReg); in maybeRewriteToFallthrough()
H A DWebAssemblyFixBrTableDefaults.cpp67 MI.getOperand(0).setReg(ExtMI->getOperand(1).getReg()); in fixBrTableIndex()
79 MI.getOperand(0).setReg(Reg32); in fixBrTableIndex()
H A DWebAssemblyExplicitLocals.cpp320 MI.getOperand(2).setReg(NewReg); in runOnMachineFunction()
369 Def.setReg(NewReg); in runOnMachineFunction()
427 MO.setReg(NewReg); in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DAntiDepBreaker.h63 MI.getDebugOperand(0).setReg(NewReg); in UpdateDbgValue()
67 MI.getOperand(0).setReg(NewReg); in UpdateDbgValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZCopyPhysRegs.cpp87 MI->getOperand(1).setReg(Tmp); in visitMBB()
93 MI->getOperand(0).setReg(Tmp); in visitMBB()
H A DSystemZPostRewrite.cpp118 MBBI->getOperand(1).setReg(DestReg); in selectSELRMux()
125 MBBI->getOperand(2).setReg(DestReg); in selectSELRMux()
223 SrcMO.setReg(DstReg); in selectMI()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMVETPAndVPTOptimisationsPass.cpp400 LoopPhi->getOperand(3).setReg(StartReg); in MergeLoopEnd()
401 LoopPhi->getOperand(1).setReg(DecReg); in MergeLoopEnd()
403 LoopPhi->getOperand(1).setReg(StartReg); in MergeLoopEnd()
404 LoopPhi->getOperand(3).setReg(DecReg); in MergeLoopEnd()
539 MI->getOperand(Idx + 2).setReg(LR); in ConvertTailPredLoop()
641 User.setReg(NewResult); in ReplaceRegisterUseWithVPNOT()
809 MO->setReg(LastVPNOTResult); in ReduceOldVCCRValueUses()
965 Instr.getOperand(PIdx + 1).setReg(LastVPTReg); in ReplaceConstByVPNOTs()
983 Instr.getOperand(PIdx + 1).setReg(NewVPR); in ReplaceConstByVPNOTs()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DDelaySlotFiller.cpp398 AddMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreADD()
437 OrMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreOR()
471 RestoreMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreSETHIi()
472 RestoreMI->getOperand(1).setReg(SP::G0); in combineRestoreSETHIi()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp1465 MO.setReg(RegPair.first); in processInstruction()
1475 MO.setReg(RegPair.first); in processInstruction()
1486 MO.setReg(RegPair.first); in processInstruction()
1498 MO.setReg(RegPair.first); in processInstruction()
1812 Rss.setReg(matchRegister(Reg1)); in processInstruction()
1838 Rs.setReg(matchRegister(RegPair)); in processInstruction()
1843 Rs.setReg(matchRegister(RegPair)); in processInstruction()
1855 Rs.setReg(matchRegister(RegPair)); in processInstruction()
1860 Rs.setReg(matchRegister(RegPair)); in processInstruction()
1872 Rt.setReg(matchRegister(RegPair)); in processInstruction()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrBuilder.h137 MI->getOperand(Operand + 2).setReg(0); in setDirectAddressInInstr()
139 MI->getOperand(Operand + 4).setReg(0); in setDirectAddressInInstr()
H A DX86FastPreTileConfig.cpp251 MO.setReg(StrideReg); in reload()
262 MO.setReg(TileReg); in reload()
419 MO.setReg(StrideReg); in convertPHI()
482 InMO->setReg(DefTileReg); in canonicalizePHIs()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLocalizer.cpp137 LocalizedMI->getOperand(0).setReg(NewReg); in localizeInterBlock()
145 MOUse.setReg(NewVRegIt->second); in localizeInterBlock()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsOptimizePICCall.cpp157 I->getOperand(0).setReg(DstReg); in setCallTargetReg()
248 getCallTargetRegOpnd(*I)->setReg(getReg(Entry)); in visitNode()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ExpandSpecialInstrs.cpp91 DstOp.setReg(R600::OQAP); in runOnMachineFunction()
97 Mov->getOperand(MovPredSelIdx).setReg( in runOnMachineFunction()

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