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Searched refs:setDesc (Results 1 – 25 of 122) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyLowerBrUnless.cpp80 Def->setDesc(TII.get(NE_I32)); in runOnMachineFunction()
84 Def->setDesc(TII.get(EQ_I32)); in runOnMachineFunction()
88 Def->setDesc(TII.get(LE_S_I32)); in runOnMachineFunction()
92 Def->setDesc(TII.get(LT_S_I32)); in runOnMachineFunction()
96 Def->setDesc(TII.get(GE_S_I32)); in runOnMachineFunction()
100 Def->setDesc(TII.get(GT_S_I32)); in runOnMachineFunction()
104 Def->setDesc(TII.get(LE_U_I32)); in runOnMachineFunction()
108 Def->setDesc(TII.get(LT_U_I32)); in runOnMachineFunction()
112 Def->setDesc(TII.get(GE_U_I32)); in runOnMachineFunction()
116 Def->setDesc(TII.get(GT_U_I32)); in runOnMachineFunction()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp258 MIB->setDesc(TII.get(ARM::VMOVDRR)); in selectMergeValues()
290 MIB->setDesc(TII.get(ARM::VMOVRRD)); in selectUnmergeValues()
679 MIB->setDesc(TII.get(Opc)); in selectGlobal()
717 MIB->setDesc(TII.get(Opc)); in selectGlobal()
737 MIB->setDesc(TII.get(Opcodes.ADDrr)); in selectGlobal()
749 MIB->setDesc(TII.get(Opcodes.MOVi32imm)); in selectGlobal()
752 MIB->setDesc(TII.get(Opcodes.ConstPoolLoad)); in selectGlobal()
758 MIB->setDesc(TII.get(Opcodes.MOVi32imm)); in selectGlobal()
760 MIB->setDesc(TII.get(Opcodes.LDRLIT_ga_abs)); in selectGlobal()
809 MIB->setDesc(TII.get(ARM::MOVsr)); in selectShift()
[all …]
H A DThumb2InstrInfo.cpp577 MI.setDesc(TII.get(ARM::tMOVr)); in rewriteT2FrameIndex()
592 MI.setDesc(IsSP ? TII.get(ARM::t2SUBspImm) : TII.get(ARM::t2SUBri)); in rewriteT2FrameIndex()
594 MI.setDesc(IsSP ? TII.get(ARM::t2ADDspImm) : TII.get(ARM::t2ADDri)); in rewriteT2FrameIndex()
612 MI.setDesc(TII.get(NewOpc)); in rewriteT2FrameIndex()
732 MI.setDesc(TII.get(NewOpc)); in rewriteT2FrameIndex()
775 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc))); in rewriteT2FrameIndex()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZShortenInst.cpp96 MI.setDesc(TII->get(LLIxL)); in shortenIIF()
101 MI.setDesc(TII->get(LLIxH)); in shortenIIF()
112 MI.setDesc(TII->get(Opcode)); in shortenOn0()
123 MI.setDesc(TII->get(Opcode)); in shortenOn01()
136 MI.setDesc(TII->get(Opcode)); in shortenOn001()
169 MI.setDesc(TII->get(Opcode)); in shortenFPConv()
196 MI.setDesc(TII->get(Opcode)); in shortenFusedFPOp()
365 MI.setDesc(TII->get(TwoOperandOpcode)); in processBlock()
H A DSystemZPostRewrite.cpp88 MBBI->setDesc(TII->get(LowOpcode)); in selectLOCRMux()
90 MBBI->setDesc(TII->get(HighOpcode)); in selectLOCRMux()
139 MBBI->setDesc(TII->get(LowOpcode)); in selectSELRMux()
141 MBBI->setDesc(TII->get(HighOpcode)); in selectSELRMux()
216 MI.setDesc(TII->get(TargetMemOpcode)); in selectMI()
H A DSystemZInstrInfo.cpp98 HighPartMI->setDesc(get(HighOpcode)); in splitMove()
99 LowPartMI->setDesc(get(LowOpcode)); in splitMove()
145 MI->setDesc(get(NewOpcode)); in splitAdjDynAlloc()
160 MI.setDesc(get(IsHigh ? HighOpcode : LowOpcode)); in expandRIPseudo()
177 MI.setDesc(get(LowOpcodeK)); in expandRIEPseudo()
185 MI.setDesc(get(DestIsHigh ? HighOpcode : LowOpcode)); in expandRIEPseudo()
199 MI.setDesc(get(Opcode)); in expandRXYPseudo()
209 MI.setDesc(get(Opcode)); in expandLOCPseudo()
254 MI->setDesc(get(SystemZ::LG)); in expandLoadStackGuard()
683 UseMI.setDesc(get(SystemZ::REG_SEQUENCE)); in foldImmediate()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIOptimizeExecMasking.cpp217 MI.setDesc(TII->get(RegSrc ? AMDGPU::COPY : AMDGPU::S_MOV_B32)); in removeTerminatorBit()
222 MI.setDesc(TII->get(RegSrc ? AMDGPU::COPY : AMDGPU::S_MOV_B64)); in removeTerminatorBit()
228 MI.setDesc(TII->get(AMDGPU::S_XOR_B64)); in removeTerminatorBit()
234 MI.setDesc(TII->get(AMDGPU::S_XOR_B32)); in removeTerminatorBit()
240 MI.setDesc(TII->get(AMDGPU::S_OR_B64)); in removeTerminatorBit()
246 MI.setDesc(TII->get(AMDGPU::S_OR_B32)); in removeTerminatorBit()
252 MI.setDesc(TII->get(AMDGPU::S_ANDN2_B64)); in removeTerminatorBit()
258 MI.setDesc(TII->get(AMDGPU::S_ANDN2_B32)); in removeTerminatorBit()
264 MI.setDesc(TII->get(AMDGPU::S_AND_B64)); in removeTerminatorBit()
270 MI.setDesc(TII->get(AMDGPU::S_AND_B32)); in removeTerminatorBit()
H A DSIFoldOperands.cpp348 MI->setDesc(TII->get(NegOpcode)); in tryFoldImmWithOpSel()
411 MI->setDesc(TII->get(AMDGPU::IMPLICIT_DEF)); in updateOperand()
425 MI->setDesc(TII->get(NewMFMAOpc)); in updateOperand()
478 MI->setDesc(TII->get(NewOpc)); in tryAddToFoldList()
502 MI->setDesc(TII->get(Opc)); in tryAddToFoldList()
518 MI->setDesc(TII->get(NewOpc)); in tryAddToFoldList()
530 MI->setDesc(TII->get(Opc)); in tryAddToFoldList()
548 MI->setDesc(TII->get(ImmOpc)); in tryAddToFoldList()
827 UseMI->setDesc(TII->get(NewOpc)); in foldOperand()
853 UseMI->setDesc(TII->get(AMDGPU::V_ACCVGPR_WRITE_B32_e64)); in foldOperand()
[all …]
H A DSIShrinkInstructions.cpp266 MI.setDesc(TII->get(SOPKOpc)); in shrinkScalarCompare()
278 MI.setDesc(NewDesc); in shrinkScalarCompare()
387 MI.setDesc(TII->get(NewOpcode)); in shrinkMIMG()
500 MI.setDesc(TII->get(NewOpcode)); in shrinkMadFma()
559 MI.setDesc(TII->get(Opc)); in shrinkScalarLogicOp()
828 MI.setDesc(TII->get(ModOpcode)); in runOnMachineFunction()
870 MI.setDesc(TII->get(Opc)); in runOnMachineFunction()
891 MI.setDesc(TII->get(AMDGPU::S_MOVK_I32)); in runOnMachineFunction()
895 MI.setDesc(TII->get(ModOpc)); in runOnMachineFunction()
H A DSIModeRegister.cpp181 MI.setDesc(TII->get(AMDGPU::V_CVT_F16_F32_t16_e64)); in getInstructionMode()
189 MI.setDesc(TII->get(AMDGPU::V_CVT_F16_F32_e32)); in getInstructionMode()
198 MI.setDesc(TII->get(AMDGPU::V_CVT_F16_F32_t16_e64)); in getInstructionMode()
206 MI.setDesc(TII->get(AMDGPU::V_CVT_F16_F32_e32)); in getInstructionMode()
H A DSIPreEmitPeephole.cpp196 MI.setDesc(TII->get(AMDGPU::S_BRANCH)); in optimizeVccBranch()
224 MI.setDesc(TII->get(AMDGPU::S_BRANCH)); in optimizeVccBranch()
234 MI.setDesc( in optimizeVccBranch()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVERegisterInfo.cpp251 MI.setDesc(get(VE::STrii)); in processSTQ()
271 MI.setDesc(get(VE::LDrii)); in processLDQ()
310 MI.setDesc(get(VE::STrii)); in processSTVM()
346 MI.setDesc(get(VE::LDrii)); in processLDVM()
408 MI.setDesc(get(VE::STrii)); in processSTVM512()
447 MI.setDesc(get(VE::LDrii)); in processLDVM512()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp
H A DX86FixupInstTuning.cpp139 MI.setDesc(TII->get(NewOpc)); in processInstruction()
154 MI.setDesc(TII->get(NewOpc)); in processInstruction()
168 MI.setDesc(TII->get(NewOpc)); in processInstruction()
190 MI.setDesc(TII->get(NewOpc)); in processInstruction()
202 MI.setDesc(TII->get(NewOpc)); in processInstruction()
H A DX86ExpandPseudo.cpp558 MI.setDesc(TII->get(GET_EGPR_IF_ENABLED(X86::LDTILECFG))); in expandMI()
568 MI.setDesc(TII->get(Opc)); in expandMI()
594 MI.setDesc(TII->get(Opc)); in expandMI()
601 MI.setDesc(TII->get(GET_EGPR_IF_ENABLED(X86::TILESTORED))); in expandMI()
608 MI.setDesc(TII->get(X86::TILEZERO)); in expandMI()
698 MI.setDesc(TII->get(LoadOpc)); in expandMI()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DExpandPostRAPseudos.cpp82 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerSubregToReg()
95 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerSubregToReg()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86InstructionSelector.cpp350 I.setDesc(TII.get(X86::COPY)); in selectCopy()
594 I.setDesc(TII.get(NewOpc)); in selectLoadStoreOp()
656 I.setDesc(TII.get(NewOpc)); in selectFrameIndexOrGep()
708 I.setDesc(TII.get(NewOpc)); in selectGlobalValue()
760 I.setDesc(TII.get(NewOpc)); in selectConstant()
785 I.setDesc(TII.get(X86::COPY)); in selectTurnIntoCOPY()
851 I.setDesc(TII.get(X86::COPY)); in selectTruncOrPtrToInt()
960 I.setDesc(TII.get(X86::COPY)); in selectAnyext()
1258 I.setDesc(TII.get(X86::VEXTRACTF32x4Z256rr)); in selectExtract()
1260 I.setDesc(TII.get(X86::VEXTRACTF128rr)); in selectExtract()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CompressJumpTables.cpp148 MI.setDesc(TII->get(AArch64::JumpTableDest8)); in compressJumpTable()
154 MI.setDesc(TII->get(AArch64::JumpTableDest16)); in compressJumpTable()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrInfo.cpp373 MIB->setDesc(get(M68k::MOVQ)); in ExpandMOVI()
377 MIB->setDesc(get(MVTSize == MVT::i16 ? M68k::MOV16ri : M68k::MOV32ri)); in ExpandMOVI()
413 MIB->setDesc(get(Move)); in ExpandMOVX_RR()
490 MIB->setDesc(Desc); in ExpandMOVSZX_RM()
529 MIB->setDesc(get(M68k::MOV16cd)); in ExpandCCR()
532 MIB->setDesc(get(M68k::MOV16dc)); in ExpandCCR()
600 MIB->setDesc(Desc); in Expand2AddrUndef()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DDelaySlotFiller.cpp190 slot->setDesc(Subtarget->getInstrInfo()->get(SP::RET)); in findDelayInstr()
393 AddMI->setDesc(TII->get((AddMI->getOpcode() == SP::ADDrr) in combineRestoreADD()
432 OrMI->setDesc(TII->get((OrMI->getOpcode() == SP::ORrr) in combineRestoreOR()
469 RestoreMI->setDesc(TII->get(SP::RESTOREri)); in combineRestoreSETHIi()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCEarlyReturn.cpp93 MI->setDesc(TII->get(PPC::BCCLR)); in processBlock()
110 MI->setDesc( in processBlock()
H A DPPCInstrInfo.cpp2183 MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR) in PredicateInstruction()
2190 MI.setDesc(get(PPC::BCLR)); in PredicateInstruction()
2193 MI.setDesc(get(PPC::BCLRn)); in PredicateInstruction()
2196 MI.setDesc(get(PPC::BCCLR)); in PredicateInstruction()
2206 MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) in PredicateInstruction()
2216 MI.setDesc(get(PPC::BC)); in PredicateInstruction()
2224 MI.setDesc(get(PPC::BCn)); in PredicateInstruction()
2232 MI.setDesc(get(PPC::BCC)); in PredicateInstruction()
2251 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8) in PredicateInstruction()
2255 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n) in PredicateInstruction()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVInstructionSelector.cpp542 MI.setDesc(TII.get(TargetOpcode::PHI)); in select()
687 MI.setDesc(TII.get(RISCV::PseudoBRIND)); in select()
696 MI.setDesc(TII.get(RISCV::ADDI)); in select()
736 MI.setDesc(TII.get(RISCV::BuildPairF64Pseudo)); in selectMergeValues()
752 MI.setDesc(TII.get(RISCV::SplitF64Pseudo)); in selectUnmergeValues()
778 MI.setDesc(TII.get(TargetOpcode::G_ADD)); in preISelLower()
786 MI.setDesc(TII.get(TargetOpcode::G_AND)); in preISelLower()
910 MI.setDesc(TII.get(RISCV::COPY)); in selectCopy()
929 MI.setDesc(TII.get(TargetOpcode::IMPLICIT_DEF)); in selectImplicitDef()
1007 MI.setDesc(TII.get(RISCV::PseudoLLA)); in selectAddr()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVISelLowering.cpp402 MI.setDesc(STI.getInstrInfo()->get(SPIRV::OpLogicalOr)); in finalizeLowering()
408 MI.setDesc(STI.getInstrInfo()->get(SPIRV::OpLogicalAnd)); in finalizeLowering()
414 MI.setDesc(STI.getInstrInfo()->get(SPIRV::OpLogicalNotEqual)); in finalizeLowering()
429 MI.setDesc(STI.getInstrInfo()->get(SPIRV::OpConstantNull)); in finalizeLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVVectorPeephole.cpp189 MI.setDesc(TII->get(NewOpc)); in convertVMergeToVMv()
228 MI.setDesc(MCID); in convertToUnmasked()

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