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Searched refs:setDesc (Results 1 – 25 of 128) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyLowerBrUnless.cpp80 Def->setDesc(TII.get(NE_I32)); in runOnMachineFunction()
84 Def->setDesc(TII.get(EQ_I32)); in runOnMachineFunction()
88 Def->setDesc(TII.get(LE_S_I32)); in runOnMachineFunction()
92 Def->setDesc(TII.get(LT_S_I32)); in runOnMachineFunction()
96 Def->setDesc(TII.get(GE_S_I32)); in runOnMachineFunction()
100 Def->setDesc(TII.get(GT_S_I32)); in runOnMachineFunction()
104 Def->setDesc(TII.get(LE_U_I32)); in runOnMachineFunction()
108 Def->setDesc(TII.get(LT_U_I32)); in runOnMachineFunction()
112 Def->setDesc(TII.get(GE_U_I32)); in runOnMachineFunction()
116 Def->setDesc(TII.get(GT_U_I32)); in runOnMachineFunction()
[all …]
H A DWebAssemblyRegStackify.cpp110 MI->setDesc(TII->get(WebAssembly::CONST_I32)); in convertImplicitDefToConstZero()
113 MI->setDesc(TII->get(WebAssembly::CONST_I64)); in convertImplicitDefToConstZero()
116 MI->setDesc(TII->get(WebAssembly::CONST_F32)); in convertImplicitDefToConstZero()
121 MI->setDesc(TII->get(WebAssembly::CONST_F64)); in convertImplicitDefToConstZero()
126 MI->setDesc(TII->get(WebAssembly::CONST_V128_I64x2)); in convertImplicitDefToConstZero()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZShortenInst.cpp93 MI.setDesc(TII->get(LLIxL)); in shortenIIF()
98 MI.setDesc(TII->get(LLIxH)); in shortenIIF()
109 MI.setDesc(TII->get(Opcode)); in shortenOn0()
120 MI.setDesc(TII->get(Opcode)); in shortenOn01()
133 MI.setDesc(TII->get(Opcode)); in shortenOn001()
166 MI.setDesc(TII->get(Opcode)); in shortenFPConv()
193 MI.setDesc(TII->get(Opcode)); in shortenFusedFPOp()
362 MI.setDesc(TII->get(TwoOperandOpcode)); in processBlock()
H A DSystemZPostRewrite.cpp87 MBBI->setDesc(TII->get(LowOpcode)); in selectLOCRMux()
89 MBBI->setDesc(TII->get(HighOpcode)); in selectLOCRMux()
159 MBBI->setDesc(TII->get(LowOpcode)); in selectSELRMux()
161 MBBI->setDesc(TII->get(HighOpcode)); in selectSELRMux()
239 MI.setDesc(TII->get(TargetMemOpcode)); in selectMI()
H A DSystemZInstrInfo.cpp100 HighPartMI->setDesc(get(HighOpcode)); in splitMove()
101 LowPartMI->setDesc(get(LowOpcode)); in splitMove()
147 MI->setDesc(get(NewOpcode)); in splitAdjDynAlloc()
162 MI.setDesc(get(IsHigh ? HighOpcode : LowOpcode)); in expandRIPseudo()
179 MI.setDesc(get(LowOpcodeK)); in expandRIEPseudo()
187 MI.setDesc(get(DestIsHigh ? HighOpcode : LowOpcode)); in expandRIEPseudo()
201 MI.setDesc(get(Opcode)); in expandRXYPseudo()
211 MI.setDesc(get(Opcode)); in expandLOCPseudo()
256 MI->setDesc(get(SystemZ::LG)); in expandLoadStackGuard()
705 UseMI.setDesc(get(SystemZ::REG_SEQUENCE)); in foldImmediate()
[all …]
H A DSystemZElimCompare.cpp219 Branch->setDesc(TII->get(BRCT)); in convertToBRCT()
265 Branch->setDesc(TII->get(LATOpcode)); in convertToLoadAndTrap()
331 MI.setDesc(TII->get(ConvOpc)); in convertToLogical()
659 Branch->setDesc(TII->get(FusedOpcode)); in fuseCompareOperations()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp258 MIB->setDesc(TII.get(ARM::VMOVDRR)); in selectMergeValues()
290 MIB->setDesc(TII.get(ARM::VMOVRRD)); in selectUnmergeValues()
679 MIB->setDesc(TII.get(Opc)); in selectGlobal()
717 MIB->setDesc(TII.get(Opc)); in selectGlobal()
737 MIB->setDesc(TII.get(Opcodes.ADDrr)); in selectGlobal()
749 MIB->setDesc(TII.get(Opcodes.MOVi32imm)); in selectGlobal()
752 MIB->setDesc(TII.get(Opcodes.ConstPoolLoad)); in selectGlobal()
758 MIB->setDesc(TII.get(Opcodes.MOVi32imm)); in selectGlobal()
760 MIB->setDesc(TII.get(Opcodes.LDRLIT_ga_abs)); in selectGlobal()
809 MIB->setDesc(TII.get(ARM::MOVsr)); in selectShift()
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H A DThumb2InstrInfo.cpp579 MI.setDesc(TII.get(ARM::tMOVr)); in rewriteT2FrameIndex()
594 MI.setDesc(IsSP ? TII.get(ARM::t2SUBspImm) : TII.get(ARM::t2SUBri)); in rewriteT2FrameIndex()
596 MI.setDesc(IsSP ? TII.get(ARM::t2ADDspImm) : TII.get(ARM::t2ADDri)); in rewriteT2FrameIndex()
614 MI.setDesc(TII.get(NewOpc)); in rewriteT2FrameIndex()
734 MI.setDesc(TII.get(NewOpc)); in rewriteT2FrameIndex()
777 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc))); in rewriteT2FrameIndex()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIOptimizeExecMasking.cpp236 MI.setDesc(TII->get(RegSrc ? AMDGPU::COPY : AMDGPU::S_MOV_B32)); in removeTerminatorBit()
241 MI.setDesc(TII->get(RegSrc ? AMDGPU::COPY : AMDGPU::S_MOV_B64)); in removeTerminatorBit()
247 MI.setDesc(TII->get(AMDGPU::S_XOR_B64)); in removeTerminatorBit()
253 MI.setDesc(TII->get(AMDGPU::S_XOR_B32)); in removeTerminatorBit()
259 MI.setDesc(TII->get(AMDGPU::S_OR_B64)); in removeTerminatorBit()
265 MI.setDesc(TII->get(AMDGPU::S_OR_B32)); in removeTerminatorBit()
271 MI.setDesc(TII->get(AMDGPU::S_ANDN2_B64)); in removeTerminatorBit()
277 MI.setDesc(TII->get(AMDGPU::S_ANDN2_B32)); in removeTerminatorBit()
283 MI.setDesc(TII->get(AMDGPU::S_AND_B64)); in removeTerminatorBit()
289 MI.setDesc(TII->get(AMDGPU::S_AND_B32)); in removeTerminatorBit()
H A DSIShrinkInstructions.cpp277 MI.setDesc(TII->get(SOPKOpc)); in shrinkScalarCompare()
289 MI.setDesc(NewDesc); in shrinkScalarCompare()
398 MI.setDesc(TII->get(NewOpcode)); in shrinkMIMG()
528 MI.setDesc(TII->get(NewOpcode)); in shrinkMadFma()
587 MI.setDesc(TII->get(Opc)); in shrinkScalarLogicOp()
873 MI.setDesc(TII->get(ModOpcode)); in run()
916 MI.setDesc(TII->get(Opc)); in run()
937 MI.setDesc(TII->get(AMDGPU::S_MOVK_I32)); in run()
941 MI.setDesc(TII->get(ModOpc)); in run()
H A DSIModeRegister.cpp188 MI.setDesc(TII->get(AMDGPU::V_CVT_F16_F32_e32)); in getInstructionMode()
194 MI.setDesc(TII->get(AMDGPU::V_CVT_F16_F32_fake16_e32)); in getInstructionMode()
200 MI.setDesc(TII->get(AMDGPU::V_CVT_F16_F32_t16_e64)); in getInstructionMode()
206 MI.setDesc(TII->get(AMDGPU::V_CVT_F32_F64_e32)); in getInstructionMode()
H A DSIPreEmitPeephole.cpp198 MI.setDesc(TII->get(AMDGPU::S_BRANCH)); in optimizeVccBranch()
226 MI.setDesc(TII->get(AMDGPU::S_BRANCH)); in optimizeVccBranch()
236 MI.setDesc( in optimizeVccBranch()
H A DSIFoldOperands.cpp599 MI->setDesc(TII->get(NegOpcode)); in tryFoldImmWithOpSel()
666 MI->setDesc(TII->get(AMDGPU::IMPLICIT_DEF)); in updateOperand()
680 MI->setDesc(TII->get(NewMFMAOpc)); in updateOperand()
746 MI->setDesc(TII->get(NewOpc)); in tryAddToFoldList()
770 MI->setDesc(TII->get(Opc)); in tryAddToFoldList()
786 MI->setDesc(TII->get(NewOpc)); in tryAddToFoldList()
798 MI->setDesc(TII->get(Opc)); in tryAddToFoldList()
816 MI->setDesc(TII->get(ImmOpc)); in tryAddToFoldList()
1221 UseMI->setDesc(TII->get(NewOpc)); in foldOperand()
1248 UseMI->setDesc(TII->get(AMDGPU::V_ACCVGPR_WRITE_B32_e64)); in foldOperand()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FixupInstTuning.cpp140 MI.setDesc(TII->get(NewOpc)); in processInstruction()
159 MI.setDesc(TII->get(NewOpc)); in processInstruction()
177 MI.setDesc(TII->get(NewOpc)); in processInstruction()
202 MI.setDesc(TII->get(NewOpc)); in processInstruction()
218 MI.setDesc(TII->get(NewOpc)); in processInstruction()
257 MI.setDesc(TII->get(MovOpc)); in processInstruction()
273 MI.setDesc(TII->get(MovOpc)); in processInstruction()
H A DX86InstructionSelector.cpp
H A DX86ExpandPseudo.cpp570 MI.setDesc(TII->get(GET_EGPR_IF_ENABLED(X86::LDTILECFG))); in expandMI()
644 MI.setDesc(TII->get(Opc)); in expandMI()
779 MI.setDesc(TII->get(Opc)); in expandMI()
786 MI.setDesc(TII->get(Opcode == X86::PTTRANSPOSEDV ? X86::TTRANSPOSED in expandMI()
859 MI.setDesc(TII->get(Opc)); in expandMI()
866 MI.setDesc(TII->get(GET_EGPR_IF_ENABLED(X86::TILESTORED))); in expandMI()
873 MI.setDesc(TII->get(X86::TILEZERO)); in expandMI()
882 MI.setDesc(TII->get(X86::CALL64r)); in expandMI()
966 MI.setDesc(TII->get(LoadOpc)); in expandMI()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVERegisterInfo.cpp247 MI.setDesc(get(VE::STrii)); in processSTQ()
267 MI.setDesc(get(VE::LDrii)); in processLDQ()
306 MI.setDesc(get(VE::STrii)); in processSTVM()
342 MI.setDesc(get(VE::LDrii)); in processLDVM()
404 MI.setDesc(get(VE::STrii)); in processSTVM512()
443 MI.setDesc(get(VE::LDrii)); in processLDVM512()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CompressJumpTables.cpp143 MI.setDesc(TII->get(AArch64::JumpTableDest8)); in compressJumpTable()
149 MI.setDesc(TII->get(AArch64::JumpTableDest16)); in compressJumpTable()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrInfo.cpp378 MIB->setDesc(get(M68k::MOVQ)); in ExpandMOVI()
421 MIB->setDesc(get(M68k::MOV16ai)); in ExpandMOVI()
427 MIB->setDesc(get(MVTSize == MVT::i16 ? M68k::MOV16ri : M68k::MOV32ri)); in ExpandMOVI()
463 MIB->setDesc(get(Move)); in ExpandMOVX_RR()
540 MIB->setDesc(Desc); in ExpandMOVSZX_RM()
585 MIB->setDesc(get(M68k::MOV16cd)); in ExpandCCR()
588 MIB->setDesc(get(M68k::MOV16dc)); in ExpandCCR()
643 MIB->setDesc(Desc); in Expand2AddrUndef()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86InstructionSelector.cpp354 I.setDesc(TII.get(X86::COPY)); in selectCopy()
663 I.setDesc(TII.get(NewOpc)); in selectLoadStoreOp()
707 I.setDesc(TII.get(NewOpc)); in selectFrameIndexOrGep()
736 I.setDesc(TII.get(NewOpc)); in selectGlobalValue()
788 I.setDesc(TII.get(NewOpc)); in selectConstant()
813 I.setDesc(TII.get(X86::COPY)); in selectTurnIntoCOPY()
879 I.setDesc(TII.get(X86::COPY)); in selectTruncOrPtrToInt()
988 I.setDesc(TII.get(X86::COPY)); in selectAnyext()
1298 I.setDesc(TII.get(X86::VEXTRACTF32X4Z256rri)); in selectExtract()
1300 I.setDesc(TII.get(X86::VEXTRACTF128rri)); in selectExtract()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DExpandPostRAPseudos.cpp101 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerSubregToReg()
114 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerSubregToReg()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DDelaySlotFiller.cpp188 slot->setDesc(Subtarget->getInstrInfo()->get(SP::RET)); in findDelayInstr()
410 AddMI->setDesc(TII->get((AddMI->getOpcode() == SP::ADDrr) in combineRestoreADD()
449 OrMI->setDesc(TII->get((OrMI->getOpcode() == SP::ORrr) in combineRestoreOR()
486 RestoreMI->setDesc(TII->get(SP::RESTOREri)); in combineRestoreSETHIi()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCEarlyReturn.cpp82 MI->setDesc(TII->get(PPC::BCCLR)); in processBlock()
99 MI->setDesc( in processBlock()
H A DPPCInstrInfo.cpp2206 MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZLR8 : PPC::BDNZLR) in PredicateInstruction()
2213 MI.setDesc(get(PPC::BCLR)); in PredicateInstruction()
2216 MI.setDesc(get(PPC::BCLRn)); in PredicateInstruction()
2219 MI.setDesc(get(PPC::BCCLR)); in PredicateInstruction()
2229 MI.setDesc(get(Pred[0].getImm() ? (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) in PredicateInstruction()
2239 MI.setDesc(get(PPC::BC)); in PredicateInstruction()
2247 MI.setDesc(get(PPC::BCn)); in PredicateInstruction()
2255 MI.setDesc(get(PPC::BCC)); in PredicateInstruction()
2274 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8 : PPC::BCCTR8) in PredicateInstruction()
2278 MI.setDesc(get(isPPC64 ? (setLR ? PPC::BCCTRL8n : PPC::BCCTR8n) in PredicateInstruction()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVISelLowering.cpp461 MI.setDesc(STI.getInstrInfo()->get(SPIRV::OpLogicalNotEqual)); in finalizeLowering()
470 MI.setDesc(STI.getInstrInfo()->get(SPIRV::OpLogicalOr)); in finalizeLowering()
476 MI.setDesc(STI.getInstrInfo()->get(SPIRV::OpLogicalAnd)); in finalizeLowering()
482 MI.setDesc(STI.getInstrInfo()->get(SPIRV::OpLogicalNotEqual)); in finalizeLowering()
502 MI.setDesc(STI.getInstrInfo()->get(SPIRV::OpConstantNull)); in finalizeLowering()

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