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Searched refs:rs1 (Results 1 – 25 of 94) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoD.td187 def : InstAlias<"fld $rd, (${rs1})", (FLD FPR64:$rd, GPR:$rs1, 0), 0>;
188 def : InstAlias<"fsd $rs2, (${rs1})", (FSD FPR64:$rs2, GPR:$rs1, 0), 0>;
248 def : Pat<(any_fpround FPR64:$rs1), (FCVT_S_D FPR64:$rs1, FRM_DYN)>;
249 def : Pat<(any_fpextend FPR32:$rs1), (FCVT_D_S FPR32:$rs1, FRM_RNE)>;
256 def : Pat<(any_fpround FPR64INX:$rs1), (FCVT_S_D_INX FPR64INX:$rs1, FRM_DYN)>;
257 def : Pat<(any_fpextend FPR32INX:$rs1), (FCVT_D_S_INX FPR32INX:$rs1, FRM_RNE)>;
264 def : Pat<(any_fpround FPR64IN32X:$rs1), (FCVT_S_D_IN32X FPR64IN32X:$rs1, FRM_DYN)>;
265 def : Pat<(any_fpextend FPR32INX:$rs1), (FCVT_D_S_IN32X FPR32INX:$rs1, FRM_RNE)>;
281 def : Pat<(any_fsqrt FPR64:$rs1), (FSQRT_D FPR64:$rs1, FRM_DYN)>;
283 def : Pat<(fneg FPR64:$rs1), (FSGNJN_D $rs1, $rs1)>;
[all …]
H A DRISCVInstrInfoZfh.td231 def : InstAlias<"flh $rd, (${rs1})", (FLH FPR16:$rd, GPR:$rs1, 0), 0>;
232 def : InstAlias<"fsh $rs2, (${rs1})", (FSH FPR16:$rs2, GPR:$rs1, 0), 0>;
294 def : Pat<(f16 (any_fsqrt FPR16:$rs1)), (FSQRT_H FPR16:$rs1, FRM_DYN)>;
296 def : Pat<(f16 (fneg FPR16:$rs1)), (FSGNJN_H $rs1, $rs1)>;
297 def : Pat<(f16 (fabs FPR16:$rs1)), (FSGNJX_H $rs1, $rs1)>;
299 def : Pat<(riscv_fclass (f16 FPR16:$rs1)), (FCLASS_H $rs1)>;
303 def : Pat<(f16 (fcopysign FPR16:$rs1, (f16 (fneg FPR16:$rs2)))),
304 (FSGNJN_H FPR16:$rs1, FPR16:$rs2)>;
305 def : Pat<(f16 (fcopysign FPR16:$rs1, FPR32:$rs2)),
306 (FSGNJ_H $rs1, (f16 (FCVT_H_S $rs2, FRM_DYN)))>;
[all …]
H A DRISCVInstrInfoXwch.td65 (ins GPRCMem:$rs1, uimm5:$imm),
66 "qk.c.lbu", "$rd, ${imm}(${rs1})">,
75 (ins GPRC:$rs2, GPRCMem:$rs1,
77 "qk.c.sb", "$rs2, ${imm}(${rs1})">,
87 (ins GPRCMem:$rs1, uimm6_lsb0:$imm),
88 "qk.c.lhu", "$rd, ${imm}(${rs1})">,
96 (ins GPRC:$rs2, GPRCMem:$rs1, uimm6_lsb0:$imm),
97 "qk.c.sh", "$rs2, ${imm}(${rs1})">,
106 (ins SPMem:$rs1, uimm4:$imm),
107 "qk.c.lbusp", "$rd_rs2, ${imm}(${rs1})">,
[all …]
H A DRISCVInstrInfoC.td238 : RVInst16CI<funct3, 0b10, (outs cls:$rd), (ins SPMem:$rs1, opnd:$imm),
239 OpcodeStr, "$rd, ${imm}(${rs1})">;
244 : RVInst16CSS<funct3, 0b10, (outs), (ins cls:$rs2, SPMem:$rs1, opnd:$imm),
245 OpcodeStr, "$rs2, ${imm}(${rs1})">;
250 : RVInst16CL<funct3, 0b00, (outs cls:$rd), (ins GPRCMem:$rs1, opnd:$imm),
251 OpcodeStr, "$rd, ${imm}(${rs1})">;
256 : RVInst16CS<funct3, 0b00, (outs), (ins cls:$rs2,GPRCMem:$rs1, opnd:$imm),
257 OpcodeStr, "$rs2, ${imm}(${rs1})">;
261 : RVInst16CB<funct3, 0b01, (outs), (ins GPRC:$rs1, bare_simm9_lsb0:$imm),
262 OpcodeStr, "$rs1, $imm"> {
[all …]
H A DRISCVInstrInfoZc.td108 (ins GPRCMem:$rs1, uimm2:$imm),
109 OpcodeStr, "$rd, ${imm}(${rs1})"> {
119 (ins GPRCMem:$rs1, uimm2_lsb0:$imm),
120 OpcodeStr, "$rd, ${imm}(${rs1})"> {
129 (ins GPRC:$rs2, GPRCMem:$rs1, uimm2:$imm),
130 OpcodeStr, "$rs2, ${imm}(${rs1})"> {
140 (ins rty:$rs2, GPRCMem:$rs1, uimm2_lsb0:$imm),
141 OpcodeStr, "$rs2, ${imm}(${rs1})"> {
223 (ins SR07:$rs1, SR07:$rs2), "cm.mva01s", "$rs1, $rs2">,
227 def CM_MVSA01 : RVInst16CA<0b101011, 0b01, 0b10, (outs SR07:$rs1, SR07:$rs2),
[all …]
H A DRISCVInstrInfoF.td104 def any_fma_nsz : PatFrag<(ops node:$rs1, node:$rs2, node:$rs3),
105 (any_fma node:$rs1, node:$rs2, node:$rs3), [{
199 (ins GPRMem:$rs1, simm12:$imm12),
200 opcodestr, "$rd, ${imm12}(${rs1})">,
207 (ins rty:$rs2, GPRMem:$rs1, simm12:$imm12),
208 opcodestr, "$rs2, ${imm12}(${rs1})">,
216 (ins rty:$rs1, rty:$rs2, rty:$rs3, frmarg:$frm),
217 opcodestr, "$rd, $rs1, $rs2, $rs3$frm">;
229 (ins rty:$rs1, rty:$rs2), opcodestr, "$rd, $rs1, $rs2"> {
243 (ins rty:$rs1, rty:$rs2, frmarg:$frm), opcodestr,
[all …]
H A DRISCVInstrInfoXMips.td46 bits<5> rs1;
53 let Inst{19-15} = rs1;
63 bits<5> rs1;
70 let Inst{19-15} = rs1;
82 bits<5> rs1;
87 let Inst{19-15} = rs1;
100 bits<5> rs1;
105 let Inst{19-15} = rs1;
117 bits<5> rs1;
122 let Inst{19-15} = rs1;
[all …]
H A DRISCVInstrInfoXqci.td231 bits<5> rs1;
237 let Inst{19-15} = rs1;
251 bits<5> rs1;
259 let Inst{19-15} = rs1;
297 bits<5> rs1;
305 let Inst{19-15} = rs1;
326 AnyReg:$rs1,
328 "$opcode, $func3, $func2, $rd, $rs1, $imm26">;
333 AnyReg:$rs1,
335 "$opcode, $func3, $func2, $rd, ${imm26}(${rs1})">;
[all …]
H A DRISCVGISel.td44 def : Pat<(XLenVT (setult (PtrVT GPR:$rs1), simm12:$imm12)),
45 (SLTIU GPR:$rs1, simm12:$imm12)>;
46 def : Pat<(XLenVT (setult (PtrVT GPR:$rs1), (PtrVT GPR:$rs2))),
47 (SLTU GPR:$rs1, GPR:$rs2)>;
48 def : Pat<(XLenVT (setlt (PtrVT GPR:$rs1), simm12:$imm12)),
49 (SLTI GPR:$rs1, simm12:$imm12)>;
50 def : Pat<(XLenVT (setlt (PtrVT GPR:$rs1), (PtrVT GPR:$rs2))),
51 (SLT GPR:$rs1, GPR:$rs2)>;
56 def : Pat<(XLenVT (seteq (Ty GPR:$rs1), (Ty 0))), (SLTIU GPR:$rs1, 1)>;
57 def : Pat<(XLenVT (seteq (Ty GPR:$rs1), (Ty simm12Plus1:$imm12))),
[all …]
H A DRISCVInstrInfoZb.td254 : RVInstR<funct7, funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1),
255 opcodestr, "$rd, $rs1"> {
263 (ins GPR:$rs1, uimmlog2xlen:$shamt), opcodestr,
264 "$rd, $rs1, $shamt">;
463 def : InstAlias<"ror $rd, $rs1, $shamt",
464 (RORI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>;
468 def : InstAlias<"rorw $rd, $rs1, $shamt",
469 (RORIW GPR:$rd, GPR:$rs1, uimm5:$shamt), 0>;
473 def : InstAlias<"bset $rd, $rs1, $shamt",
474 (BSETI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>;
[all …]
H A DRISCVInstrInfoXVentana.td21 (ins GPR:$rs1, GPR:$rs2), opcodestr,
22 "$rd, $rs1, $rs2"> {
32 def : Pat<(XLenVT (riscv_czero_eqz GPR:$rs1, GPR:$rc)),
33 (VT_MASKC GPR:$rs1, GPR:$rc)>;
34 def : Pat<(XLenVT (riscv_czero_nez GPR:$rs1, GPR:$rc)),
35 (VT_MASKCN GPR:$rs1, GPR:$rc)>;
37 def : Pat<(XLenVT (riscv_czero_eqz GPR:$rs1, (riscv_setne (XLenVT GPR:$rc)))),
38 (VT_MASKC GPR:$rs1, GPR:$rc)>;
39 def : Pat<(XLenVT (riscv_czero_eqz GPR:$rs1, (riscv_seteq (XLenVT GPR:$rc)))),
40 (VT_MASKCN GPR:$rs1, GPR:$rc)>;
[all …]
H A DRISCVInstrInfoZfa.td68 (ins rsty:$rs1, rsty:$rs2), opcodestr, "$rd, $rs1, $rs2">;
78 let rs1 = imm;
86 (ins rs1ty:$rs1, rtzarg:$frm), opcodestr,
87 "$rd, $rs1$frm"> {
251 def: Pat<(any_frint FPR32:$rs1), (FROUNDNX_S FPR32:$rs1, FRM_DYN)>;
254 def: Pat<(any_fnearbyint FPR32:$rs1), (FROUND_S FPR32:$rs1, FRM_DYN)>;
256 def: Pat<(any_fround FPR32:$rs1), (FROUND_S FPR32:$rs1, FRM_RMM)>;
257 def: Pat<(any_froundeven FPR32:$rs1), (FROUND_S FPR32:$rs1, FRM_RNE)>;
258 def: Pat<(any_ffloor FPR32:$rs1), (FROUND_S FPR32:$rs1, FRM_RDN)>;
259 def: Pat<(any_fceil FPR32:$rs1), (FROUND_S FPR32:$rs1, FRM_RUP)>;
[all …]
H A DRISCVInstrInfoZclsd.td75 def : InstAlias<"c.ld $rd, (${rs1})",
76 (C_LD_RV32 GPRPairCRV32:$rd, GPRCMem:$rs1, 0), 0>;
77 def : InstAlias<"c.sd $rs2, (${rs1})",
78 (C_SD_RV32 GPRPairCRV32:$rs2, GPRCMem:$rs1, 0), 0>;
79 def : InstAlias<"c.ldsp $rd, (${rs1})",
80 (C_LDSP_RV32 GPRPairNoX0RV32:$rd, SPMem:$rs1, 0), 0>;
81 def : InstAlias<"c.sdsp $rs2, (${rs1})",
82 (C_SDSP_RV32 GPRPairRV32:$rs2, SPMem:$rs1, 0), 0>;
90 def : CompressPat<(LD_RV32 GPRPairNoX0RV32:$rd, SPMem:$rs1, uimm9_lsb000:$imm),
91 (C_LDSP_RV32 GPRPairNoX0RV32:$rd, SPMem:$rs1, uimm9_lsb000:$imm)>;
[all …]
H A DRISCVInstrInfoSFB.td47 // Conditional binops, that updates update $dst to (op rs1, rs2) when condition
55 GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
60 GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
65 GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
70 GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
75 GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
80 GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
85 GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
90 GPR:$falsev, GPR:$rs1, GPR:$rs2), []>,
96 GPR:$falsev, GPR:$rs1, simm12:$rs2), []>,
[all …]
H A DRISCVInstrInfoXTHead.td92 // op vd, rs1, vs2, vm (reverse the order of rs1 and vs2)
96 (ins VR:$vd, GPR:$rs1, VR:$vs2, VMaskOp:$vm),
97 opcodestr, "$vd, $rs1, $vs2$vm"> {
106 (ins GPR:$rs1, GPR:$rs2, uimm2:$uimm2),
107 opcodestr, "$rd, $rs1, $rs2, $uimm2"> {
116 (ins GPR:$rs1, uimmlog2xlen:$shamt),
117 opcodestr, "$rd, $rs1, $shamt">;
122 (ins GPR:$rs1, uimmlog2xlen:$msb, uimmlog2xlen:$lsb),
123 opcodestr, "$rd, $rs1, $msb, $lsb"> {
133 (outs GPR:$rd), (ins GPR:$rs1), opcodestr, "$rd, $rs1">;
[all …]
H A DRISCVInstrInfoVSDPatterns.td37 def : Pat<(type (load (XLenVT GPR:$rs1))),
38 (load_instr (type (IMPLICIT_DEF)), GPR:$rs1, avl,
41 def : Pat<(store (type regclass:$rs2), (XLenVT GPR:$rs1)),
42 (store_instr reg_class:$rs2, GPR:$rs1, avl, log2sew)>;
49 def : Pat<(m.Mask (load GPR:$rs1)),
50 (load_instr (m.Mask (IMPLICIT_DEF)), GPR:$rs1, m.AVL,
53 def : Pat<(store (m.Mask VR:$rs2), GPR:$rs1),
54 (store_instr VR:$rs2, GPR:$rs1, m.AVL, m.Log2SEW)>;
67 (op_type op_reg_class:$rs1),
74 op_reg_class:$rs1,
[all …]
H A DRISCVInstrInfoXCV.td68 (ins GPR:$rs1, i3type:$is3, uimm5:$is2),
69 opcodestr, "$rd, $rs1, $is3, $is2">;
73 (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">;
77 (ins GPR:$rs1), opcodestr, "$rd, $rs1"> {
84 (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
85 opcodestr, "$rd, $rs1, $rs2"> {
95 "$rd, $rs1, $rs2, $imm5"> {
108 (ins GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$imm5), opcodestr> {
114 (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5), opcodestr>;
119 (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5), opcodestr,
[all …]
/freebsd/contrib/llvm-project/clang/lib/Headers/
H A Dsifive_vector.h16 #define __riscv_sf_vc_x_se_u8mf4(p27_26, p24_20, p11_7, rs1, vl) \ argument
17 __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint8_t)rs1, 8, 6, vl)
18 #define __riscv_sf_vc_x_se_u8mf2(p27_26, p24_20, p11_7, rs1, vl) \ argument
19 __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint8_t)rs1, 8, 7, vl)
20 #define __riscv_sf_vc_x_se_u8m1(p27_26, p24_20, p11_7, rs1, vl) \ argument
21 __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint8_t)rs1, 8, 0, vl)
22 #define __riscv_sf_vc_x_se_u8m2(p27_26, p24_20, p11_7, rs1, vl) \ argument
23 __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint8_t)rs1, 8, 1, vl)
24 #define __riscv_sf_vc_x_se_u8m4(p27_26, p24_20, p11_7, rs1, vl) \ argument
25 __riscv_sf_vc_x_se(p27_26, p24_20, p11_7, (uint8_t)rs1, 8, 2, vl)
[all …]
/freebsd/crypto/openssl/crypto/perlasm/
H A Driscv.pm286 my $rs1 = read_reg shift;
288 return ".word ".($template | ($rs2 << 20) | ($rs1 << 15) | ($rd << 7));
296 my $rs1 = read_reg shift;
298 return ".word ".($template | ($rs2 << 20) | ($rs1 << 15) | ($rd << 7));
306 my $rs1 = read_reg shift;
308 return ".word ".($template | ($rs2 << 20) | ($rs1 << 15) | ($rd << 7));
316 my $rs1 = read_reg shift;
318 return ".word ".($template | ($rs2 << 20) | ($rs1 << 15) | ($rd << 7));
326 my $rs1 = read_reg shift;
327 return ".word ".($template | ($rs1 << 15) | ($rd << 7));
[all …]
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/
H A DEmulateInstructionRISCV.cpp168 static bool CompareB(uint64_t rs1, uint64_t rs2, uint32_t funct3) { in CompareB() argument
171 return rs1 == rs2; in CompareB()
173 return rs1 != rs2; in CompareB()
175 return int64_t(rs1) < int64_t(rs2); in CompareB()
177 return int64_t(rs1) >= int64_t(rs2); in CompareB()
179 return rs1 < rs2; in CompareB()
181 return rs1 >= rs2; in CompareB()
221 return transformOptional(inst.rs1.Read(emulator), [&](uint64_t rs1) { in LoadStoreAddr() argument
222 return rs1 + uint64_t(SignExt(inst.imm)); in LoadStoreAddr()
256 return transformOptional(inst.rs1.Read(emulator), in AtomicAddr()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstrVIS.td19 (outs RC:$rd), (ins RC:$rs1, RC:$rs2),
20 !strconcat(OpcStr, " $rs1, $rs2, $rd")>;
25 (outs I64Regs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
26 !strconcat(OpcStr, " $rs1, $rs2, $rd")>;
29 let rd = 0, rs1 = 0, rs2 = 0 in
33 // For VIS Instructions with only rs1, rd operands.
37 (outs RC:$rd), (ins RC:$rs1),
38 !strconcat(OpcStr, " $rs1, $rd")>;
41 let rs1 = 0 in
48 let rs1 = 0, rs2 = 0 in
[all …]
H A DSparcInstrUAOSA.td16 let rs1 = 0;
23 : F3_4<op3val, op5val, (outs RC:$rd), (ins RC:$rs1, RC:$rs2, RC:$rs3),
24 !strconcat(OpcStr, " $rs1, $rs2, $rs3, $rd")>;
29 (ins cbtarget:$imm10, CCOp:$cond, IntRegs:$rs1, IntRegs:$rs2),
30 !strconcat(OpcStr, "$cond $rs1, $rs2, $imm10")>;
32 (ins cbtarget:$imm10, CCOp:$cond, IntRegs:$rs1, simm5Op:$simm5),
33 !strconcat(OpcStr, "$cond $rs1, $simm5, $imm10")>;
72 def : Pat<(f32 (any_fma f32:$rs1, f32:$rs2, f32:$add)), (FMADDS $rs1, $rs2, $add)>;
73 def : Pat<(f64 (any_fma f64:$rs1, f64:$rs2, f64:$add)), (FMADDD $rs1, $rs2, $add)>;
74 def : Pat<(f32 (any_fma f32:$rs1, f32:$rs2, (fneg f32:$sub))), (FMSUBS $rs1, $rs2, $sub)>;
[all …]
H A DSparcInstrAliases.td62 // movr<cond> rs1, rs2, rd
68 // movr<cond> $rs1, $rs2, $rd
69 def : InstAlias<!strconcat(!strconcat("movr", rcond), " $rs1, $rs2, $rd"),
70 (movrrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, condVal)>;
72 // movr<cond> $rs1, $simm10, $rd
73 def : InstAlias<!strconcat(!strconcat("movr", rcond), " $rs1, $simm10, $rd"),
74 (movrri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, condVal)>;
76 // fmovrs<cond> $rs1, $rs2, $rd
77 def : InstAlias<!strconcat(!strconcat("fmovrs", rcond), " $rs1, $rs2, $rd"),
78 (fmovrs FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, condVal)>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfoF2.td299 def : Pat<(brcond (i32 (setcc FPR32Op:$rs1, FPR32Op:$rs2, CC)), bb:$imm16),
300 (Br0 (!cast<Instruction>(Instr#_S) FPR32Op:$rs1, FPR32Op:$rs2), bb:$imm16)>;
302 def : Pat<(brcond (xor (i32 (setcc FPR32Op:$rs1, FPR32Op:$rs2, CC)), 1), bb:$imm16),
303 (Br1 (!cast<Instruction>(Instr#_S) FPR32Op:$rs1, FPR32Op:$rs2), bb:$imm16)>;
305 def : Pat<(brcond (i32 (setcc FPR64Op:$rs1, FPR64Op:$rs2, CC)), bb:$imm16),
306 (Br0 (!cast<Instruction>(Instr#_D) FPR64Op:$rs1, FPR64Op:$rs2), bb:$imm16)>;
308 def : Pat<(brcond (xor (i32 (setcc FPR64Op:$rs1, FPR64Op:$rs2, CC)), 1), bb:$imm16),
309 (Br1 (!cast<Instruction>(Instr#_D) FPR64Op:$rs1, FPR64Op:$rs2), bb:$imm16)>;
312 def : Pat<(i32 (setcc FPR32Op:$rs1, FPR32Op:$rs2, CC)),
313 (MV (!cast<Instruction>(Instr#_S) FPR32Op:$rs1, FPR32O
[all...]
H A DCSKYInstrInfoF1.td308 def : Pat<(f64(CSKY_BITCAST_FROM_LOHI GPR:$rs1, GPR:$rs2)), (FMTVRH_D(FMTVRL_D GPR:$rs1), GPR:$rs2)>,
313 def : Pat<(brcond (i32 (setcc sFPR32Op:$rs1, sFPR32Op:$rs2, CC)), bb:$imm16),
314 (Br0 (!cast<Instruction>(Instr#_S) sFPR32Op:$rs1, sFPR32Op:$rs2), bb:$imm16)>;
316 def : Pat<(brcond (xor (i32 (setcc sFPR32Op:$rs1, sFPR32Op:$rs2, CC)), 1), bb:$imm16),
317 (Br1 (!cast<Instruction>(Instr#_S) sFPR32Op:$rs1, sFPR32Op:$rs2), bb:$imm16)>;
319 def : Pat<(brcond (i32 (setcc sFPR64Op:$rs1, sFPR64Op:$rs2, CC)), bb:$imm16),
320 (Br0 (!cast<Instruction>(Instr#_D) sFPR64Op:$rs1, sFPR64Op:$rs2), bb:$imm16)>;
322 def : Pat<(brcond (xor (i32 (setcc sFPR64Op:$rs1, sFPR64Op:$rs2, CC)), 1), bb:$imm16),
323 (Br1 (!cast<Instruction>(Instr#_D) sFPR64Op:$rs1, sFPR64O
[all...]

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