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Searched refs:pipelined (Results 1 – 19 of 19) sorted by relevance

/freebsd/libexec/phttpget/
H A Dphttpget.c308 int pipelined = 0; /* != 0 if connection in pipelined mode. */ in main() local
393 if (pipelined) { in main()
400 while ((nreq < argc) && ((reqbuf == NULL) || pipelined)) { in main()
409 if (pipelined) { in main()
430 if (pipelined) { in main()
484 pipelined = 1; in main()
514 pipelined = 0; in main()
662 pipelined = 0; in main()
688 if (pipelined == 0 && keepalive == 0) in main()
720 pipelined = 0; in main()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSchedRocket.td169 // FP division unit on Rocket is not pipelined, so set resource cycles to latency.
175 // FP square root unit on Rocket is not pipelined, so set resource cycles to latency.
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleR52.td14 // The Cortex-R52 is an in-order pipelined superscalar microprocessor with
16 // There are two ALUs, one LDST, one MUL and a non-pipelined integer DIV.
75 let Latency = 8; let ReleaseAtCycles = [8]; // non-pipelined
110 let ReleaseAtCycles = [7]; // is not pipelined
148 let Latency = 8; let ReleaseAtCycles = [8]; // not pipelined
H A DARMScheduleM4.td16 let LoadLatency = 2; // Latency when not pipelined, not pc-relative
H A DARMSchedule.td51 // // cycle because these resources happen to be pipelined.
H A DARMFeatures.td344 // True if VFP instructions are not pipelined.
347 "VFP instructions are not pipelined">;
H A DARMScheduleSwift.td33 // FIXME: Model the pipelined behavior of CMP / TST instructions.
37 // FIXME: Model non-pipelined nature of FP div / sqrt unit.
H A DARMScheduleA8.td27 // Two fully-pipelined integer ALU pipelines
H A DARMScheduleA9.td41 // Two fully-pipelined integer ALU pipelines
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCScheduleE500.td25 // 6 pipelined execution units: SU0, SU1, BU, LSU, MU.
H A DPPCScheduleE500mc.td25 // 6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX.
H A DPPCScheduleE5500.td26 // 6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX.
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Dmvebu-devbus.txt48 synchronous pipelined devices, where the address
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetItinerary.td42 // Instruction stage - These values represent a non-pipelined step in
H A DTargetSchedule.td293 // cycle, regardless of latency, which models a fully pipelined processing
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedA55.td46 def CortexA55UnitDiv : ProcResource<1> { let BufferSize = 0; } // Int Division, not pipelined
187 // FP Mul, Div, Sqrt. Div/Sqrt are not pipelined
H A DAArch64SchedA510.td46 def CortexA510UnitDiv : ProcResource<1>; // Int Division, not pipelined
200 // FP Mul, Div, Sqrt. Div/Sqrt are not pipelined
/freebsd/contrib/unbound/doc/
H A DChangelog3586 pipelined response between mesh send and callback end, this fixes
3604 - Fix double file close in tcp pipelined response code.
3607 - Fix that spoolbuf is not used to store tcp pipelined response
/freebsd/contrib/one-true-awk/testdir/
H A Dfunstack.in17157 …: (1) performing global query optimization, (2) exploiting disjoint and pipelined concurrency, (3)…
17163 …obal query optimisation; inverted; manipulation language; optimisation; pipelined concurrency; pro…