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/freebsd/contrib/llvm-project/llvm/tools/llvm-objdump/
H A DMachODump.cpp228 dumpBytes(ArrayRef(bytes, 4), outs()); in DumpDataInCode()
230 outs() << "\t.long " << Value; in DumpDataInCode()
234 dumpBytes(ArrayRef(bytes, 2), outs()); in DumpDataInCode()
236 outs() << "\t.short " << Value; in DumpDataInCode()
240 dumpBytes(ArrayRef(bytes, 2), outs()); in DumpDataInCode()
242 outs() << "\t.byte " << Value; in DumpDataInCode()
246 outs() << "\t@ KIND_DATA\n"; in DumpDataInCode()
248 outs() << "\t@ data in code kind = " << Kind << "\n"; in DumpDataInCode()
252 dumpBytes(ArrayRef(bytes, 1), outs()); in DumpDataInCode()
254 outs() << "\t.byte " << format("%3u", Value) << "\t@ KIND_JUMP_TABLE8\n"; in DumpDataInCode()
[all …]
H A DCOFFDump.cpp93 outs() << "\t(" << I.Name << ')'; in printOptionalEnumName()
101 outs() << format("%-23s ", K) << format(Fmt, V); in printPEHeader()
108 outs() << format("%-23s ", K) << formatAddr(V) << '\n'; in printPEHeader()
113 outs() << '\n'; in printPEHeader()
138 outs() << '\n'; in printPEHeader()
143 outs() << "\t\t\t\t\t" << #Name << '\n'; in printPEHeader()
182 outs() << "\nThe Data Directory\n"; in printPEHeader()
189 outs() << format("Entry %x ", I) << formatAddr(Addr) in printPEHeader()
262 outs() << format(" 0x%02x: ", unsigned(UCs[0].u.CodeOffset)) in printUnwindCode()
266 outs() << " " << getUnwindRegisterName(UCs[0].getOpInfo()); in printUnwindCode()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrConv.td15 defm I32_WRAP_I64 : I<(outs I32:$dst), (ins I64:$src), (outs), (ins),
19 defm I64_EXTEND_S_I32 : I<(outs I64:$dst), (ins I32:$src), (outs), (ins),
23 defm I64_EXTEND_U_I32 : I<(outs I64:$dst), (ins I32:$src), (outs), (ins),
29 defm I32_EXTEND8_S_I32 : I<(outs I32:$dst), (ins I32:$src), (outs), (ins),
33 defm I32_EXTEND16_S_I32 : I<(outs I32:$dst), (ins I32:$src), (outs), (ins),
37 defm I64_EXTEND8_S_I64 : I<(outs I64:$dst), (ins I64:$src), (outs), (ins),
41 defm I64_EXTEND16_S_I64 : I<(outs I64:$dst), (ins I64:$src), (outs), (ins),
45 defm I64_EXTEND32_S_I64 : I<(outs I64:$dst), (ins I64:$src), (outs), (ins),
58 defm I32_TRUNC_S_SAT_F32 : I<(outs I32:$dst), (ins F32:$src), (outs), (ins),
63 defm I32_TRUNC_U_SAT_F32 : I<(outs I32:$dst), (ins F32:$src), (outs), (ins),
[all …]
H A DWebAssemblyInstrControl.td16 defm BR_IF : I<(outs), (ins bb_op:$dst, I32:$cond),
17 (outs), (ins bb_op:$dst),
21 defm BR_UNLESS : I<(outs), (ins bb_op:$dst, I32:$cond),
22 (outs), (ins bb_op:$dst), []>;
24 defm BR : NRI<(outs), (ins bb_op:$dst),
50 defm BR_TABLE_I32 : I<(outs), (ins I32:$index, variable_ops),
51 (outs), (ins brlist:$brl),
58 defm BR_TABLE_I64 : I<(outs), (ins I64:$index, variable_ops),
59 (outs), (ins brlist:$brl),
67 defm NOP : NRI<(outs), (ins), [], "nop", 0x01>;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430InstrFormats.td32 class MSP430Inst<dag outs, dag ins, int size, string asmstr> : Instruction {
38 dag OutOperandList = outs;
47 dag outs, dag ins, string asmstr, list<dag> pattern>
48 : MSP430Inst<outs, ins, size, asmstr> {
64 dag outs, dag ins, string asmstr, list<dag> pattern>
65 : IForm<opcode, dest, 1, src, size, outs, ins, asmstr, pattern>;
68 dag outs, dag ins, string asmstr, list<dag> pattern>
69 : IForm8<opcode, DstReg, SrcReg, 2, outs, ins, asmstr, pattern> {
74 dag outs, dag ins, string asmstr, list<dag> pattern>
75 : IForm8<opcode, DstReg, SrcImm, 4, outs, ins, asmstr, pattern> {
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrSPE.td132 def BRINC : EVXForm_1<527, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
136 def EFDABS : EFXForm_2<740, (outs sperc:$RT), (ins sperc:$RA),
140 def EFDADD : EFXForm_1<736, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
144 def EFDCFS : EFXForm_2a<751, (outs sperc:$RT), (ins spe4rc:$RB),
148 def EFDCFSF : EFXForm_2a<755, (outs sperc:$RT), (ins spe4rc:$RB),
151 def EFDCFSI : EFXForm_2a<753, (outs sperc:$RT), (ins gprc:$RB),
155 def EFDCFSID : EFXForm_2a<739, (outs sperc:$RT), (ins gprc:$RB),
159 def EFDCFUF : EFXForm_2a<754, (outs sperc:$RT), (ins spe4rc:$RB),
162 def EFDCFUI : EFXForm_2a<752, (outs sperc:$RT), (ins gprc:$RB),
166 def EFDCFUID : EFXForm_2a<738, (outs sperc:$RT), (ins gprc:$RB),
[all …]
H A DPPCInstrDFP.td19 defm DADD : XForm_28r<59, 2, (outs f8rc:$RST), (ins f8rc:$RA, f8rc:$RB),
22 defm DADDQ : XForm_28r<63, 2, (outs fpairrc:$RST), (ins fpairrc:$RA, fpairrc:$RB),
26 defm DSUB : XForm_28r<59, 514, (outs f8rc:$RST), (ins f8rc:$RA, f8rc:$RB),
29 defm DSUBQ : XForm_28r<63, 514, (outs fpairrc:$RST), (ins fpairrc:$RA, fpairrc:$RB),
33 defm DMUL : XForm_28r<59, 34, (outs f8rc:$RST), (ins f8rc:$RA, f8rc:$RB),
36 defm DMULQ : XForm_28r<63, 34, (outs fpairrc:$RST), (ins fpairrc:$RA, fpairrc:$RB),
40 defm DDIV : XForm_28r<59, 546, (outs f8rc:$RST), (ins f8rc:$RA, f8rc:$RB),
43 defm DDIVQ : XForm_28r<63, 546, (outs fpairrc:$RST), (ins fpairrc:$RA, fpairrc:$RB),
47 def DCMPU : XForm_17<59, 642, (outs crrc:$BF), (ins f8rc:$RA, f8rc:$RB),
50 def DCMPUQ : XForm_17<63, 642, (outs crrc:$BF), (ins fpairrc:$RA, fpairrc:$RB),
[all …]
H A DPPCInstr64Bit.td78 def BLR8 : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
82 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
85 def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins (pred $BIBO, $CR):$cond),
90 def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$BI),
93 def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$BI),
100 def MovePCtoLR8 : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR8", []>,
105 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$BD),
107 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$BD),
112 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
114 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreInstrFormats.td12 class InstXCore<int sz, dag outs, dag ins, string asmstr, list<dag> pattern>
17 dag OutOperandList = outs;
26 class PseudoInstXCore<dag outs, dag ins, string asmstr, list<dag> pattern>
27 : InstXCore<0, outs, ins, asmstr, pattern> {
35 class _F3R<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
36 : InstXCore<2, outs, ins, asmstr, pattern> {
44 class _F3RImm<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
45 : _F3R<opc, outs, ins, asmstr, pattern> {
49 class _FL3R<bits<9> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
50 : InstXCore<4, outs, ins, asmstr, pattern> {
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrSystem.td17 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", []>, TB;
20 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
25 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
27 def UD1Wm : I<0xB9, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
29 def UD1Lm : I<0xB9, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
31 def UD1Qm : RI<0xB9, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
34 def UD1Wr : I<0xB9, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
36 def UD1Lr : I<0xB9, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
38 def UD1Qr : RI<0xB9, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
43 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
[all …]
H A DX86InstrFPStack.td19 def FP32_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP32:$src),
21 def FP32_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP32:$src),
23 def FP32_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP32:$src),
25 def FP64_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP64:$src),
27 def FP64_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP64:$src),
29 def FP64_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP64:$src),
31 def FP80_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP80:$src),
33 def FP80_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP80:$src),
35 def FP80_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP80:$src),
38 def FP80_ADDr : PseudoI<(outs RFP8
[all...]
H A DX86InstrControl.td23 def RET32 : I <0xC3, RawFrm, (outs), (ins variable_ops),
25 def RET64 : I <0xC3, RawFrm, (outs), (ins variable_ops),
27 def RET16 : I <0xC3, RawFrm, (outs), (ins),
29 def RETI32 : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
31 def RETI64 : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
33 def RETI16 : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt),
35 def LRET32 : I <0xCB, RawFrm, (outs), (ins),
37 def LRET64 : RI <0xCB, RawFrm, (outs), (ins),
39 def LRET16 : I <0xCB, RawFrm, (outs), (ins),
41 def LRETI32 : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
[all …]
H A DX86InstrAMX.td21 def LDTILECFG#Suffix : I<0x49, MRM0m, (outs), (ins opaquemem:$src),
26 def STTILECFG#Suffix : I<0x49, MRM0m, (outs), (ins opaquemem:$src),
31 def TILELOADD#Suffix : I<0x4b, MRMSrcMemFSIB, (outs TILE:$dst),
36 def TILELOADDT1#Suffix : I<0x4b, MRMSrcMemFSIB, (outs TILE:$dst),
41 def TILESTORED#Suffix : I<0x4b, MRMDestMemFSIB, (outs),
54 def TILERELEASE : I<0x49, MRM_C0, (outs), (ins),
56 def TILEZERO : I<0x49, MRMr0, (outs TILE:$dst), (ins),
63 def PLDTILECFGV : PseudoI<(outs), (ins opaquemem:$src), []>;
65 def PTILELOADDV : PseudoI<(outs TILE:$dst), (ins GR16:$src1,
69 def PTILELOADDT1V : PseudoI<(outs TILE:$dst), (ins GR16:$src1,
[all …]
H A DX86InstrMisc.td19 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>;
20 def NOOPW : I<0x1f, MRMXm, (outs), (ins i16mem:$zero),
22 def NOOPL : I<0x1f, MRMXm, (outs), (ins i32mem:$zero),
24 def NOOPQ : RI<0x1f, MRMXm, (outs), (ins i64mem:$zero),
27 def NOOPWr : I<0x1f, MRMXr, (outs), (ins GR16:$zero),
29 def NOOPLr : I<0x1f, MRMXr, (outs), (ins GR32:$zero),
31 def NOOPQr : RI<0x1f, MRMXr, (outs), (ins GR64:$zero),
37 def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl),
42 def LEAVE : I<0xC9, RawFrm, (outs), (ins), "leave", []>,
46 def LEAVE64 : I<0xC9, RawFrm, (outs), (ins), "leave", []>,
[all …]
H A DX86InstrShiftRotate.td347 : ITy<o, MRMDestReg, t, (outs t.RegClass:$dst),
359 : BinOpRR<o, m, !if(!eq(ndd, 0), triop_cl_args, triop_cl_ndd_args), t, (outs t.RegClass:$dst), []>, NDD<ndd> {
368 : ITy<o, MRMDestMem, t, (outs), (ins t.MemOperand:$src1, t.RegClass:$src2, u8imm:$src3),
380 : BinOpMR<o, m, triop_cl_args, t, (outs), []>, TB {
390 : ITy<o, MRMDestMem, t, (outs t.RegClass:$dst), (ins t.MemOperand:$src1, t.RegClass:$src2, u8imm:$src3),
401 : BinOpMR<o, m, triop_cl_ndd_args, t, (outs t.RegClass:$dst), []>, NDD<1> {
510 def SHLDROT32ri : I<0, Pseudo, (outs GR32:$dst),
513 def SHLDROT64ri : I<0, Pseudo, (outs GR64:$dst),
517 def SHRDROT32ri : I<0, Pseudo, (outs GR32:$dst),
520 def SHRDROT64ri : I<0, Pseudo, (outs GR6
[all...]
/freebsd/contrib/llvm-project/llvm/tools/bugpoint/
H A DFindBugs.cpp25 outs() << "Starting bug finding procedure...\n\n"; in runManyPasses()
31 outs() << "\n"; in runManyPasses()
33 outs() << "Generating reference output from raw program: \n"; in runManyPasses()
49 outs() << "Running selected passes on program to test for crash: "; in runManyPasses()
51 outs() << "-" << Pass << " "; in runManyPasses()
55 outs() << "\n"; in runManyPasses()
56 outs() << "Optimizer passes caused failure!\n\n"; in runManyPasses()
59 outs() << "Combination " << num << " optimized successfully!\n"; in runManyPasses()
65 outs() << "Running the code generator to test for a crash: "; in runManyPasses()
67 outs() << "\n*** compileProgram threw an exception: "; in runManyPasses()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVInstrInfo.td18 def ASSIGN_TYPE: Pseudo<(outs ID:$dst_id), (ins ID:$src_id, TYPE:$src_ty)>;
22 : UnknownOp<(outs TYPE:$type), (ins i32imm:$opcode, variable_ops), " ">;
31 : Op<opCode, (outs ID:$dst), (ins TYPE:$src_ty, ID:$src, ID:$src2),
35 : Op<opCode, (outs CID:$dst), (ins TYPE:$src_ty, CID:$src, CID:$src2),
40 : Op<opCode, (outs CID:$dst), (ins TYPE:$src_ty, CCond:$cond, CID:$src1, CID:$src2),
87 : Op<opCode, (outs ID:$dst), (ins TYPE:$type, ID:$src),
90 : Op<opCode, (outs CID:$dst), (ins TYPE:$src_ty, CID:$src),
93 class SimpleOp<string name, bits<16> opCode>: Op<opCode, (outs), (ins), name>;
98 def OpUndef: Op<1, (outs ID:$res), (ins TYPE:$type), "$res = OpUndef $type">;
99 def OpSizeOf: Op<321, (outs ID:$res), (ins TYPE:$ty, ID:$ptr), "$res = OpSizeOf $ty $ptr">;
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchLASXInstrFormats.td21 class Fmt1RI13_XI<bits<32> op, dag outs, dag ins, string opnstr,
23 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {
34 class Fmt2R_XX<bits<32> op, dag outs, dag ins, string opnstr,
36 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {
46 class Fmt2R_XR<bits<32> op, dag outs, dag ins, string opnstr,
48 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {
58 class Fmt2R_CX<bits<32> op, dag outs, dag ins, string opnstr,
60 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {
71 class Fmt2RI1_XXI<bits<32> op, dag outs, dag ins, string opnstr,
73 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {
[all …]
H A DLoongArchLSXInstrFormats.td21 class Fmt1RI13_VI<bits<32> op, dag outs, dag ins, string opnstr,
23 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {
34 class Fmt2R_VV<bits<32> op, dag outs, dag ins, string opnstr,
36 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {
46 class Fmt2R_VR<bits<32> op, dag outs, dag ins, string opnstr,
48 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {
58 class Fmt2R_CV<bits<32> op, dag outs, dag ins, string opnstr,
60 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {
71 class Fmt2RI1_VVI<bits<32> op, dag outs, dag ins, string opnstr,
73 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {
[all …]
H A DLoongArchInstrFormats.td19 class LAInst<dag outs, dag ins, string opcstr, string opnstr,
31 let OutOperandList = outs;
46 class Pseudo<dag outs, dag ins, list<dag> pattern = [], string opcstr = "",
48 : LAInst<outs, ins, opcstr, opnstr, pattern> {
59 class Fmt2R<bits<32> op, dag outs, dag ins, string opnstr,
61 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {
72 class Fmt3R<bits<32> op, dag outs, dag ins, string opnstr,
74 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {
87 class Fmt3RI2<bits<32> op, dag outs, dag ins, string opnstr,
89 : LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcInstrFormats.td9 class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern,
20 dag OutOperandList = outs;
36 class F2<dag outs, dag ins, string asmstr, list<dag> pattern,
38 : InstSP<outs, ins, asmstr, pattern, itin> {
48 class F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern,
50 : F2<outs, ins, asmstr, pattern, itin> {
58 class F2_2<bits<3> op2Val, bit annul, dag outs, dag ins, string asmstr,
60 : F2<outs, ins, asmstr, pattern, itin> {
69 dag outs, dag ins, string asmstr, list<dag> pattern,
71 : InstSP<outs, ins, asmstr, pattern, itin> {
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrFormatsF2.td13 class CSKYInstF2<AddrMode am, dag outs, dag ins, string opcodestr,
15 : CSKY32Inst<am, 0x3d, outs, ins, opcodestr, pattern> {
20 class F2_XYZ<bits<5> datatype, bits<6> sop, string opcodestr, dag outs, dag ins,
22 : CSKYInstF2<AddrModeNone, outs, ins, opcodestr, pattern> {
36 (outs FPR32Op:$vrz), (ins FPR32Op:$vrx, FPR32Op:$vry),
40 (outs FPR64Op:$vrz), (ins FPR64Op:$vrx, FPR64Op:$vry),
47 (outs FPR32Op:$vrz), (ins FPR32Op:$vrZ, FPR32Op:$vrx, FPR32Op:$vry),
51 (outs FPR64Op:$vrz), (ins FPR64Op:$vrZ, FPR64Op:$vrx, FPR64Op:$vry),
58 (outs regtype:$vrz), (ins regtype:$vrx),
63 (outs regtype:$vrz), (ins regtype:$vrx),
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DGenericOpcodes.td45 let OutOperandList = (outs type0:$dst);
53 let OutOperandList = (outs type0:$dst);
67 let OutOperandList = (outs type0:$dst);
75 let OutOperandList = (outs type0:$dst);
84 let OutOperandList = (outs type0:$dst);
91 let OutOperandList = (outs type0:$dst);
98 let OutOperandList = (outs type0:$dst);
105 let OutOperandList = (outs type0:$dst);
111 let OutOperandList = (outs type0:$dst);
117 let OutOperandList = (outs type0:$dst);
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaInstrFormats.td12 class XtensaInst<int size, dag outs, dag ins, string asmstr, list<dag> pattern,
19 let OutOperandList = outs;
29 class XtensaInst24<dag outs, dag ins, string asmstr, list<dag> pattern,
31 : XtensaInst<3, outs, ins, asmstr, pattern, itin> {
37 class XtensaInst16<dag outs, dag ins, string asmstr, list<dag> pattern,
39 : XtensaInst<2, outs, ins, asmstr, pattern, itin> {
45 class RRR_Inst<bits<4> op0, bits<4> op1, bits<4> op2, dag outs, dag ins,
47 : XtensaInst24<outs, ins, asmstr, pattern, itin> {
60 class RRI4_Inst<bits<4> op0, bits<4> op1, dag outs, dag ins,
62 : XtensaInst24<outs, ins, asmstr, pattern, itin> {
[all …]
/freebsd/contrib/llvm-project/llvm/tools/llvm-size/
H A Dllvm-size.cpp220 outs() << "Segment " << Seg.segname << ": " in printDarwinSectionSizes()
223 outs() << " (vmaddr 0x" << format("%" PRIx64, Seg.vmaddr) << " fileoff " in printDarwinSectionSizes()
225 outs() << "\n"; in printDarwinSectionSizes()
231 outs() << "\tSection (" << format("%.16s", &Sec.segname) << ", " in printDarwinSectionSizes()
234 outs() << "\tSection " << format("%.16s", &Sec.sectname) << ": "; in printDarwinSectionSizes()
235 outs() << format(fmtbuf.c_str(), Sec.size); in printDarwinSectionSizes()
237 outs() << " (addr 0x" << format("%" PRIx64, Sec.addr) << " offset " in printDarwinSectionSizes()
239 outs() << "\n"; in printDarwinSectionSizes()
243 outs() << "\ttotal " << format(fmtbuf.c_str(), sec_total) << "\n"; in printDarwinSectionSizes()
247 outs() << "Segment " << Seg.segname << ": " in printDarwinSectionSizes()
[all …]

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