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Searched refs:operand (Results 1 – 25 of 274) sorted by relevance

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/freebsd/contrib/libpcap/
H A Dbpf_image.c135 const char *operand; in bpf_image() local
142 operand = operand_buf; in bpf_image()
148 operand = operand_buf; in bpf_image()
153 operand = ""; in bpf_image()
159 operand = operand_buf; in bpf_image()
165 operand = operand_buf; in bpf_image()
171 operand = operand_buf; in bpf_image()
176 operand = "#pktlen"; in bpf_image()
182 operand = operand_buf; in bpf_image()
188 operand = operand_buf; in bpf_image()
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/freebsd/sys/sys/
H A Dstdatomic.h266 #define atomic_fetch_add_explicit(object, operand, order) \ argument
267 __c11_atomic_fetch_add(object, operand, order)
268 #define atomic_fetch_sub_explicit(object, operand, order) \ argument
269 __c11_atomic_fetch_sub(object, operand, order)
270 #define atomic_fetch_or_explicit(object, operand, order) \ argument
271 __c11_atomic_fetch_or(object, operand, order)
272 #define atomic_fetch_xor_explicit(object, operand, order) \ argument
273 __c11_atomic_fetch_xor(object, operand, order)
274 #define atomic_fetch_and_explicit(object, operand, order) \ argument
275 __c11_atomic_fetch_and(object, operand, order)
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/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetMacroFusion.td48 // Tie firstOpIdx and secondOpIdx. The operand of `FirstMI` at position
49 // `firstOpIdx` should be the same as the operand of `SecondMI` at position
51 // If the fusion has `IsCommutable` being true and the operand at `secondOpIdx`
52 // has commutable operand, then the commutable operand will be checked too.
58 // The operand of `FirstMI` at position `firstOpIdx` should be the same as the
59 // operand at position `secondOpIdx`.
60 // If the fusion has `IsCommutable` being true and the operand at `secondOpIdx`
61 // has commutable operand, then the commutable operand will be checked too.
67 // The operand of `SecondMI` at position `firstOpIdx` should be the same as the
68 // operand at position `secondOpIdx`.
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H A DTargetInstrPredicate.td26 // whose opcode is BLR, and whose first operand is a register different from
90 // operands. It is used to reference a specific machine operand.
95 // Return true if machine operand at position `Index` is a register operand.
98 // Return true if machine operand at position `Index` is a virtual register operand.
101 // Return true if machine operand at position `Index` is not a virtual register operand.
104 // Return true if machine operand at position `Index` is an immediate operand
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H A DTarget.td304 // model instruction operand constraints, and should have isAllocatable = 0.
345 // The diagnostic type to present when referencing this operand in a match
348 // value will be generated and used for this operand type. The target
354 // register class when it is being used as an assembly operand. If this is
385 // numbered registers. Takes an optional 4th operand which is a stride to use
594 dag OutOperandList; // An dag containing the MI def operand list.
595 dag InOperandList; // An dag containing the MI use operand list.
609 list<Register> Uses = []; // Default to using no non-operand registers
610 list<Register> Defs = []; // Default to modifying no non-operand registers
646 bit canFoldAsLoad = false; // Can this be folded as a simple memory operand?
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/freebsd/contrib/llvm-project/clang/lib/Headers/
H A Dstdatomic.h156 #define atomic_fetch_add(object, operand) __c11_atomic_fetch_add(object, operand, __ATOMIC_SEQ_CST) argument
159 #define atomic_fetch_sub(object, operand) __c11_atomic_fetch_sub(object, operand, __ATOMIC_SEQ_CST) argument
162 #define atomic_fetch_or(object, operand) __c11_atomic_fetch_or(object, operand, __ATOMIC_SEQ_CST) argument
165 #define atomic_fetch_xor(object, operand) __c11_atomic_fetch_xor(object, operand, __ATOMIC_SEQ_CST) argument
168 #define atomic_fetch_and(object, operand) __c11_atomic_fetch_and(object, operand, __ATOMIC_SEQ_CST) argument
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrFormats.td50 /// Form without size qualifier will adapt to operand size automatically, e.g.:
82 (operand "$"#reg_opnd, 4),
94 (operand "$"#disp_opnd, 8, (encoder disp_encoder))
100 /*REGISTER*/(operand "$"#reg_opnd, 3));
105 /*REGISTER*/(operand "$"#reg_opnd, 3));
110 /*REGISTER with D/A bit*/(operand "$"#reg_opnd, 4));
127 let Supplement = (operand "$"#opnd_name, 16,
133 /*REGISTER*/(operand "$"#opnd_name#".reg", 3));
136 let Supplement = (operand "$"#opnd_name#".disp", 16,
142 /*REGISTER*/(operand "
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H A DM68kInstrInfo.td140 // operand from the destination data register and sets the condition
147 // M68k conditional moves. Operand 0 and operand 1 are the two values
148 // to select from. Operand 2 is the condition code, and operand 3 is the
149 // flag operand produced by a CMP or TEST instruction. It also writes a
153 // M68k conditional branches. Operand 0 is the chain operand, operand 1
154 // is the block to branch if condition is true, operand 2 is the
155 // condition code, and operand 3 is the flag operand produced by a CMP
159 // M68k SetCC. Operand 0 is condition code, and operand 1 is the CCR
160 // operand, usually produced by a CMP instruction.
232 // REGISTER DIRECT. The operand is in the data register specified by
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H A DM68kInstrAtomics.td53 (descend 0b0000000, (operand "$du", 3), 0b000, (operand "$dc", 3))
70 (descend 0b0000000, (operand "$du", 3), 0b000, (operand "$dc", 3))
87 (descend 0b0000000, (operand "$du", 3), 0b000, (operand "$dc", 3))
104 (descend 0b0000000, (operand "$du", 3), 0b000, (operand "$dc", 3))
H A DM68kInstrArithmetic.td74 CMD, (operand "$dst", 3),
77 !eq(SRC_TYPE.RLet, "r") : (descend 0b00, (operand "$opd", 4)),
78 !eq(SRC_TYPE.RLet, "d") : (descend 0b000, (operand "$opd", 3))
94 CMD, (operand "$opd", 3),
98 /*REGISTER*/(operand "$dst", 3));
108 (descend CMD, (operand "$dst", 3),
135 (descend CMD, (operand "$dst", 3),
155 /*REGISTER*/(operand "$dst", 3)),
171 (descend CMD, (operand "$opd", 3),
342 (operand "$dst", 3),
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H A DM68kInstrControl.td101 /*REGISTER prefixed with D/A bit*/(operand "$dst", 4));
190 (operand "$dst", 8, (encoder "encodePCRelImm<8>")), (ascend)>;
194 (operand "$dst", 16, (encoder "encodePCRelImm<16>"))>;
198 (operand "$dst", 32, (encoder "encodePCRelImm<32>"))>;
229 (operand "$dst", 8, (encoder "encodePCRelImm<8>")), (ascend)>;
232 (operand "$dst", 16, (encoder "encodePCRelImm<16>"))>;
235 (operand "$dst", 32, (encoder "encodePCRelImm<32>"),
261 (operand "$dst", 8, (encoder "encodePCRelImm<8>")), (ascend)>;
264 (operand "$dst", 16, (encoder "encodePCRelImm<16>"))>;
267 (operand "$dst", 32, (encoder "encodePCRelImm<32>"),
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/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreInstrFormats.td41 // 3R with first operand as an immediate. Used for TSETR where the first
42 // operand is treated as an immediate since it refers to a register number in
59 // L3R with first operand as both a source and a destination.
71 // 2RUS with bitp operand
88 // L2RUS with bitp operand
160 // 2R with first operand as an immediate. Used for TSETMR where the first
161 // operand is treated as an immediate since it refers to a register number in
168 // 2R with first operand as both a source and a destination.
187 // RUS with bitp operand
194 // RUS with first operand as both a source and a destination and a bitp second
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSDNodeProperties.td23 def SDNPHasChain : SDNodeProperty; // R/W chain operand and result
25 def SDNPInGlue : SDNodeProperty; // Read a flag operand
26 def SDNPOptInGlue : SDNodeProperty; // Optionally read a flag operand
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/GlobalISel/
H A DTarget.td42 // The function that determines whether the operand matches. It should be of
46 // on match failure, or a ComplexRendererFn that renders the operand in case
58 // The function renders the operand(s) of the matched instruction to
64 // references the source operand MI.getOperand(OpIdx). Otherwise,
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMRegisterInfo.td239 let DiagnosticString = "operand must be a register in range [r0, r15]";
256 let DiagnosticString = "operand must be a register in range [r0, r14]";
260 // certain operand slots, particularly as the destination. Primarily
268 let DiagnosticString = "operand must be a register in range [r0, r14]";
279 let DiagnosticString = "operand must be a register in range [r0, r14] or apsr_nzcv";
289 let DiagnosticString = "operand must be a register in range [r0, r12] or LR or PC";
302 let DiagnosticString = "operand must be a register in range [r0, r14] or zr";
310 let DiagnosticString = "operand must be a register in range [r0, r12] or r14 or zr";
319 let DiagnosticString = "operand must be a register sp";
347 "operand must be a register in the range [r0, r12], r14 or apsr_nzcv";
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZSchedule.td32 // ReadAdvances, used for the register operand next to a memory operand,
33 // modelling that the register operand is needed later than the address
H A DSystemZPatterns.td10 // in which the operand is sign-extended from 32 to 64 bits.
19 // in which the first operand has class CLS and which the second operand
41 // of the second operand.
49 // memory location. IMM is the type of the second operand.
57 // The inserted operand is loaded using LOAD from an address of mode MODE.
124 // The other operand is a load of type LOAD, which accesses LENGTH bytes.
H A DSystemZOperands.td41 // Constructs both a DAG pattern and instruction operand for an immediate
43 // the operand value associated with the node. ASMOP is the name of the
44 // associated asm operand, and also forms the basis of the asm print method.
54 // Constructs an asm operand for a PC-relative address. SIZE says how
66 // Constructs an operand for a PC-relative address with address type VT.
67 // ASMOP is the associated asm operand.
79 // Constructs both a DAG pattern and instruction operand for a PC-relative
80 // address with address size VT. SELF is the name of the operand and
81 // ASMOP is the associated asm operand.
101 // Constructs an instruction operand for an addressing mode. FORMAT,
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/freebsd/contrib/llvm-project/clang/include/clang/CIR/Dialect/IR/
H A DCIROps.td232 Given a base pointer as first operand, provides a new pointer after applying
233 a stride (second operand).
431 `cir.store` stores a value (first operand) to the memory address specified
432 in the second operand. A unit attribute `volatile` can be used to indicate
471 The operation takes an optional operand and produces no results.
472 The operand type must match the signature of the function that contains
483 // The return operation takes an optional input operand to return. This
490 // Allow building a ReturnOp with no return operand.
514 conditionally executing two regions of code. The operand is a `cir.bool`
566 `cir.bool` operand and, depending on its value, may branch to different
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/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsRISCV.td65 // Signed min and max need an extra operand to do sign extension with.
130 // The intrinsic does not have any operand that must be extended.
133 // The intrinsic does not have a VL operand.
139 // operand, so they have to be extended.
216 // For strided load with passthru operand
236 // For indexed load with passthru operand
421 // second operand is XLen.
431 // Second operand is XLen.
498 // second source operand must match the destination type or be an XLen scalar.
508 // The second source operand must match the destination type or be an XLen scalar.
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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchLBTInstrFormats.td13 // rd/sd - destination register operand.
14 // rj/rk/sj - source register operand.
15 // immN/ptr - immediate data operand.
18 // output operand. In other words, there will be no output operand in the
/freebsd/contrib/llvm-project/lldb/source/Plugins/Disassembler/LLVMC/
H A DDisassemblerLLVMC.cpp1111 Operand operand; in ParseOperands() local
1114 if ((std::tie(operand, iter) = ParseIntelIndexedAccess(osi, ose), in ParseOperands()
1115 operand.IsValid()) || in ParseOperands()
1116 (std::tie(operand, iter) = ParseIntelDerefAccess(osi, ose), in ParseOperands()
1117 operand.IsValid()) || in ParseOperands()
1118 (std::tie(operand, iter) = ParseARMOffsetAccess(osi, ose), in ParseOperands()
1119 operand.IsValid()) || in ParseOperands()
1120 (std::tie(operand, iter) = ParseARMDerefAccess(osi, ose), in ParseOperands()
1121 operand.IsValid()) || in ParseOperands()
1122 (std::tie(operand, iter) = ParseRegisterName(osi, ose), in ParseOperands()
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/freebsd/contrib/llvm-project/clang/lib/CIR/CodeGen/
H A DCIRGenBuilder.h357 mlir::Value createComplexReal(mlir::Location loc, mlir::Value operand) { in createComplexReal() argument
358 auto operandTy = mlir::cast<cir::ComplexType>(operand.getType()); in createComplexReal()
359 return create<cir::ComplexRealOp>(loc, operandTy.getElementType(), operand); in createComplexReal()
362 mlir::Value createComplexImag(mlir::Location loc, mlir::Value operand) { in createComplexImag() argument
363 auto operandTy = mlir::cast<cir::ComplexType>(operand.getType()); in createComplexImag()
364 return create<cir::ComplexImagOp>(loc, operandTy.getElementType(), operand); in createComplexImag()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrFormats.td143 class I_16_J_XI<bits<5> sop, string op, Operand operand, list<dag> pattern>
145 (ins GPR:$rx, operand:$imm2),
170 class I_16_X<bits<5> sop, string op, Operand operand>
172 (ins GPR:$rx, operand:$imm16), !strconcat(op, "\t$rx, $imm16"), []> {
183 class I_16_X_L<bits<5> sop, string op, Operand operand>
184 : CSKY32Inst<AddrModeNone, 0x3a, (outs), (ins GPR:$rx, operand:$imm16),
238 class I_LD<AddrMode am, bits<4> sop, string op, Operand operand>
240 (outs GPR:$rz), (ins GPR:$rx, operand:$imm12), op, []>;
244 class I_ST<AddrMode am, bits<4> sop, string op, Operand operand>
246 (ins GPR:$rz, GPR:$rx, operand:$imm12), op, []>;
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/freebsd/contrib/llvm-project/llvm/include/llvm/Support/
H A DTargetOpcodes.def60 /// where an undef operand must be allocated to a different register than an
61 /// early-clobber result operand.
65 /// The result of this instruction is the value of the second operand inserted
66 /// into the subregister specified by the third operand. All other bits are
68 /// first operand. This instruction just communicates information; No code
104 // In SDNode form, the first operand encodes the register class created by
106 // pair. Once it has been lowered to a MachineInstr, the regclass operand
180 /// size or be preceded with a nop of that size. The first operand is
225 /// Represents a use of the operand but generates no code.
478 /// Generic instruction to truncate a signed operand to a signed result with saturation.
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