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Searched refs:opc1 (Results 1 – 7 of 7) sorted by relevance

/freebsd/contrib/llvm-project/clang/lib/Headers/
H A Darm_acle.h779 #define __arm_cdp(coproc, opc1, CRd, CRn, CRm, opc2) \ argument
780 __builtin_arm_cdp(coproc, opc1, CRd, CRn, CRm, opc2)
786 #define __arm_mcr(coproc, opc1, value, CRn, CRm, opc2) \ argument
787 __builtin_arm_mcr(coproc, opc1, value, CRn, CRm, opc2)
788 #define __arm_mrc(coproc, opc1, CRn, CRm, opc2) \ argument
789 __builtin_arm_mrc(coproc, opc1, CRn, CRm, opc2)
797 #define __arm_cdp(coproc, opc1, CRd, CRn, CRm, opc2) \ argument
798 __builtin_arm_cdp(coproc, opc1, CRd, CRn, CRm, opc2)
806 #define __arm_cdp2(coproc, opc1, CRd, CRn, CRm, opc2) \ argument
807 __builtin_arm_cdp2(coproc, opc1, CRd, CRn, CRm, opc2)
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrInfo.td4608 class SMLAL<bits<2> opc1, string asm>
4609 : AMulxyI64<0b0001010, opc1,
5389 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
5391 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
5392 [(int_arm_cdp timm:$cop, timm:$opc1, timm:$CRd, timm:$CRn,
5395 bits<4> opc1;
5408 let Inst{23-20} = opc1;
5413 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
5415 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
5416 [(int_arm_cdp2 timm:$cop, timm:$opc1, timm:$CRd, timm:$CRn,
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H A DARMInstrThumb2.td4605 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
4613 bits<3> opc1;
4620 let Inst{23-21} = opc1;
4630 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4638 bits<4> opc1;
4644 let Inst{7-4} = opc1;
4653 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4655 [(int_arm_mcr timm:$cop, timm:$opc1, GPR:$Rt, timm:$CRn,
4658 def : t2InstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4659 (t2MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
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/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.td208 multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> {
209 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
217 multiclass F3R_2RUS_np<bits<5> opc1, bits<5> opc2, string OpcStr> {
218 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
224 multiclass F3R_2RBITP<bits<5> opc1, bits<5> opc2, string OpcStr,
226 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
245 multiclass FL3R_L2RUS<bits<9> opc1, bits<9> opc2, string OpcStr,
247 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
256 multiclass FL3R_L2RBITP<bits<9> opc1, bits<9> opc2, string OpcStr,
258 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrFormats.td4807 class BaseMemTag<bits<2> opc1, bits<2> opc2, string asm_insn,
4814 let Inst{23-22} = opc1;
4847 class BaseMemTagStore<bits<2> opc1, bits<2> opc2, string asm_insn,
4849 : BaseMemTag<opc1, opc2, asm_insn, asm_opnds, cstr, oops, iops> {
4859 multiclass MemTagStore<bits<2> opc1, string insn> {
4861 BaseMemTagStore<opc1, 0b10, insn, "\t$Rt, [$Rn, $offset]", "",
4864 BaseMemTagStore<opc1, 0b11, insn, "\t$Rt, [$Rn, $offset]!",
4869 BaseMemTagStore<opc1, 0b01, insn, "\t$Rt, [$Rn], $offset",
11469 bit opc1, bit opc2, RegisterOperand dst_reg,
11495 let Inst{15} = opc1;
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp6196 unsigned opc1 = fieldFromInstruction(Val, 4, 4); in DecoderForMRRC2AndMCRR2() local
6224 Inst.addOperand(MCOperand::createImm(opc1)); in DecoderForMRRC2AndMCRR2()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrAVX512.td2945 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
2947 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode,
2950 defm B : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "b"), VK8, OpNode,