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Searched refs:op0 (Results 1 – 12 of 12) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaInstrFormats.td45 class RRR_Inst<bits<4> op0, bits<4> op1, bits<4> op2, dag outs, dag ins,
57 let Inst{3-0} = op0;
60 class RRI4_Inst<bits<4> op0, bits<4> op1, dag outs, dag ins,
73 let Inst{3-0} = op0;
76 class RRI8_Inst<bits<4> op0, dag outs, dag ins,
88 let Inst{3-0} = op0;
91 class RI16_Inst<bits<4> op0, dag outs, dag ins,
99 let Inst{3-0} = op0;
102 class RSR_Inst<bits<4> op0, bits<4> op1, bits<4> op2, dag outs, dag ins,
112 let Inst{3-0} = op0;
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/freebsd/sys/contrib/zstd/lib/decompress/
H A Dhuf_decompress_amd64.S49 #define op0 rsi macro
123 movq 32(%rax), %op0
326 movq %op0, 32(%rax)
377 movq 32(%rax), %op0
432 subq %op0, %rax /* rax = oend0 - op0 */
558 movq %op0, 32(%rax)
/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A Driscv_vector.td1409 // Unmasked: (passthru, op0, op1, round_mode, vl)
1424 Operands.push_back(Ops[Offset]); // op0
1458 // Unmasked: (passthru, op0, op1, round_mode, vl)
1473 Operands.push_back(Ops[Offset]); // op0
1513 // Unmasked: (passthru, op0, op1, round_mode, vl)
1532 Operands.push_back(Ops[Offset]); // op0
1590 // Unmasked: (passthru, op0, op1, round_mode, vl)
1609 Operands.push_back(Ops[Offset]); // op0
1664 // Unmasked: (passthru, op0, op1, round_mode, vl)
1674 Operands.push_back(Ops[Offset]); // op0
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H A Driscv_sifive_vector.td171 Operands.push_back(Ops[Offset]); // op0
/freebsd/sys/dev/mthca/
H A Dmthca_qp.c1630 u8 op0 = 0; in mthca_tavor_post_send() local
1778 op0 = mthca_opcode[wr->opcode]; in mthca_tavor_post_send()
1793 qp->send_wqe_offset) | f0 | op0, in mthca_tavor_post_send()
1945 u8 op0 = 0; in mthca_arbel_post_send() local
1958 ((qp->sq.head & 0xffff) << 8) | f0 | op0; in mthca_arbel_post_send()
2119 op0 = mthca_opcode[wr->opcode]; in mthca_arbel_post_send()
2131 dbhi = (nreq << 24) | ((qp->sq.head & 0xffff) << 8) | f0 | op0; in mthca_arbel_post_send()
/freebsd/sys/arm64/include/
H A Darmreg.h55 #define __MRS_REG(op0, op1, crn, crm, op2) \ argument
56 (((op0) << MRS_Op0_SHIFT) | ((op1) << MRS_Op1_SHIFT) | \
62 #define __MRS_REG_ALT_NAME(op0, op1, crn, crm, op2) \ argument
63 S##op0##_##op1##_C##crn##_C##crm##_##op2
64 #define _MRS_REG_ALT_NAME(op0, op1, crn, crm, op2) \ argument
65 __MRS_REG_ALT_NAME(op0, op1, crn, crm, op2)
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DSMEInstrFormats.td1816 class sme2_mla_long_array_index_base<bits<2> op0, bits<2> op, Operand index_ty,
1826 let Inst{23-22} = op0;
1837 multiclass sme2_mla_long_array_index<string mnemonic, bits<2> op0, bits<2> op, ValueType zpr_ty, SD…
1838 def _HtoS : sme2_mla_long_array_index_base<op0, op, uimm3s2range, ZPR16,
1854 class sme2_mla_long_array_vg2_index<string mnemonic, bits<2> op0, bits<2> op>
1855 : sme2_mla_long_array_index_base<op0, op, uimm2s2range, ZZ_h_mul_r,
1890 class sme2_mla_long_array_vg4_index<string mnemonic, bits<2> op0, bits<2> op>
1891 : sme2_mla_long_array_index_base<op0, op, uimm2s2range, ZZZZ_h_mul_r,
1926 class sme2_mla_long_array<bits<2>op0, bits<2> op,
1939 let Inst{23-22} = op0;
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H A DAArch64SystemOperands.td658 class SysReg<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm,
666 let Encoding{15-14} = op0;
676 class RWSysReg<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm,
678 : SysReg<name, op0, op1, crn, crm, op2> {
683 class ROSysReg<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm,
685 : SysReg<name, op0, op1, crn, crm, op2> {
690 class WOSysReg<string name, bits<2> op0, bits<3> op1, bits<4> crn, bits<4> crm,
692 : SysReg<name, op0, op1, crn, crm, op2> {
H A DAArch64InstrFormats.td1779 // concatenation of op0, op1, CRn, CRm, op2. 16-bit immediate.
11643 class CryptoRRTied<bits<1>op0, bits<2>op1, string asm, string asmops>
11649 let Inst{14} = op0;
11653 class CryptoRRTied_2D<bits<1>op0, bits<2>op1, string asm>
11654 : CryptoRRTied<op0, op1, asm, "{\t$Vd.2d, $Vn.2d|.2d\t$Vd, $Vn}">;
11655 class CryptoRRTied_4S<bits<1>op0, bits<2>op1, string asm>
11656 : CryptoRRTied<op0, op1, asm, "{\t$Vd.4s, $Vn.4s|.4s\t$Vd, $Vn}">;
11658 class CryptoRRR<bits<1> op0, bits<2>op1, dag oops, dag iops, string asm,
11665 let Inst{14} = op0;
11669 class CryptoRRR_2D<bits<1> op0, bits<2>op1, string asm>
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H A DAArch64InstrInfo.td6519 def trunc_optional_assert_ext : PatFrags<(ops node:$op0),
6520 [(trunc node:$op0),
6521 (assertzext (trunc node:$op0)),
6522 (assertsext (trunc node:$op0))]>;
10097 // MRRS <Xt>, <Xt+1>, <sysreg|S<op0>_<op1>_<Cn>_<Cm>_<op2>>
10098 // MSRR <sysreg|S<op0>_<op1>_<Cn>_<Cm>_<op2>>, <Xt>, <Xt+1>
/freebsd/sys/fs/nfsserver/
H A Dnfs_nfsdsocket.c712 int i, lktype, op, op0 = 0, rstat, statsinprog = 0; in nfsrvd_compound() local
900 op0 = op; in nfsrvd_compound()
931 else if (i != 0 && op0 != NFSV4OP_SEQUENCE) in nfsrvd_compound()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86IntrinsicsInfo.h93 #define X86_INTRINSIC_DATA(id, type, op0, op1) \ argument
94 { Intrinsic::x86_##id, type, op0, op1 }