| /freebsd/sys/contrib/device-tree/Bindings/mtd/ |
| H A D | marvell-nand.txt | 5 * "marvell,armada-8k-nand-controller"
6 * "marvell,armada370-nand-controller"
7 * "marvell,pxa3xx-nand-controller"
8 * "marvell,armada-8k-nand" (deprecated)
9 * "marvell,armada370-nand" (deprecated)
10 * "marvell,pxa3xx-nand" (deprecated)
23 "marvell,armada-8k-nand[-controller]" compatibles).
28 This property is only used with "marvell,pxa3xx-nand[-controller]"
31 This property is only used with "marvell,pxa3xx-nand[-controller]"
39 - nand-rb: see nand-controller.yaml (0-1).
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| H A D | samsung-s3c2410.txt | 5 "samsung,s3c2410-nand"
6 "samsung,s3c2412-nand"
7 "samsung,s3c2440-nand"
9 - #address-cells, #size-cells : see nand-controller.yaml
10 - clocks : phandle to the nand controller clock
11 - clock-names : must contain "nand"
14 Child nodes representing the available nand chips.
17 - nand-ecc-mode : see nand-controller.yaml
18 - nand-on-flash-bbt : see nand-controller.yaml
26 nand-controller@4e000000 {
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| H A D | nvidia-tegra20-nand.txt | 5 - "nvidia,tegra20-nand"
11 - nand
15 - nand
25 - nand-ecc-mode: String, operation mode of the NAND ecc mode. Currently only
27 - nand-ecc-algo: string, algorithm of NAND ECC.
29 - nand-bus-width : See nand-controller.yaml
30 - nand-on-flash-bbt: See nand-controller.yaml
31 - nand-ecc-strength: integer representing the number of bits to correct
36 - nand-ecc-maximize: See nand-controller.yaml
37 - nand-is-boot-medium: Makes sure only ECC strengths supported by the boot ROM
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| H A D | mxc-nand.txt | 4 - compatible: "fsl,imxXX-nand"
7 - nand-bus-width: see nand-controller.yaml
8 - nand-ecc-mode: see nand-controller.yaml
9 - nand-on-flash-bbt: see nand-controller.yaml
13 nand@d8000000 {
14 compatible = "fsl,imx27-nand";
17 nand-bus-width = <8>;
18 nand-ecc-mode = "hw";
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| H A D | vf610-nfc.txt | 10 - #address-cells: shall be set to 1. Encode the nand CS.
23 Children nodes represent the available nand chips. Currently the driver can
28 - nand-bus-width: see nand-controller.yaml
29 - nand-ecc-mode: see nand-controller.yaml
32 - nand-ecc-strength: supported strengths are 24 and 32 bit (see nand-controller.yaml)
33 - nand-ecc-step-size: step size equals page size, currently only 2k pages are
35 - nand-on-flash-bbt: see nand-controller.yaml
39 nfc: nand@400e0000 {
50 nand@0 {
53 nand-bus-width = <8>;
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| H A D | hisi504-nand.txt | 10 - nand-bus-width: See nand-controller.yaml.
11 - nand-ecc-mode: Support none and hw ecc mode.
17 - nand-ecc-strength: Number of bits to correct per ECC step.
18 - nand-ecc-step-size: Number of data bytes covered by a single ECC step.
22 - nand-ecc-strength = <16>, nand-ecc-step-size = <1024>
29 nand: nand@4020000 {
33 nand-bus-width = <8>;
34 nand-ecc-mode = "hw";
35 nand-ecc-strength = <16>;
36 nand-ecc-step-size = <1024>;
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| H A D | qcom_nandc.txt | 5 * "qcom,ipq806x-nand" - for EBI2 NAND controller being used in IPQ806x
7 * "qcom,ipq4019-nand" - for QPIC NAND controller v1.4.0 being used in
9 * "qcom,ipq6018-nand" - for QPIC NAND controller v1.5.0 being used in
11 * "qcom,ipq8074-nand" - for QPIC NAND controller v1.5.0 being used in
13 * "qcom,sdx55-nand" - for QPIC NAND controller v2.0.0 being used in
54 - nand-bus-width: see nand-controller.yaml
55 - nand-ecc-strength: see nand-controller.yaml. If not specified, then ECC strength will
65 nand-controller@1ac00000 {
66 compatible = "qcom,ipq806x-nand";
81 nand@0 {
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| H A D | brcm,brcmnand.txt | 39 ranges. Should contain "nand" and (optionally)
40 "flash-dma" or "flash-edu" and/or "nand-cache".
45 May be "nand", if the SoC has the individual NAND
53 - clock-names : "nand" (required for the above clock)
54 - brcm,nand-has-wp : Some versions of this IP include a write-protect
76 * "brcm,nand-bcm63138"
79 - reg-names: (required) "nand-int-base"
81 * "brcm,nand-bcm6368"
82 - compatible: should contain "brcm,nand-bcm<soc>", "brcm,nand-bcm6368"
85 - reg-names: (required) "nand-int-base"
[all …]
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| H A D | atmel-nand.txt | 12 "atmel,at91rm9200-nand-controller"
13 "atmel,at91sam9260-nand-controller"
14 "atmel,at91sam9261-nand-controller"
15 "atmel,at91sam9g45-nand-controller"
16 "atmel,sama5d3-nand-controller"
17 "microchip,sam9x60-nand-controller"
89 nand_controller: nand-controller {
90 compatible = "atmel,sama5d3-nand-controller";
98 nand@3 {
116 "atmel,at91rm9200-nand"
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| H A D | tango-nand.txt | 5 - compatible: "sigma,smp8758-nand"
14 See Documentation/devicetree/bindings/mtd/nand-controller.yaml for generic bindings.
18 nandc: nand-controller@2c000 {
19 compatible = "sigma,smp8758-nand";
27 nand@0 {
29 nand-ecc-strength = <14>;
30 nand-ecc-step-size = <1024>;
33 nand@1 {
35 nand-ecc-strength = <14>;
36 nand-ecc-step-size = <1024>;
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| H A D | mxic-nand.txt | 5 - compatible: should be "mxic,multi-itfc-v009-nand-controller"
17 See Documentation/devicetree/bindings/mtd/nand-controller.yaml
22 nand: nand-controller@43c30000 {
23 compatible = "mxic,multi-itfc-v009-nand-controller";
31 nand@0 {
33 nand-ecc-mode = "soft";
34 nand-ecc-algo = "bch";
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| H A D | oxnas-nand.txt | 3 Please refer to nand-controller.yaml for generic information regarding MTD NAND bindings.
6 - compatible: "oxsemi,ox820-nand"
15 nandc: nand-controller@41000000 {
16 compatible = "oxsemi,ox820-nand";
23 nand@0 {
27 nand-ecc-mode = "soft";
28 nand-ecc-algo = "hamming";
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| H A D | fsmc-nand.txt | 5 - compatible : "st,spear600-fsmc-nand", "stericsson,fsmc-nand"
12 - nand-skip-bbtscan: Indicates the BBT scanning should be skipped
33 - nand-ecc-mode : see nand-controller.yaml
34 - nand-ecc-strength : see nand-controller.yaml
35 - nand-ecc-step-size : see nand-controller.yaml
43 compatible = "st,spear600-fsmc-nand";
53 nand-skip-bbtscan;
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| H A D | davinci-nand.txt | 12 - compatible: "ti,davinci-nand"
13 "ti,keystone-nand"
22 for accessing the nand.
42 - nand-ecc-mode: operation mode of the NAND ecc mode. ECC mode
50 - nand-bus-width: buswidth 8 or 16. If not present 8.
52 - nand-on-flash-bbt: use flash based bad block table support. OOB
64 - ti,davinci-nand-buswidth: buswidth 8 or 16. If not present 8.
66 - ti,davinci-nand-use-bbt: use flash based bad block table support. OOB
79 compatible = "ti,davinci-nand";
86 nand-ecc-mode = "hw";
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| H A D | mtk-nand.txt | 5 the nand controller interface driver and the ECC engine driver.
48 - nand-on-flash-bbt: Store BBT on NAND Flash.
49 - nand-ecc-mode: the NAND ecc mode (check driver for supported modes)
50 - nand-ecc-step-size: Number of data bytes covered by a single ECC step.
55 - nand-ecc-strength: Number of bits to correct per ECC step.
65 E : nand-ecc-strength.
71 Q : nand-ecc-step-size.
124 nand@0 {
126 nand-on-flash-bbt;
127 nand-ecc-mode = "hw";
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| H A D | gpmi-nand.txt | 3 The GPMI nand controller provides an interface to control the
7 - compatible : should be "fsl,<chip>-gpmi-nand", chip can be:
14 - reg-names: Should contain the reg names "gpmi-nand" and "bch"
30 - nand-on-flash-bbt: boolean to enable on flash bbt option if not
44 'nand-on-flash-bbt'.
50 - nand-ecc-strength: integer representing the number of bits to correct
52 - nand-ecc-step-size: integer representing the number of data bytes
61 gpmi-nand@8000c000 {
62 compatible = "fsl,imx28-gpmi-nand";
66 reg-names = "gpmi-nand", "bch";
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| /freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | marvell,kirkwood-pinctrl.txt | 24 mpp0 0 gpio, nand(io2), spi(cs)
25 mpp1 1 gpo, nand(io3), spi(mosi)
26 mpp2 2 gpo, nand(io4), spi(sck)
27 mpp3 3 gpo, nand(io5), spi(miso)
28 mpp4 4 gpio, nand(io6), uart0(rxd), ptp(clk)
29 mpp5 5 gpo, nand(io7), uart0(txd), ptp(trig)
45 mpp18 18 gpo, nand(io0)
46 mpp19 19 gpo, nand(io1)
62 mpp0 0 gpio, nand(io2), spi(cs)
63 mpp1 1 gpo, nand(io3), spi(mosi)
[all …]
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| H A D | lantiq,pinctrl-xway.txt | 56 ebu wait, nand ale, nand cs1, nand cle, spi_di, spi_do, spi_clk, spi_cs1,
67 ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, nand rd,
79 ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, nand rd,
93 exin0, exin1, exin2, exin4, nand ale, nand cs0, nand cs1, nand cle,
94 nand rdy, nand rd, nand_d0, nand_d1, nand_d2, nand_d3, nand_d4, nand_d5,
95 nand_d6, nand_d7, nand_d1, nand wr, nand wp, nand se, spi_di, spi_do,
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| H A D | marvell,orion-pinctrl.txt | 55 mpp6 6 gpio, pci(req5), nand(re0), sata0(act)
56 mpp7 7 gpio, pci(gnt5), nand(we0), sata1(act)
61 mpp12 12 gpio, ge(txd4), nand(re1), sata0(ledprsnt)
62 mpp13 13 gpio, ge(txd5), nand(we1), sata1(ledprsnt)
63 mpp14 14 gpio, ge(txd6), nand(re2), sata0(ledact)
64 mpp15 15 gpio, ge(txd7), nand(we2), sata1(ledact)
80 mpp6 6 gpio, pci(req5), nand(re0)
81 mpp7 7 gpio, pci(gnt5), nand(we0)
86 mpp12 12 gpio, ge(txd4), nand(re1)
87 mpp13 13 gpio, ge(txd5), nand(we1)
[all …]
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| /freebsd/sys/contrib/device-tree/src/arm/microchip/ |
| H A D | at91-linea.dtsi | 61 nand: nand@3 { label
64 nand-bus-width = <8>;
65 nand-ecc-mode = "hw";
66 nand-ecc-strength = <4>;
67 nand-ecc-step-size = <512>;
68 nand-on-flash-bbt;
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| H A D | pm9g45.dts | 39 nand {
40 pinctrl_nand_rb: nand-rb-0 {
89 nand_controller: nand-controller {
94 nand@3 {
98 nand-bus-width = <8>;
99 nand-ecc-mode = "soft";
100 nand-on-flash-bbt;
158 linux,default-trigger = "nand-disk";
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| H A D | at91sam9x5cm.dtsi | 57 nand_controller: nand-controller {
64 nand@3 {
68 nand-bus-width = <8>;
69 nand-ecc-mode = "hw";
70 nand-ecc-strength = <2>;
71 nand-ecc-step-size = <512>;
72 nand-on-flash-bbt;
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| /freebsd/sys/contrib/device-tree/src/mips/ni/ |
| H A D | 169445.dts | 44 compatible = "ni,169445-nand-gpio";
52 compatible = "ni,169445-nand-gpio";
60 nand@0 {
61 compatible = "gpio-control-nand";
62 nand-on-flash-bbt;
63 nand-ecc-mode = "soft_bch";
64 nand-ecc-step-size = <512>;
65 nand-ecc-strength = <4>;
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| /freebsd/sys/contrib/device-tree/src/mips/brcm/ |
| H A D | bcm97xxx-nand-cs1-bch24.dtsi | 2 &nand {
6 nand-on-flash-bbt;
8 nand-ecc-strength = <24>;
9 nand-ecc-step-size = <1024>;
10 brcm,nand-oob-sector-size = <27>;
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| H A D | bcm97xxx-nand-cs1-bch4.dtsi | 2 &nand {
6 nand-on-flash-bbt;
8 nand-ecc-strength = <4>;
9 nand-ecc-step-size = <512>;
10 brcm,nand-oob-sector-size = <16>;
|