1*c66ec88fSEmmanuel VadotMacronix Raw NAND Controller Device Tree Bindings 2*c66ec88fSEmmanuel Vadot------------------------------------------------- 3*c66ec88fSEmmanuel Vadot 4*c66ec88fSEmmanuel VadotRequired properties: 5*c66ec88fSEmmanuel Vadot- compatible: should be "mxic,multi-itfc-v009-nand-controller" 6*c66ec88fSEmmanuel Vadot- reg: should contain 1 entry for the registers 7*c66ec88fSEmmanuel Vadot- #address-cells: should be set to 1 8*c66ec88fSEmmanuel Vadot- #size-cells: should be set to 0 9*c66ec88fSEmmanuel Vadot- interrupts: interrupt line connected to this raw NAND controller 10*c66ec88fSEmmanuel Vadot- clock-names: should contain "ps", "send" and "send_dly" 11*c66ec88fSEmmanuel Vadot- clocks: should contain 3 phandles for the "ps", "send" and 12*c66ec88fSEmmanuel Vadot "send_dly" clocks 13*c66ec88fSEmmanuel Vadot 14*c66ec88fSEmmanuel VadotChildren nodes: 15*c66ec88fSEmmanuel Vadot- children nodes represent the available NAND chips. 16*c66ec88fSEmmanuel Vadot 17*c66ec88fSEmmanuel VadotSee Documentation/devicetree/bindings/mtd/nand-controller.yaml 18*c66ec88fSEmmanuel Vadotfor more details on generic bindings. 19*c66ec88fSEmmanuel Vadot 20*c66ec88fSEmmanuel VadotExample: 21*c66ec88fSEmmanuel Vadot 22*c66ec88fSEmmanuel Vadot nand: nand-controller@43c30000 { 23*c66ec88fSEmmanuel Vadot compatible = "mxic,multi-itfc-v009-nand-controller"; 24*c66ec88fSEmmanuel Vadot reg = <0x43c30000 0x10000>; 25*c66ec88fSEmmanuel Vadot #address-cells = <1>; 26*c66ec88fSEmmanuel Vadot #size-cells = <0>; 27*c66ec88fSEmmanuel Vadot interrupts = <GIC_SPI 0x1d IRQ_TYPE_EDGE_RISING>; 28*c66ec88fSEmmanuel Vadot clocks = <&clkwizard 0>, <&clkwizard 1>, <&clkc 15>; 29*c66ec88fSEmmanuel Vadot clock-names = "send", "send_dly", "ps"; 30*c66ec88fSEmmanuel Vadot 31*c66ec88fSEmmanuel Vadot nand@0 { 32*c66ec88fSEmmanuel Vadot reg = <0>; 33*c66ec88fSEmmanuel Vadot nand-ecc-mode = "soft"; 34*c66ec88fSEmmanuel Vadot nand-ecc-algo = "bch"; 35*c66ec88fSEmmanuel Vadot }; 36*c66ec88fSEmmanuel Vadot }; 37