Home
last modified time | relevance | path

Searched refs:msix (Results 1 – 25 of 47) sorted by relevance

12

/freebsd/sys/amd64/vmm/io/
H A Dppt.c106 } msix; member
278 rid = ppt->msix.startrid + idx; in ppt_teardown_msix_intr()
279 res = ppt->msix.res[idx]; in ppt_teardown_msix_intr()
280 cookie = ppt->msix.cookie[idx]; in ppt_teardown_msix_intr()
288 ppt->msix.res[idx] = NULL; in ppt_teardown_msix_intr()
289 ppt->msix.cookie[idx] = NULL; in ppt_teardown_msix_intr()
297 if (ppt->msix.num_msgs == 0) in ppt_teardown_msix()
300 for (i = 0; i < ppt->msix.num_msgs; i++) in ppt_teardown_msix()
303 free(ppt->msix.res, M_PPTMSIX); in ppt_teardown_msix()
304 free(ppt->msix.cookie, M_PPTMSIX); in ppt_teardown_msix()
[all …]
/freebsd/sys/dev/pci/
H A Dpci.c957 cfg->msix.msix_location = ptr; in pci_read_cap()
958 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2); in pci_read_cap()
960 cfg->msix.msix_table_bar = PCIR_BAR(val & in pci_read_cap()
962 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK; in pci_read_cap()
964 cfg->msix.msix_pba_bar = PCIR_BAR(val & in pci_read_cap()
966 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK; in pci_read_cap()
1688 struct pcicfg_msix *msix = &dinfo->cfg.msix; in pci_write_msix_entry() local
1691 KASSERT(msix->msix_table_len > index, ("bogus index")); in pci_write_msix_entry()
1692 offset = msix->msix_table_offset + index * 16; in pci_write_msix_entry()
1693 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff); in pci_write_msix_entry()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dal,alpine-msix.txt7 - compatible: should be "al,alpine-msix"
17 msix: msix {
18 compatible = "al,alpine-msix";
/freebsd/sys/contrib/device-tree/src/arm/amazon/
H A Dalpine.dtsi164 msi-parent = <&msix>;
167 msix: msix@fbe00000 { label
168 compatible = "al,alpine-msix";
/freebsd/sys/dev/igc/
H A Dif_igc.h279 u32 msix; member
288 u32 msix; member
325 int msix; member
H A Dif_igc.c1031 IGC_WRITE_REG(hw, IGC_EITR(que->msix), que->eitr_setting); in igc_neweitr()
1120 struct tx_ring *txr = &sc->tx_queues[que->msix].txr; in igc_msix_que()
1519 igc_if_msix_intr_assign(if_ctx_t ctx, int msix) in igc_if_msix_intr_assign() argument
1541 rx_que->msix = vector; in igc_if_msix_intr_assign()
1561 tx_que->msix = (vector % sc->rx_num_queues); in igc_if_msix_intr_assign()
1613 ivar |= (rx_que->msix | IGC_IVAR_VALID) << 16; in igc_configure_queues()
1616 ivar |= rx_que->msix | IGC_IVAR_VALID; in igc_configure_queues()
1627 ivar |= (tx_que->msix | IGC_IVAR_VALID) << 24; in igc_configure_queues()
1630 ivar |= (tx_que->msix | IGC_IVAR_VALID) << 8; in igc_configure_queues()
1649 IGC_WRITE_REG(hw, IGC_EITR(rx_que->msix), newitr); in igc_configure_queues()
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/al/
H A Dalpine-v2.dtsi142 msi-parent = <&msix>;
145 msix: msix@fbe00000 { label
146 compatible = "al,alpine-msix";
/freebsd/sys/contrib/device-tree/src/arm64/amazon/
H A Dalpine-v2.dtsi143 msi-parent = <&msix>;
146 msix: msix@fbe00000 { label
147 compatible = "al,alpine-msix";
H A Dalpine-v3.dtsi352 msi-parent = <&msix>;
355 msix: msix@fbe00000 { label
356 compatible = "al,alpine-msix";
/freebsd/sys/dev/e1000/
H A Dif_em.h444 u32 msix; member
453 u32 msix; member
489 int msix; member
H A Dif_em.c1769 E1000_WRITE_REG(hw, E1000_EITR(que->msix), in em_newitr()
1777 if (hw->mac.type == e1000_82574 && que->msix) { in em_newitr()
1779 E1000_EITR_82574(que->msix), in em_newitr()
1900 struct tx_ring *txr = &sc->tx_queues[que->msix].txr; in em_msix_que()
2475 em_if_msix_intr_assign(if_ctx_t ctx, int msix) in em_if_msix_intr_assign() argument
2497 rx_que->msix = vector; in em_if_msix_intr_assign()
2508 sc->ivars |= (8 | rx_que->msix) << (i * 4); in em_if_msix_intr_assign()
2524 tx_que->msix = (vector % sc->rx_num_queues); in em_if_msix_intr_assign()
2535 sc->ivars |= (8 | tx_que->msix) << (8 + (i * 4)); in em_if_msix_intr_assign()
2600 ivar |= (rx_que->msix | E1000_IVAR_VALID) << in igb_configure_queues()
[all …]
/freebsd/sys/dev/ixgbe/
H A Dixgbe.h319 u32 msix; /* This queue's MSIX vector */ member
331 u32 msix; /* This queue's MSIX vector */ member
377 int msix; member
H A Dif_ixv.c712 ixv_disable_queue(sc, que->msix); in ixv_msix_que()
1034 ixv_if_msix_intr_assign(if_ctx_t ctx, int msix) in ixv_if_msix_intr_assign() argument
1059 rx_que->msix = vector; in ixv_if_msix_intr_assign()
1065 tx_que->msix = i % sc->num_rx_queues; in ixv_if_msix_intr_assign()
1067 &sc->rx_queues[tx_que->msix].que_irq, in ixv_if_msix_intr_assign()
1638 ixv_enable_queue(sc, que->msix); in ixv_if_enable_intr()
1711 ixv_set_ivar(sc, i, que->msix, 0); in ixv_configure_ivars()
1713 ixv_set_ivar(sc, i, que->msix, 1); in ixv_configure_ivars()
1715 IXGBE_WRITE_REG(&sc->hw, IXGBE_VTEITR(que->msix), in ixv_configure_ivars()
H A Dif_fdir.c142 input, common, que->msix); in ixgbe_atr()
H A Dif_ix.c2206 ixgbe_if_msix_intr_assign(if_ctx_t ctx, int msix) in ixgbe_if_msix_intr_assign() argument
2232 rx_que->msix = vector; in ixgbe_if_msix_intr_assign()
2237 tx_que->msix = i % sc->num_rx_queues; in ixgbe_if_msix_intr_assign()
2239 &sc->rx_queues[tx_que->msix].que_irq, in ixgbe_if_msix_intr_assign()
2277 IXGBE_WRITE_REG(&sc->hw, IXGBE_EITR(que->msix), in ixgbe_perform_aim()
2340 ixgbe_disable_queue(sc, que->msix); in ixgbe_msix_que()
2792 reg = IXGBE_READ_REG(&que->sc->hw, IXGBE_EITR(que->msix)); in ixgbe_sysctl_interrupt_rate_handler()
2809 IXGBE_WRITE_REG(&que->sc->hw, IXGBE_EITR(que->msix), reg); in ixgbe_sysctl_interrupt_rate_handler()
3450 ixgbe_set_ivar(sc, rxr->me, rx_que->msix, 0); in ixgbe_configure_ivars()
3453 IXGBE_WRITE_REG(&sc->hw, IXGBE_EITR(rx_que->msix), newitr); in ixgbe_configure_ivars()
[all …]
/freebsd/sys/dts/arm/
H A Dannapurna-alpine.dts178 msix: msix { label
179 compatible = "annapurna-labs,al-msix";
199 msi-parent = <&msix>;
/freebsd/sys/dev/iavf/
H A Diavf_iflib.h203 u32 msix; member
222 u32 msix; member
H A Dif_iavf_iflib.c57 static int iavf_if_msix_intr_assign(if_ctx_t ctx, int msix);
818 iavf_if_msix_intr_assign(if_ctx_t ctx, int msix __unused) in iavf_if_msix_intr_assign()
854 rx_que->msix = vector; in iavf_if_msix_intr_assign()
865 tx_que->msix = (i % vsi->shared->isc_nrxqsets) + 1; in iavf_if_msix_intr_assign()
924 iavf_enable_queue_irq(hw, rx_que->msix - 1); in iavf_if_rx_queue_intr_enable()
945 iavf_enable_queue_irq(hw, tx_que->msix - 1); in iavf_if_tx_queue_intr_enable()
2059 sbuf_printf(buf, "(rxq %3d): %d\n", i, rx_que->msix); in iavf_sysctl_queue_interrupt_table()
2063 sbuf_printf(buf, "(txq %3d): %d\n", i, tx_que->msix); in iavf_sysctl_queue_interrupt_table()
/freebsd/sys/dev/oce/
H A Doce_user.h75 } msix; member
/freebsd/sys/dev/ixl/
H A Dixl.h386 u32 msix; member
396 u32 msix; /* This queue's MSIX vector */ member
H A Dixl_iw.c41 #define IXL_IW_VEC_BASE(pf) ((pf)->msix - (pf)->iw_msix)
43 #define IXL_IW_VEC_LIMIT(pf) ((pf)->msix)
H A Dif_ixl.c104 static int ixl_if_msix_intr_assign(if_ctx_t ctx, int msix);
1073 ixl_if_msix_intr_assign(if_ctx_t ctx, int msix) in ixl_if_msix_intr_assign() argument
1116 rx_que->msix = vector; in ixl_if_msix_intr_assign()
1130 tx_que->msix = (i % vsi->shared->isc_nrxqsets) + 1; in ixl_if_msix_intr_assign()
1178 ixl_disable_queue(hw, rx_que->msix - 1); in ixl_if_disable_intr()
1194 ixl_enable_queue(hw, rx_que->msix - 1); in ixl_if_rx_queue_intr_enable()
1206 ixl_enable_queue(hw, tx_que->msix - 1); in ixl_if_tx_queue_intr_enable()
/freebsd/sys/dev/ice/
H A Dice_rdma.h228 * @var ice_rdma_peer::msix
229 * info about msix vectors
248 struct ice_rdma_msix msix; member
/freebsd/sys/dev/tws/
H A Dtws.h237 struct tws_msix_info msix; /* msix info */ member
/freebsd/sys/dev/irdma/
H A Dicrdma.c529 rf->msix_count = peer->msix.count; in irdma_fill_device_info()
530 rf->msix_info.entry = peer->msix.base; in irdma_fill_device_info()
531 rf->msix_info.vector = peer->msix.count; in irdma_fill_device_info()

12