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Searched refs:msi (Results 1 – 25 of 271) sorted by relevance

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/freebsd/sys/x86/x86/
H A Dmsi.c92 #define INTEL_ADDR(msi) \ argument
93 (MSI_INTEL_ADDR_BASE | (msi)->msi_cpu << 12 | \
95 #define INTEL_ADDR_EXT(msi) \ argument
96 (MSI_INTEL_ADDR_BASE | ((msi)->msi_cpu & 0xff) << 12 | \
97 ((msi)->msi_cpu & 0x7f00) >> 3 | \
99 #define INTEL_DATA(msi) \ argument
100 (MSI_INTEL_DATA_TRGREDG | MSI_INTEL_DATA_DELFIXED | (msi)->msi_vector)
210 struct msi_intsrc *msi = (struct msi_intsrc *)isrc; in msi_enable_intr() local
212 msi = msi->msi_first; in msi_enable_intr()
213 if (msi->msi_enabled == 0) { in msi_enable_intr()
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/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dpci-msi.txt23 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
32 - msi-map: Maps a Requester ID to an MSI controller and associated
33 msi-specifier data. The property is an arbitrary number of tuples of
34 (rid-base,msi-controller,msi-base,length), where:
38 * msi-controller is a single phandle to an MSI controller
40 * msi-base is an msi-specifier describing the msi-specifier produced for the
47 the listed msi-controller, with the msi-specifier (r - rid-base + msi-base).
49 - msi-map-mask: A mask to be applied to each Requester ID prior to being mapped
50 to an msi-specifier per the msi-map property.
52 - msi-parent: Describes the MSI parent of the root complex itself. Where
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H A Dxgene-pci-msi.txt5 - compatible: should be "apm,xgene1-msi" to identify
7 - msi-controller: indicates that this is an X-Gene v1 PCIe MSI controller node
16 Each PCIe node needs to have property msi-parent that points to an MSI
24 msi@79000000 {
25 compatible = "apm,xgene1-msi";
26 msi-controller;
46 + PCIe controller node with msi-parent property pointing to MSI node:
67 msi-parent= <&msi>;
H A Dbrcm,iproc-pcie.txt52 - msi-map: Maps a Requester ID to an MSI controller and associated MSI
55 - msi-parent: Link to the device node of the MSI controller, used when no MSI
60 the use of 'msi-map' and 'msi-parent':
61 Documentation/devicetree/bindings/pci/pci-msi.txt
62 Documentation/devicetree/bindings/interrupt-controller/msi.txt
66 - compatible: Must be "brcm,iproc-msi"
67 - msi-controller: claims itself as an MSI controller
71 - brcm,pcie-msi-inten: Needs to be present for some older iProc platforms that
99 msi-parent = <&msi0>;
102 msi0: msi@18012000 {
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H A Daltera-pcie-msi.txt4 - compatible: should contain "altr,msi-1.0"
14 - msi-controller: indicates that this is MSI controller node
18 msi0: msi@0xFF200000 {
19 compatible = "altr,msi-1.0";
25 msi-controller;
/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dfsl,ls-scfg-msi.txt5 - compatible: should be "fsl,<soc-name>-msi" to identify
7 "fsl,ls1021a-msi"
8 "fsl,ls1043a-msi"
9 "fsl,ls1046a-msi"
10 "fsl,ls1043a-v1.1-msi"
11 "fsl,ls1012a-msi"
12 - msi-controller: indicates that this is a PCIe MSI controller node
20 Each PCIe node needs to have property msi-parent that points to
25 msi1: msi-controller@1571000 {
26 compatible = "fsl,ls1043a-msi";
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H A Dmsi.txt40 - msi-controller: Identifies the node as an MSI controller.
45 - #msi-cells: The number of cells in an msi-specifier, required if not zero.
50 The meaning of the msi-specifier is defined by the device tree binding of
64 - msi-parent: A list of phandle + msi-specifier pairs, one for each MSI
68 MSI controllers listed in the msi-parent property.
73 When #msi-cells is non-zero, busses with an msi-parent will require
85 msi_a: msi-controller@a {
88 msi-controller;
89 /* No sideband data, so #msi-cells omitted */
92 msi_b: msi-controller@b {
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H A Dal,alpine-msix.txt10 - msi-controller: identifies the node as an PCI Message Signaled Interrupt
12 - al,msi-base-spi: SPI base of the MSI frame
13 - al,msi-num-spis: number of SPIs assigned to the MSI frame, relative to SPI0
22 msi-controller;
23 al,msi-base-spi = <160>;
24 al,msi-num-spis = <160>;
/freebsd/sys/contrib/device-tree/Bindings/powerpc/fsl/
H A Dmsi-pic.txt5 The first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
6 etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" or
7 "fsl,mpic-msi-v4.3" depending on the parent type and version. If mpic
9 provided to access these 16 registers, and compatible "fsl,mpic-msi-v4.3"
21 be set as edge sensitive. If msi-available-ranges is present, only
25 - msi-available-ranges: use <start count> style section to define which
26 msi interrupt can be used in the 256 msi interrupts. This property is
33 - msi-address-64: 64-bit PCI address of the MSIIR register. The MSIIR register
43 msi@41600 {
44 compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
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/freebsd/sys/contrib/device-tree/src/mips/loongson/
H A Dloongson64c_4core_ls7a.dts28 msi: msi-controller@2ff00000 { label
29 compatible = "loongson,pch-msi-1.0";
33 msi-controller;
34 loongson,msi-base-vec = <64>;
35 loongson,msi-num-vecs = <64>;
H A Dloongson64g_4core_ls7a.dts32 msi: msi-controller@2ff00000 { label
33 compatible = "loongson,pch-msi-1.0";
37 msi-controller;
38 loongson,msi-base-vec = <64>;
39 loongson,msi-num-vecs = <192>;
/freebsd/sys/contrib/device-tree/src/arm64/marvell/
H A Darmada-ap80x.dtsi112 msi-controller;
114 arm,msi-base-spi = <160>;
115 arm,msi-num-spis = <32>;
119 msi-controller;
121 arm,msi-base-spi = <192>;
122 arm,msi-num-spis = <32>;
126 msi-controller;
128 arm,msi-base-spi = <224>;
129 arm,msi-num-spis = <32>;
133 msi-controller;
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H A Darmada-ap810-ap0.dtsi63 gic_its_ap0: msi-controller@3040000 {
65 msi-controller;
66 #msi-cells = <1>;
75 msi-parent = <&gic_its_ap0 0xa0>;
83 msi-parent = <&gic_its_ap0 0xa1>;
91 msi-parent = <&gic_its_ap0 0xa2>;
99 msi-parent = <&gic_its_ap0 0xa3>;
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dmpc8641si-post.dtsi75 msi@41600 {
76 compatible = "fsl,mpc8641-msi", "fsl,mpic-msi";
78 msi@41800 {
79 compatible = "fsl,mpc8641-msi", "fsl,mpic-msi";
81 msi@41a00 {
82 compatible = "fsl,mpc8641-msi", "fsl,mpic-msi";
H A Dqoriq-mpic.dtsi54 msi0: msi@41600 {
55 compatible = "fsl,mpic-msi";
57 msi-available-ranges = <0 0x100>;
69 msi1: msi@41800 {
70 compatible = "fsl,mpic-msi";
72 msi-available-ranges = <0 0x100>;
84 msi2: msi@41a00 {
85 compatible = "fsl,mpic-msi";
87 msi-available-ranges = <0 0x100>;
H A Dqoriq-mpic4.3.dtsi54 msi0: msi@41600 {
55 compatible = "fsl,mpic-msi-v4.3";
76 msi1: msi@41800 {
77 compatible = "fsl,mpic-msi-v4.3";
98 msi2: msi@41a00 {
99 compatible = "fsl,mpic-msi-v4.3";
120 msi3: msi@41c00 {
121 compatible = "fsl,mpic-msi-v4.3";
/freebsd/sys/amd64/vmm/io/
H A Dppt.c102 } msi; member
275 if (ppt->msi.num_msgs == 0) in ppt_teardown_msi()
278 for (i = 0; i < ppt->msi.num_msgs; i++) { in ppt_teardown_msi()
279 rid = ppt->msi.startrid + i; in ppt_teardown_msi()
280 res = ppt->msi.res[i]; in ppt_teardown_msi()
281 cookie = ppt->msi.cookie[i]; in ppt_teardown_msi()
289 ppt->msi.res[i] = NULL; in ppt_teardown_msi()
290 ppt->msi.cookie[i] = NULL; in ppt_teardown_msi()
293 if (ppt->msi.startrid == 1) in ppt_teardown_msi()
296 ppt->msi.num_msgs = 0; in ppt_teardown_msi()
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/freebsd/sys/contrib/device-tree/src/arm64/broadcom/northstar2/
H A Dns2.dtsi143 msi-parent = <&v2m0>;
173 msi-parent = <&v2m0>;
191 msi-parent = <&v2m0>;
370 msi-controller;
372 arm,msi-base-spi = <72>;
373 arm,msi-num-spis = <16>;
378 msi-controller;
380 arm,msi-base-spi = <88>;
381 arm,msi-num-spis = <16>;
386 msi-controller;
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/freebsd/sys/arm/arm/
H A Dgic_acpi.c271 ACPI_MADT_GENERIC_MSI_FRAME *msi; in madt_gicv2m_handler() local
278 msi = (ACPI_MADT_GENERIC_MSI_FRAME *)entry; in madt_gicv2m_handler()
280 device_printf(dev, "frame: %x %lx %x %u %u\n", msi->MsiFrameId, in madt_gicv2m_handler()
281 msi->BaseAddress, msi->Flags, msi->SpiCount, msi->SpiBase); in madt_gicv2m_handler()
290 msi->BaseAddress, msi->BaseAddress + PAGE_SIZE - 1, in madt_gicv2m_handler()
/freebsd/sys/dev/ahci/
H A Dahci_pci.c618 ctlr->msi = 0; in ahci_pci_attach()
621 ctlr->msi = 1; in ahci_pci_attach()
623 ctlr->msi = 2; in ahci_pci_attach()
625 device_get_unit(dev), "msi", &ctlr->msi); in ahci_pci_attach()
628 ctlr->msi = 0; in ahci_pci_attach()
629 if (ctlr->msi < 0) in ahci_pci_attach()
630 ctlr->msi = 0; in ahci_pci_attach()
631 else if (ctlr->msi == 1) { in ahci_pci_attach()
634 } else if (ctlr->msi > 1) in ahci_pci_attach()
635 ctlr->msi = 2; in ahci_pci_attach()
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/freebsd/sys/contrib/device-tree/src/arm64/hisilicon/
H A Dhip05.dtsi253 its_peri: msi-controller@8c000000 {
255 msi-controller;
256 #msi-cells = <1>;
260 its_m3: msi-controller@a3000000 {
262 msi-controller;
263 #msi-cells = <1>;
267 its_pcie: msi-controller@b7000000 {
269 msi-controller;
270 #msi-cells = <1>;
274 its_dsa: msi-controller@c6000000 {
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H A Dhip07.dtsi959 p0_its_peri_a: msi-controller@4c000000 {
961 msi-controller;
962 #msi-cells = <1>;
966 p0_its_peri_b: msi-controller@6c000000 {
968 msi-controller;
969 #msi-cells = <1>;
973 p0_its_dsa_a: msi-controller@c6000000 {
975 msi-controller;
976 #msi-cells = <1>;
980 p0_its_dsa_b: msi-controller@8c6000000 {
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/freebsd/sys/contrib/device-tree/src/arm64/arm/
H A Dmorello.dtsi241 its1: msi-controller@30040000 {
245 msi-controller;
246 #msi-cells = <1>;
249 its2: msi-controller@30060000 {
253 msi-controller;
254 #msi-cells = <1>;
257 its_ccix: msi-controller@30080000 {
261 msi-controller;
262 #msi-cells = <1>;
265 its_pcie: msi-controller@300a0000 {
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/freebsd/sys/dev/mvs/
H A Dmvs_pci.c295 int msi = 0; in mvs_setup_interrupt() local
299 device_get_unit(dev), "msi", &msi); in mvs_setup_interrupt()
300 if (msi < 0) in mvs_setup_interrupt()
301 msi = 0; in mvs_setup_interrupt()
302 else if (msi > 0) in mvs_setup_interrupt()
303 msi = min(1, pci_msi_count(dev)); in mvs_setup_interrupt()
305 if (msi && pci_alloc_msi(dev, &msi) != 0) in mvs_setup_interrupt()
306 msi = 0; in mvs_setup_interrupt()
307 ctlr->msi = msi; in mvs_setup_interrupt()
309 ctlr->irq.r_irq_rid = msi ? 1 : 0; in mvs_setup_interrupt()
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/freebsd/sys/contrib/device-tree/Bindings/misc/
H A Dfsl,qoriq-mc.txt32 The msi-map property is used to associate the devices with both the ITS
36 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
127 - msi-map: Maps an ICID to a GIC ITS and associated msi-specifier
131 (icid-base,gic-its,msi-base,length).
134 associated with the listed GIC ITS, with the msi-specifier
135 (i - icid-base + msi-base).
139 - msi-parent
147 use msi-map.
164 msi-controller;
174 /* define msi map for ICIDs 23-64 */
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