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/freebsd/sys/dev/mlx4/mlx4_core/
H A Dmlx4_fw_qos.c87 struct mlx4_cmd_mailbox *mailbox; in mlx4_SET_PORT_PRIO2TC() local
93 mailbox = mlx4_alloc_cmd_mailbox(dev); in mlx4_SET_PORT_PRIO2TC()
94 if (IS_ERR(mailbox)) in mlx4_SET_PORT_PRIO2TC()
95 return PTR_ERR(mailbox); in mlx4_SET_PORT_PRIO2TC()
97 context = mailbox->buf; in mlx4_SET_PORT_PRIO2TC()
103 err = mlx4_cmd(dev, mailbox->dma, in_mod, 1, MLX4_CMD_SET_PORT, in mlx4_SET_PORT_PRIO2TC()
106 mlx4_free_cmd_mailbox(dev, mailbox); in mlx4_SET_PORT_PRIO2TC()
114 struct mlx4_cmd_mailbox *mailbox; in mlx4_SET_PORT_SCHEDULER() local
120 mailbox = mlx4_alloc_cmd_mailbox(dev); in mlx4_SET_PORT_SCHEDULER()
121 if (IS_ERR(mailbox)) in mlx4_SET_PORT_SCHEDULER()
[all …]
H A Dmlx4_cq.c94 static int mlx4_SW2HW_CQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, in mlx4_SW2HW_CQ() argument
97 return mlx4_cmd(dev, mailbox->dma, cq_num, 0, in mlx4_SW2HW_CQ()
102 static int mlx4_MODIFY_CQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, in mlx4_MODIFY_CQ() argument
105 return mlx4_cmd(dev, mailbox->dma, cq_num, opmod, MLX4_CMD_MODIFY_CQ, in mlx4_MODIFY_CQ()
109 static int mlx4_HW2SW_CQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, in mlx4_HW2SW_CQ() argument
112 return mlx4_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, in mlx4_HW2SW_CQ()
113 cq_num, mailbox ? 0 : 1, MLX4_CMD_HW2SW_CQ, in mlx4_HW2SW_CQ()
120 struct mlx4_cmd_mailbox *mailbox; in mlx4_cq_modify() local
124 mailbox = mlx4_alloc_cmd_mailbox(dev); in mlx4_cq_modify()
125 if (IS_ERR(mailbox)) in mlx4_cq_modify()
[all …]
H A Dmlx4_srq.c64 static int mlx4_SW2HW_SRQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, in mlx4_SW2HW_SRQ() argument
67 return mlx4_cmd(dev, mailbox->dma, srq_num, 0, in mlx4_SW2HW_SRQ()
72 static int mlx4_HW2SW_SRQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, in mlx4_HW2SW_SRQ() argument
75 return mlx4_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, srq_num, in mlx4_HW2SW_SRQ()
76 mailbox ? 0 : 1, MLX4_CMD_HW2SW_SRQ, in mlx4_HW2SW_SRQ()
86 static int mlx4_QUERY_SRQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, in mlx4_QUERY_SRQ() argument
89 return mlx4_cmd_box(dev, 0, mailbox->dma, srq_num, 0, MLX4_CMD_QUERY_SRQ, in mlx4_QUERY_SRQ()
166 struct mlx4_cmd_mailbox *mailbox; in mlx4_srq_alloc() local
181 mailbox = mlx4_alloc_cmd_mailbox(dev); in mlx4_srq_alloc()
182 if (IS_ERR(mailbox)) { in mlx4_srq_alloc()
[all …]
H A Dmlx4_mcg.c54 struct mlx4_cmd_mailbox *mailbox, in mlx4_QP_FLOW_STEERING_ATTACH() argument
61 err = mlx4_cmd_imm(dev, mailbox->dma, &imm, size, 0, in mlx4_QP_FLOW_STEERING_ATTACH()
83 struct mlx4_cmd_mailbox *mailbox) in mlx4_READ_ENTRY() argument
85 return mlx4_cmd_box(dev, 0, mailbox->dma, index, 0, MLX4_CMD_READ_MCG, in mlx4_READ_ENTRY()
90 struct mlx4_cmd_mailbox *mailbox) in mlx4_WRITE_ENTRY() argument
92 return mlx4_cmd(dev, mailbox->dma, index, 0, MLX4_CMD_WRITE_MCG, in mlx4_WRITE_ENTRY()
97 struct mlx4_cmd_mailbox *mailbox) in mlx4_WRITE_PROMISC() argument
102 return mlx4_cmd(dev, mailbox->dma, in_mod, 0x1, in mlx4_WRITE_PROMISC()
107 static int mlx4_GID_HASH(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, in mlx4_GID_HASH() argument
113 err = mlx4_cmd_imm(dev, mailbox->dma, &imm, 0, op_mod, in mlx4_GID_HASH()
[all …]
H A Dmlx4_fw.c179 struct mlx4_cmd_mailbox *mailbox; in mlx4_MOD_STAT_CFG() local
188 mailbox = mlx4_alloc_cmd_mailbox(dev); in mlx4_MOD_STAT_CFG()
189 if (IS_ERR(mailbox)) in mlx4_MOD_STAT_CFG()
190 return PTR_ERR(mailbox); in mlx4_MOD_STAT_CFG()
191 inbox = mailbox->buf; in mlx4_MOD_STAT_CFG()
196 err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG, in mlx4_MOD_STAT_CFG()
199 mlx4_free_cmd_mailbox(dev, mailbox); in mlx4_MOD_STAT_CFG()
205 struct mlx4_cmd_mailbox *mailbox; in mlx4_QUERY_FUNC() local
220 mailbox = mlx4_alloc_cmd_mailbox(dev); in mlx4_QUERY_FUNC()
221 if (IS_ERR(mailbox)) in mlx4_QUERY_FUNC()
[all …]
H A Dmlx4_mr.c282 static int mlx4_SW2HW_MPT(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, in mlx4_SW2HW_MPT() argument
285 return mlx4_cmd(dev, mailbox->dma, mpt_index, in mlx4_SW2HW_MPT()
290 static int mlx4_HW2SW_MPT(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox, in mlx4_HW2SW_MPT() argument
293 return mlx4_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, mpt_index, in mlx4_HW2SW_MPT()
294 !mailbox, MLX4_CMD_HW2SW_MPT, in mlx4_HW2SW_MPT()
304 struct mlx4_cmd_mailbox *mailbox = NULL; in mlx4_mr_hw_get_mpt() local
323 mailbox = mlx4_alloc_cmd_mailbox(dev); in mlx4_mr_hw_get_mpt()
324 if (IS_ERR(mailbox)) in mlx4_mr_hw_get_mpt()
325 return PTR_ERR(mailbox); in mlx4_mr_hw_get_mpt()
327 err = mlx4_cmd_box(dev, 0, mailbox->dma, key, in mlx4_mr_hw_get_mpt()
[all …]
H A Dmlx4_port.c130 struct mlx4_cmd_mailbox *mailbox; in mlx4_set_port_mac_table() local
134 mailbox = mlx4_alloc_cmd_mailbox(dev); in mlx4_set_port_mac_table()
135 if (IS_ERR(mailbox)) in mlx4_set_port_mac_table()
136 return PTR_ERR(mailbox); in mlx4_set_port_mac_table()
138 memcpy(mailbox->buf, entries, MLX4_MAC_TABLE_SIZE); in mlx4_set_port_mac_table()
142 err = mlx4_cmd(dev, mailbox->dma, in_mod, MLX4_SET_PORT_ETH_OPCODE, in mlx4_set_port_mac_table()
146 mlx4_free_cmd_mailbox(dev, mailbox); in mlx4_set_port_mac_table()
539 struct mlx4_cmd_mailbox *mailbox; in mlx4_set_port_vlan_table() local
543 mailbox = mlx4_alloc_cmd_mailbox(dev); in mlx4_set_port_vlan_table()
544 if (IS_ERR(mailbox)) in mlx4_set_port_vlan_table()
[all …]
/freebsd/sys/dev/mthca/
H A Dmthca_cmd.c607 struct mthca_mailbox *mailbox; in mthca_alloc_mailbox() local
609 mailbox = kmalloc(sizeof *mailbox, gfp_mask); in mthca_alloc_mailbox()
610 if (!mailbox) in mthca_alloc_mailbox()
613 mailbox->buf = pci_pool_alloc(dev->cmd.pool, gfp_mask, &mailbox->dma); in mthca_alloc_mailbox()
614 if (!mailbox->buf) { in mthca_alloc_mailbox()
615 kfree(mailbox); in mthca_alloc_mailbox()
619 return mailbox; in mthca_alloc_mailbox()
622 void mthca_free_mailbox(struct mthca_dev *dev, struct mthca_mailbox *mailbox) in mthca_free_mailbox() argument
624 if (!mailbox) in mthca_free_mailbox()
627 pci_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma); in mthca_free_mailbox()
[all …]
H A Dmthca_mcg.c67 struct mthca_mailbox *mailbox; in find_mgm() local
72 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); in find_mgm()
73 if (IS_ERR(mailbox)) in find_mgm()
75 mgid = mailbox->buf; in find_mgm()
79 err = mthca_MGID_HASH(dev, mailbox, hash); in find_mgm()
116 mthca_free_mailbox(dev, mailbox); in find_mgm()
123 struct mthca_mailbox *mailbox; in mthca_multicast_attach() local
131 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); in mthca_multicast_attach()
132 if (IS_ERR(mailbox)) in mthca_multicast_attach()
133 return PTR_ERR(mailbox); in mthca_multicast_attach()
[all …]
H A Dmthca_cmd.h253 void mthca_free_mailbox(struct mthca_dev *dev, struct mthca_mailbox *mailbox);
283 int mthca_SW2HW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
285 int mthca_HW2SW_MPT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
287 int mthca_WRITE_MTT(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
292 int mthca_SW2HW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
294 int mthca_HW2SW_EQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
296 int mthca_SW2HW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
298 int mthca_HW2SW_CQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
301 int mthca_SW2HW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
303 int mthca_HW2SW_SRQ(struct mthca_dev *dev, struct mthca_mailbox *mailbox,
[all …]
H A Dmthca_srq.c204 struct mthca_mailbox *mailbox; in mthca_alloc_srq() local
250 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL); in mthca_alloc_srq()
251 if (IS_ERR(mailbox)) { in mthca_alloc_srq()
252 err = PTR_ERR(mailbox); in mthca_alloc_srq()
266 mthca_arbel_init_srq_context(dev, pd, srq, mailbox->buf, udata); in mthca_alloc_srq()
268 mthca_tavor_init_srq_context(dev, pd, srq, mailbox->buf, udata); in mthca_alloc_srq()
270 err = mthca_SW2HW_SRQ(dev, mailbox, srq->srqn); in mthca_alloc_srq()
286 mthca_free_mailbox(dev, mailbox); in mthca_alloc_srq()
297 err = mthca_HW2SW_SRQ(dev, mailbox, srq->srqn); in mthca_alloc_srq()
306 mthca_free_mailbox(dev, mailbox); in mthca_alloc_srq()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mailbox/
H A Domap-mailbox.txt4 The OMAP mailbox hardware facilitates communication between different processors
5 using a queued mailbox interrupt mechanism. The IP block is external to the
10 Each mailbox IP block/cluster has a certain number of h/w fifo queues and output
43 "ti,omap2-mailbox" for OMAP2420, OMAP2430 SoCs
44 "ti,omap3-mailbox" for OMAP3430, OMAP3630 SoCs
45 "ti,omap4-mailbox" for OMAP44xx, OMAP54xx, AM33xx,
47 "ti,am654-mailbox" for K3 AM65x and J721E SoCs
48 "ti,am64-mailbox" for K3 AM64x SoCs
49 - reg: Contains the mailbox register address range (base
51 - interrupts: Contains the interrupt information for the mailbox
[all …]
H A Dmailbox.txt4 assign appropriate mailbox channel to client drivers.
9 - #mbox-cells: Must be at least 1. Number of cells in a mailbox
13 mailbox: mailbox {
22 - mboxes: List of phandle and mailbox channel specifiers.
25 - mbox-names: List of identifier strings for each mailbox channel.
27 users of these mailboxes for IPC, one for each mailbox. This shared
29 communication between the mailbox client and the remote.
36 mboxes = <&mailbox 0 &mailbox 1>;
57 mboxes = <&mailbox 0>;
H A Daltera-mailbox.txt5 - compatible : "altr,mailbox-1.0".
6 - reg : physical base address of the mailbox and length of
8 - #mbox-cells: Common mailbox binding property to identify the number
9 of cells required for the mailbox specifier. Should be 1.
16 mbox_tx: mailbox@100 {
17 compatible = "altr,mailbox-1.0";
24 mbox_rx: mailbox@200 {
25 compatible = "altr,mailbox-1.0";
35 Documentation/devicetree/bindings/mailbox/mailbox.txt for details). Each value
36 of the mboxes property should contain a phandle to the mailbox controller
H A Dxlnx,zynqmp-ipi-mailbox.txt4 The Xilinx IPI(Inter Processor Interrupt) mailbox controller is to manage
35 - compatible: Shall be: "xlnx,zynqmp-ipi-mailbox"
40 - #address-cells: number of address cells of internal IPI mailbox nodes
41 - #size-cells: number of size cells of internal IPI mailbox nodes
43 Internal IPI mailbox node:
60 - xlnx,ipi-id: remote Xilinx IPI agent ID of which the mailbox is
73 - mboxes: Standard property to specify a mailbox
74 (See ./mailbox.txt)
75 - mbox-names: List of identifier strings for each mailbox
81 compatible = "xlnx,zynqmp-ipi-mailbox";
[all …]
H A Dhisilicon,hi6220-mailbox.txt4 Hisilicon Hi6220 mailbox supports up to 32 channels. Each channel
15 - reg: Contains the mailbox register address range (base
19 - #mbox-cells: Common mailbox binding property to identify the number
20 of cells required for the mailbox specifier. Must be 3.
22 phandle: Label name of mailbox controller
27 mailbox driver uses it to acknowledge interrupt
28 - interrupts: Contains the interrupt information for the mailbox
34 - hi6220,mbox-tx-noirq: Property of MCU firmware's feature, so mailbox driver
42 mailbox: mailbox@f7510000 {
58 - mboxes: Standard property to specify a Mailbox (See ./mailbox.txt)
[all …]
H A Dxgene-slimpro-mailbox.txt1 The APM X-Gene SLIMpro mailbox is used to communicate messages between
6 There are total of 8 interrupts in this mailbox. Each used for an individual
7 door bell (or mailbox channel).
12 - reg: Contains the mailbox register address range.
15 the interrupt for mailbox channel 0 and interrupt 1 for
16 mailbox channel 1 and so likewise for the reminder.
18 - #mbox-cells: only one to specify the mailbox channel number.
23 mailbox: mailbox@10540000 {
H A Drockchip-mailbox.txt1 Rockchip mailbox
3 The Rockchip mailbox is used by the Rockchip CPU cores to communicate
6 Refer to ./mailbox.txt for generic information about mailbox device-tree
17 - #mbox-cells: Common mailbox binding property to identify the number
18 of cells required for the mailbox specifier. Should be 1
25 compatible = "rockchip,rk3368-mailbox";
H A Dbrcm,bcm2835-mbox.txt1 Broadcom BCM2835 VideoCore mailbox IPC
9 - #mbox-cells: Specifies the number of cells needed to encode a mailbox
11 mailbox channel implemented by the device.
15 mailbox: mailbox@7e00b880 {
24 mboxes = <&mailbox>;
H A Dsti-mailbox.txt10 - compatible : Should be "st,stih407-mailbox"
12 - mbox-name : Name of the mailbox
20 - interrupts : Contains the IRQ line for a Rx mailbox
24 mailbox0: mailbox@0 {
25 compatible = "st,stih407-mailbox";
38 - mboxes : Standard property to specify a Mailbox (See ./mailbox.txt)
47 compatible = "mailbox-test";
H A Dmarvell,armada-3700-rwtm-mailbox.txt4 - compatible: must be "marvell,armada-3700-rwtm-mailbox"
5 - reg: physical base address of the mailbox and length of memory mapped
7 - interrupts: the IRQ line for the mailbox
11 rwtm: mailbox@b0000 {
12 compatible = "marvell,armada-3700-rwtm-mailbox";
H A Dhisilicon,hi3660-mailbox.txt3 Hisilicon Hi3660 mailbox controller supports up to 32 channels. Messages
21 - interrupts: : Contains the two IRQ lines for mailbox.
25 mailbox: mailbox@e896b000 {
38 - mboxes : Standard property to specify a Mailbox (See ./mailbox.txt)
50 mboxes = <&mailbox 13 3 0>;
/freebsd/sys/dev/mlx4/mlx4_en/
H A Dmlx4_en_port.c46 struct mlx4_cmd_mailbox *mailbox; in mlx4_SET_VLAN_FLTR() local
54 mailbox = mlx4_alloc_cmd_mailbox(dev); in mlx4_SET_VLAN_FLTR()
55 if (IS_ERR(mailbox)) in mlx4_SET_VLAN_FLTR()
56 return PTR_ERR(mailbox); in mlx4_SET_VLAN_FLTR()
58 filter = mailbox->buf; in mlx4_SET_VLAN_FLTR()
68 err = mlx4_cmd(dev, mailbox->dma, priv->port, 0, MLX4_CMD_SET_VLAN_FLTR, in mlx4_SET_VLAN_FLTR()
70 mlx4_free_cmd_mailbox(dev, mailbox); in mlx4_SET_VLAN_FLTR()
79 struct mlx4_cmd_mailbox *mailbox; in mlx4_en_QUERY_PORT() local
82 mailbox = mlx4_alloc_cmd_mailbox(mdev->dev); in mlx4_en_QUERY_PORT()
83 if (IS_ERR(mailbox)) in mlx4_en_QUERY_PORT()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/power/reset/
H A Dxlnx,zynqmp-power.txt17 mailbox controller device node and an args specifier
18 that will be the phandle to the intended sub-mailbox
20 Documentation/devicetree/bindings/mailbox/mailbox.txt
21 for more details about the generic mailbox controller
23 Documentation/devicetree/bindings/mailbox/ \
24 xlnx,zynqmp-ipi-mailbox.txt for typical controller that
45 Example with IPI mailbox method:
/freebsd/sys/contrib/device-tree/Bindings/serial/
H A Dnvidia,tegra194-tcu.txt4 systems within the Tegra SoC. It is implemented through a mailbox-
20 This node is a mailbox consumer. See the following files for details of
21 the mailbox subsystem, and the specifiers implemented by the relevant
24 - .../mailbox/mailbox.txt
25 - .../mailbox/nvidia,tegra186-hsp.txt

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