1*c66ec88fSEmmanuel VadotRockchip mailbox 2*c66ec88fSEmmanuel Vadot 3*c66ec88fSEmmanuel VadotThe Rockchip mailbox is used by the Rockchip CPU cores to communicate 4*c66ec88fSEmmanuel Vadotrequests to MCU processor. 5*c66ec88fSEmmanuel Vadot 6*c66ec88fSEmmanuel VadotRefer to ./mailbox.txt for generic information about mailbox device-tree 7*c66ec88fSEmmanuel Vadotbindings. 8*c66ec88fSEmmanuel Vadot 9*c66ec88fSEmmanuel VadotRequired properties: 10*c66ec88fSEmmanuel Vadot 11*c66ec88fSEmmanuel Vadot - compatible: should be one of the following. 12*c66ec88fSEmmanuel Vadot - "rockchip,rk3368-mbox" for rk3368 13*c66ec88fSEmmanuel Vadot - reg: physical base address of the controller and length of memory mapped 14*c66ec88fSEmmanuel Vadot region. 15*c66ec88fSEmmanuel Vadot - interrupts: The interrupt number to the cpu. The interrupt specifier format 16*c66ec88fSEmmanuel Vadot depends on the interrupt controller. 17*c66ec88fSEmmanuel Vadot - #mbox-cells: Common mailbox binding property to identify the number 18*c66ec88fSEmmanuel Vadot of cells required for the mailbox specifier. Should be 1 19*c66ec88fSEmmanuel Vadot 20*c66ec88fSEmmanuel VadotExample: 21*c66ec88fSEmmanuel Vadot-------- 22*c66ec88fSEmmanuel Vadot 23*c66ec88fSEmmanuel Vadot/* RK3368 */ 24*c66ec88fSEmmanuel Vadotmbox: mbox@ff6b0000 { 25*c66ec88fSEmmanuel Vadot compatible = "rockchip,rk3368-mailbox"; 26*c66ec88fSEmmanuel Vadot reg = <0x0 0xff6b0000 0x0 0x1000>, 27*c66ec88fSEmmanuel Vadot interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 28*c66ec88fSEmmanuel Vadot <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 29*c66ec88fSEmmanuel Vadot <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 30*c66ec88fSEmmanuel Vadot <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 31*c66ec88fSEmmanuel Vadot #mbox-cells = <1>; 32*c66ec88fSEmmanuel Vadot}; 33