1 /*- 2 * Copyright (c) 2013-2020, Mellanox Technologies. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 #ifndef MLX5_IFC_H 27 #define MLX5_IFC_H 28 29 #include <dev/mlx5/mlx5_fpga/mlx5_ifc_fpga.h> 30 31 enum { 32 MLX5_EVENT_TYPE_NOTIFY_ANY = 0x0, 33 MLX5_EVENT_TYPE_COMP = 0x0, 34 MLX5_EVENT_TYPE_PATH_MIG = 0x1, 35 MLX5_EVENT_TYPE_COMM_EST = 0x2, 36 MLX5_EVENT_TYPE_SQ_DRAINED = 0x3, 37 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13, 38 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14, 39 MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c, 40 MLX5_EVENT_TYPE_DCT_KEY_VIOLATION = 0x1d, 41 MLX5_EVENT_TYPE_CQ_ERROR = 0x4, 42 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x5, 43 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x7, 44 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc, 45 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 46 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 47 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 48 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x8, 49 MLX5_EVENT_TYPE_PORT_CHANGE = 0x9, 50 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15, 51 MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT = 0x16, 52 MLX5_EVENT_TYPE_TEMP_WARN_EVENT = 0x17, 53 MLX5_EVENT_TYPE_XRQ_ERROR = 0x18, 54 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19, 55 MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT = 0x1e, 56 MLX5_EVENT_TYPE_CODING_PPS_EVENT = 0x25, 57 MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT = 0x22, 58 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a, 59 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b, 60 MLX5_EVENT_TYPE_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 61 MLX5_EVENT_TYPE_CMD = 0xa, 62 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb, 63 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd, 64 MLX5_EVENT_TYPE_FPGA_ERROR = 0x20, 65 MLX5_EVENT_TYPE_FPGA_QP_ERROR = 0x21, 66 MLX5_EVENT_TYPE_OBJECT_CHANGE = 0x27, 67 }; 68 69 enum { 70 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, 71 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, 72 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, 73 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3, 74 MLX5_MODIFY_TIR_BITMASK_SELF_LB_EN = 0x4 75 }; 76 77 enum { 78 MLX5_MODIFY_RQT_BITMASK_RQN_LIST = 0x1, 79 }; 80 81 enum { 82 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 83 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 84 }; 85 86 enum { 87 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 88 MLX5_OBJ_TYPE_MKEY = 0xff01, 89 MLX5_OBJ_TYPE_QP = 0xff02, 90 MLX5_OBJ_TYPE_PSV = 0xff03, 91 MLX5_OBJ_TYPE_RMP = 0xff04, 92 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 93 MLX5_OBJ_TYPE_RQ = 0xff06, 94 MLX5_OBJ_TYPE_SQ = 0xff07, 95 MLX5_OBJ_TYPE_TIR = 0xff08, 96 MLX5_OBJ_TYPE_TIS = 0xff09, 97 MLX5_OBJ_TYPE_DCT = 0xff0a, 98 MLX5_OBJ_TYPE_XRQ = 0xff0b, 99 MLX5_OBJ_TYPE_RQT = 0xff0e, 100 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 101 MLX5_OBJ_TYPE_CQ = 0xff10, 102 }; 103 104 enum { 105 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 106 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 107 MLX5_CMD_OP_INIT_HCA = 0x102, 108 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 109 MLX5_CMD_OP_ENABLE_HCA = 0x104, 110 MLX5_CMD_OP_DISABLE_HCA = 0x105, 111 MLX5_CMD_OP_QUERY_PAGES = 0x107, 112 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 113 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 114 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 115 MLX5_CMD_OP_SET_ISSI = 0x10b, 116 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 117 MLX5_CMD_OP_QUERY_OTHER_HCA_CAP = 0x10e, 118 MLX5_CMD_OP_MODIFY_OTHER_HCA_CAP = 0x10f, 119 MLX5_CMD_OP_CREATE_MKEY = 0x200, 120 MLX5_CMD_OP_QUERY_MKEY = 0x201, 121 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 122 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 123 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 124 MLX5_CMD_OP_CREATE_EQ = 0x301, 125 MLX5_CMD_OP_DESTROY_EQ = 0x302, 126 MLX5_CMD_OP_QUERY_EQ = 0x303, 127 MLX5_CMD_OP_GEN_EQE = 0x304, 128 MLX5_CMD_OP_CREATE_CQ = 0x400, 129 MLX5_CMD_OP_DESTROY_CQ = 0x401, 130 MLX5_CMD_OP_QUERY_CQ = 0x402, 131 MLX5_CMD_OP_MODIFY_CQ = 0x403, 132 MLX5_CMD_OP_CREATE_QP = 0x500, 133 MLX5_CMD_OP_DESTROY_QP = 0x501, 134 MLX5_CMD_OP_RST2INIT_QP = 0x502, 135 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 136 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 137 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 138 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 139 MLX5_CMD_OP_2ERR_QP = 0x507, 140 MLX5_CMD_OP_2RST_QP = 0x50a, 141 MLX5_CMD_OP_QUERY_QP = 0x50b, 142 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 143 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 144 MLX5_CMD_OP_CREATE_PSV = 0x600, 145 MLX5_CMD_OP_DESTROY_PSV = 0x601, 146 MLX5_CMD_OP_CREATE_SRQ = 0x700, 147 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 148 MLX5_CMD_OP_QUERY_SRQ = 0x702, 149 MLX5_CMD_OP_ARM_RQ = 0x703, 150 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 151 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 152 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 153 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 154 MLX5_CMD_OP_CREATE_DCT = 0x710, 155 MLX5_CMD_OP_DESTROY_DCT = 0x711, 156 MLX5_CMD_OP_DRAIN_DCT = 0x712, 157 MLX5_CMD_OP_QUERY_DCT = 0x713, 158 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 159 MLX5_CMD_OP_SET_DC_CNAK_TRACE = 0x715, 160 MLX5_CMD_OP_QUERY_DC_CNAK_TRACE = 0x716, 161 MLX5_CMD_OP_CREATE_XRQ = 0x717, 162 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 163 MLX5_CMD_OP_QUERY_XRQ = 0x719, 164 MLX5_CMD_OP_ARM_XRQ = 0x71a, 165 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 166 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 167 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 168 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 169 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 170 171 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 172 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 173 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 174 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 175 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 176 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 177 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 178 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 179 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 180 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 181 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 182 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 183 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 184 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 185 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 186 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 187 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 188 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780, 189 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 190 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 191 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 192 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 193 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 194 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 195 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 196 MLX5_CMD_OP_ALLOC_PD = 0x800, 197 MLX5_CMD_OP_DEALLOC_PD = 0x801, 198 MLX5_CMD_OP_ALLOC_UAR = 0x802, 199 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 200 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 201 MLX5_CMD_OP_ACCESS_REG = 0x805, 202 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 203 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 204 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 205 MLX5_CMD_OP_MAD_IFC = 0x50d, 206 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 207 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 208 MLX5_CMD_OP_NOP = 0x80d, 209 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 210 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 211 MLX5_CMD_OP_SET_BURST_SIZE = 0x812, 212 MLX5_CMD_OP_QUERY_BURST_SIZE = 0x813, 213 MLX5_CMD_OP_ACTIVATE_TRACER = 0x814, 214 MLX5_CMD_OP_DEACTIVATE_TRACER = 0x815, 215 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 216 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 217 MLX5_CMD_OP_QUERY_DIAGNOSTIC_PARAMS = 0x819, 218 MLX5_CMD_OP_SET_DIAGNOSTICS = 0x820, 219 MLX5_CMD_OP_QUERY_DIAGNOSTICS = 0x821, 220 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 221 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 222 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 223 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 224 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 225 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 226 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 227 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 228 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 229 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 230 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 231 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 232 MLX5_CMD_OP_CREATE_LAG = 0x840, 233 MLX5_CMD_OP_MODIFY_LAG = 0x841, 234 MLX5_CMD_OP_QUERY_LAG = 0x842, 235 MLX5_CMD_OP_DESTROY_LAG = 0x843, 236 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 237 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 238 MLX5_CMD_OP_CREATE_TIR = 0x900, 239 MLX5_CMD_OP_MODIFY_TIR = 0x901, 240 MLX5_CMD_OP_DESTROY_TIR = 0x902, 241 MLX5_CMD_OP_QUERY_TIR = 0x903, 242 MLX5_CMD_OP_CREATE_SQ = 0x904, 243 MLX5_CMD_OP_MODIFY_SQ = 0x905, 244 MLX5_CMD_OP_DESTROY_SQ = 0x906, 245 MLX5_CMD_OP_QUERY_SQ = 0x907, 246 MLX5_CMD_OP_CREATE_RQ = 0x908, 247 MLX5_CMD_OP_MODIFY_RQ = 0x909, 248 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 249 MLX5_CMD_OP_QUERY_RQ = 0x90b, 250 MLX5_CMD_OP_CREATE_RMP = 0x90c, 251 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 252 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 253 MLX5_CMD_OP_QUERY_RMP = 0x90f, 254 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 255 MLX5_CMD_OP_QUERY_DELAY_DROP_PARAMS = 0x911, 256 MLX5_CMD_OP_CREATE_TIS = 0x912, 257 MLX5_CMD_OP_MODIFY_TIS = 0x913, 258 MLX5_CMD_OP_DESTROY_TIS = 0x914, 259 MLX5_CMD_OP_QUERY_TIS = 0x915, 260 MLX5_CMD_OP_CREATE_RQT = 0x916, 261 MLX5_CMD_OP_MODIFY_RQT = 0x917, 262 MLX5_CMD_OP_DESTROY_RQT = 0x918, 263 MLX5_CMD_OP_QUERY_RQT = 0x919, 264 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 265 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 266 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 267 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 268 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 269 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 270 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 271 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 272 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 273 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 274 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 275 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 276 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 277 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 278 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 279 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 280 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 281 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 282 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 283 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 284 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 285 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 286 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 287 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 288 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 289 MLX5_CMD_OP_CREATE_GENERAL_OBJ = 0xa00, 290 MLX5_CMD_OP_MODIFY_GENERAL_OBJ = 0xa01, 291 MLX5_CMD_OP_QUERY_GENERAL_OBJ = 0xa02, 292 MLX5_CMD_OP_DESTROY_GENERAL_OBJ = 0xa03, 293 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 294 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 295 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 296 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 297 }; 298 299 /* Valid range for general commands that don't work over an object */ 300 enum { 301 MLX5_CMD_OP_GENERAL_START = 0xb00, 302 MLX5_CMD_OP_GENERAL_END = 0xd00, 303 }; 304 305 enum { 306 MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0), 307 MLX5_FT_NIC_TX_RDMA_2_NIC_TX = BIT(1), 308 }; 309 310 enum { 311 MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_QUERY_FW_INFO = 0x8007, 312 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_CAPABILITY = 0x8400, 313 MLX5_ICMD_CMDS_OPCODE_ICMD_ACCESS_REGISTER = 0x9001, 314 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_VIRTUAL_MAC = 0x9003, 315 MLX5_ICMD_CMDS_OPCODE_ICMD_SET_VIRTUAL_MAC = 0x9004, 316 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_WOL_ROL = 0x9005, 317 MLX5_ICMD_CMDS_OPCODE_ICMD_SET_WOL_ROL = 0x9006, 318 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_INIT = 0x9007, 319 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_HEADER_STATUS = 0x9008, 320 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_ETOC_STATUS = 0x9009, 321 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_SET_EVENT = 0x900a, 322 MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_INIT_OCSD = 0xf004 323 }; 324 325 enum { 326 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = 1ULL << 0x13, 327 }; 328 329 enum { 330 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 331 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 332 }; 333 334 enum { 335 MLX5_HCA_CAP_GENERAL_OBJ_TYPES_ENCRYPTION_KEY = 1 << 0xc, 336 }; 337 338 enum { 339 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 340 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 341 }; 342 343 enum { 344 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1, 345 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2, 346 }; 347 348 struct mlx5_ifc_flow_table_fields_supported_bits { 349 u8 outer_dmac[0x1]; 350 u8 outer_smac[0x1]; 351 u8 outer_ether_type[0x1]; 352 u8 outer_ip_version[0x1]; 353 u8 outer_first_prio[0x1]; 354 u8 outer_first_cfi[0x1]; 355 u8 outer_first_vid[0x1]; 356 u8 reserved_1[0x1]; 357 u8 outer_second_prio[0x1]; 358 u8 outer_second_cfi[0x1]; 359 u8 outer_second_vid[0x1]; 360 u8 outer_ipv6_flow_label[0x1]; 361 u8 outer_sip[0x1]; 362 u8 outer_dip[0x1]; 363 u8 outer_frag[0x1]; 364 u8 outer_ip_protocol[0x1]; 365 u8 outer_ip_ecn[0x1]; 366 u8 outer_ip_dscp[0x1]; 367 u8 outer_udp_sport[0x1]; 368 u8 outer_udp_dport[0x1]; 369 u8 outer_tcp_sport[0x1]; 370 u8 outer_tcp_dport[0x1]; 371 u8 outer_tcp_flags[0x1]; 372 u8 outer_gre_protocol[0x1]; 373 u8 outer_gre_key[0x1]; 374 u8 outer_vxlan_vni[0x1]; 375 u8 outer_geneve_vni[0x1]; 376 u8 outer_geneve_oam[0x1]; 377 u8 outer_geneve_protocol_type[0x1]; 378 u8 outer_geneve_opt_len[0x1]; 379 u8 reserved_2[0x1]; 380 u8 source_eswitch_port[0x1]; 381 382 u8 inner_dmac[0x1]; 383 u8 inner_smac[0x1]; 384 u8 inner_ether_type[0x1]; 385 u8 inner_ip_version[0x1]; 386 u8 inner_first_prio[0x1]; 387 u8 inner_first_cfi[0x1]; 388 u8 inner_first_vid[0x1]; 389 u8 reserved_4[0x1]; 390 u8 inner_second_prio[0x1]; 391 u8 inner_second_cfi[0x1]; 392 u8 inner_second_vid[0x1]; 393 u8 inner_ipv6_flow_label[0x1]; 394 u8 inner_sip[0x1]; 395 u8 inner_dip[0x1]; 396 u8 inner_frag[0x1]; 397 u8 inner_ip_protocol[0x1]; 398 u8 inner_ip_ecn[0x1]; 399 u8 inner_ip_dscp[0x1]; 400 u8 inner_udp_sport[0x1]; 401 u8 inner_udp_dport[0x1]; 402 u8 inner_tcp_sport[0x1]; 403 u8 inner_tcp_dport[0x1]; 404 u8 inner_tcp_flags[0x1]; 405 u8 reserved_5[0x9]; 406 407 u8 reserved_6[0x1a]; 408 u8 bth_dst_qp[0x1]; 409 u8 reserved_7[0x4]; 410 u8 source_sqn[0x1]; 411 412 u8 reserved_8[0x20]; 413 }; 414 415 struct mlx5_ifc_eth_discard_cntrs_grp_bits { 416 u8 ingress_general_high[0x20]; 417 418 u8 ingress_general_low[0x20]; 419 420 u8 ingress_policy_engine_high[0x20]; 421 422 u8 ingress_policy_engine_low[0x20]; 423 424 u8 ingress_vlan_membership_high[0x20]; 425 426 u8 ingress_vlan_membership_low[0x20]; 427 428 u8 ingress_tag_frame_type_high[0x20]; 429 430 u8 ingress_tag_frame_type_low[0x20]; 431 432 u8 egress_vlan_membership_high[0x20]; 433 434 u8 egress_vlan_membership_low[0x20]; 435 436 u8 loopback_filter_high[0x20]; 437 438 u8 loopback_filter_low[0x20]; 439 440 u8 egress_general_high[0x20]; 441 442 u8 egress_general_low[0x20]; 443 444 u8 reserved_at_1c0[0x40]; 445 446 u8 egress_hoq_high[0x20]; 447 448 u8 egress_hoq_low[0x20]; 449 450 u8 port_isolation_high[0x20]; 451 452 u8 port_isolation_low[0x20]; 453 454 u8 egress_policy_engine_high[0x20]; 455 456 u8 egress_policy_engine_low[0x20]; 457 458 u8 ingress_tx_link_down_high[0x20]; 459 460 u8 ingress_tx_link_down_low[0x20]; 461 462 u8 egress_stp_filter_high[0x20]; 463 464 u8 egress_stp_filter_low[0x20]; 465 466 u8 egress_hoq_stall_high[0x20]; 467 468 u8 egress_hoq_stall_low[0x20]; 469 470 u8 reserved_at_340[0x440]; 471 }; 472 473 struct mlx5_ifc_flow_table_prop_layout_bits { 474 u8 ft_support[0x1]; 475 u8 reserved_at_1[0x1]; 476 u8 flow_counter[0x1]; 477 u8 flow_modify_en[0x1]; 478 u8 modify_root[0x1]; 479 u8 identified_miss_table_mode[0x1]; 480 u8 flow_table_modify[0x1]; 481 u8 reformat[0x1]; 482 u8 decap[0x1]; 483 u8 reserved_at_9[0x1]; 484 u8 pop_vlan[0x1]; 485 u8 push_vlan[0x1]; 486 u8 reserved_at_c[0x1]; 487 u8 pop_vlan_2[0x1]; 488 u8 push_vlan_2[0x1]; 489 u8 reformat_and_vlan_action[0x1]; 490 u8 reserved_at_10[0x1]; 491 u8 sw_owner[0x1]; 492 u8 reformat_l3_tunnel_to_l2[0x1]; 493 u8 reformat_l2_to_l3_tunnel[0x1]; 494 u8 reformat_and_modify_action[0x1]; 495 u8 ignore_flow_level[0x1]; 496 u8 reserved_at_16[0x1]; 497 u8 table_miss_action_domain[0x1]; 498 u8 termination_table[0x1]; 499 u8 reformat_and_fwd_to_table[0x1]; 500 u8 reserved_at_1a[0x2]; 501 u8 ipsec_encrypt[0x1]; 502 u8 ipsec_decrypt[0x1]; 503 u8 sw_owner_v2[0x1]; 504 u8 reserved_at_1f[0x1]; 505 u8 termination_table_raw_traffic[0x1]; 506 u8 reserved_at_21[0x1]; 507 u8 log_max_ft_size[0x6]; 508 u8 log_max_modify_header_context[0x8]; 509 u8 max_modify_header_actions[0x8]; 510 u8 max_ft_level[0x8]; 511 512 u8 reformat_add_esp_trasport[0x1]; 513 u8 reformat_l2_to_l3_esp_tunnel[0x1]; 514 u8 reformat_add_esp_transport_over_udp[0x1]; 515 u8 reformat_del_esp_trasport[0x1]; 516 u8 reformat_l3_esp_tunnel_to_l2[0x1]; 517 u8 reformat_del_esp_transport_over_udp[0x1]; 518 u8 execute_aso[0x1]; 519 u8 reserved_at_47[0x19]; 520 u8 reserved_at_60[0x2]; 521 u8 reformat_insert[0x1]; 522 u8 reformat_remove[0x1]; 523 u8 macsec_encrypt[0x1]; 524 u8 macsec_decrypt[0x1]; 525 u8 reserved_at_66[0x2]; 526 u8 reformat_add_macsec[0x1]; 527 u8 reformat_remove_macsec[0x1]; 528 u8 reserved_at_6a[0xe]; 529 u8 log_max_ft_num[0x8]; 530 u8 reserved_at_80[0x10]; 531 u8 log_max_flow_counter[0x8]; 532 u8 log_max_destination[0x8]; 533 u8 reserved_at_a0[0x18]; 534 u8 log_max_flow[0x8]; 535 u8 reserved_at_c0[0x40]; 536 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 537 538 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 539 }; 540 541 struct mlx5_ifc_odp_per_transport_service_cap_bits { 542 u8 send[0x1]; 543 u8 receive[0x1]; 544 u8 write[0x1]; 545 u8 read[0x1]; 546 u8 atomic[0x1]; 547 u8 srq_receive[0x1]; 548 u8 reserved_0[0x1a]; 549 }; 550 551 struct mlx5_ifc_flow_counter_list_bits { 552 u8 reserved_0[0x10]; 553 u8 flow_counter_id[0x10]; 554 555 u8 reserved_1[0x20]; 556 }; 557 558 struct mlx5_ifc_dest_format_struct_bits { 559 u8 destination_type[0x8]; 560 u8 destination_id[0x18]; 561 562 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 563 u8 packet_reformat[0x1]; 564 u8 reserved_at_22[0x6]; 565 u8 destination_table_type[0x8]; 566 u8 destination_eswitch_owner_vhca_id[0x10]; 567 }; 568 569 struct mlx5_ifc_ipv4_layout_bits { 570 u8 reserved_at_0[0x60]; 571 572 u8 ipv4[0x20]; 573 }; 574 575 struct mlx5_ifc_ipv6_layout_bits { 576 u8 ipv6[16][0x8]; 577 }; 578 579 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 580 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 581 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 582 u8 reserved_at_0[0x80]; 583 }; 584 585 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 586 u8 smac_47_16[0x20]; 587 588 u8 smac_15_0[0x10]; 589 u8 ethertype[0x10]; 590 591 u8 dmac_47_16[0x20]; 592 593 u8 dmac_15_0[0x10]; 594 u8 first_prio[0x3]; 595 u8 first_cfi[0x1]; 596 u8 first_vid[0xc]; 597 598 u8 ip_protocol[0x8]; 599 u8 ip_dscp[0x6]; 600 u8 ip_ecn[0x2]; 601 u8 cvlan_tag[0x1]; 602 u8 svlan_tag[0x1]; 603 u8 frag[0x1]; 604 u8 ip_version[0x4]; 605 u8 tcp_flags[0x9]; 606 607 u8 tcp_sport[0x10]; 608 u8 tcp_dport[0x10]; 609 610 u8 reserved_2[0x20]; 611 612 u8 udp_sport[0x10]; 613 u8 udp_dport[0x10]; 614 615 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 616 617 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 618 }; 619 620 struct mlx5_ifc_nvgre_key_bits { 621 u8 hi[0x18]; 622 u8 lo[0x8]; 623 }; 624 625 union mlx5_ifc_gre_key_bits { 626 struct mlx5_ifc_nvgre_key_bits nvgre; 627 u8 key[0x20]; 628 }; 629 630 struct mlx5_ifc_fte_match_set_misc_bits { 631 u8 gre_c_present[0x1]; 632 u8 reserved_at_1[0x1]; 633 u8 gre_k_present[0x1]; 634 u8 gre_s_present[0x1]; 635 u8 source_vhca_port[0x4]; 636 u8 source_sqn[0x18]; 637 638 u8 source_eswitch_owner_vhca_id[0x10]; 639 u8 source_port[0x10]; 640 641 u8 outer_second_prio[0x3]; 642 u8 outer_second_cfi[0x1]; 643 u8 outer_second_vid[0xc]; 644 u8 inner_second_prio[0x3]; 645 u8 inner_second_cfi[0x1]; 646 u8 inner_second_vid[0xc]; 647 648 u8 outer_second_cvlan_tag[0x1]; 649 u8 inner_second_cvlan_tag[0x1]; 650 u8 outer_second_svlan_tag[0x1]; 651 u8 inner_second_svlan_tag[0x1]; 652 u8 reserved_at_64[0xc]; 653 u8 gre_protocol[0x10]; 654 655 union mlx5_ifc_gre_key_bits gre_key; 656 657 u8 vxlan_vni[0x18]; 658 u8 bth_opcode[0x8]; 659 660 u8 geneve_vni[0x18]; 661 u8 reserved_at_d8[0x6]; 662 u8 geneve_tlv_option_0_exist[0x1]; 663 u8 geneve_oam[0x1]; 664 665 u8 reserved_at_e0[0xc]; 666 u8 outer_ipv6_flow_label[0x14]; 667 668 u8 reserved_at_100[0xc]; 669 u8 inner_ipv6_flow_label[0x14]; 670 671 u8 reserved_at_120[0xa]; 672 u8 geneve_opt_len[0x6]; 673 u8 geneve_protocol_type[0x10]; 674 675 u8 reserved_at_140[0x8]; 676 u8 bth_dst_qp[0x18]; 677 u8 inner_esp_spi[0x20]; 678 u8 outer_esp_spi[0x20]; 679 u8 reserved_at_1a0[0x60]; 680 }; 681 682 struct mlx5_ifc_fte_match_mpls_bits { 683 u8 mpls_label[0x14]; 684 u8 mpls_exp[0x3]; 685 u8 mpls_s_bos[0x1]; 686 u8 mpls_ttl[0x8]; 687 }; 688 689 struct mlx5_ifc_fte_match_set_misc2_bits { 690 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 691 692 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 693 694 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 695 696 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 697 698 u8 metadata_reg_c_7[0x20]; 699 700 u8 metadata_reg_c_6[0x20]; 701 702 u8 metadata_reg_c_5[0x20]; 703 704 u8 metadata_reg_c_4[0x20]; 705 706 u8 metadata_reg_c_3[0x20]; 707 708 u8 metadata_reg_c_2[0x20]; 709 710 u8 metadata_reg_c_1[0x20]; 711 712 u8 metadata_reg_c_0[0x20]; 713 714 u8 metadata_reg_a[0x20]; 715 716 u8 reserved_at_1a0[0x8]; 717 718 u8 macsec_syndrome[0x8]; 719 u8 ipsec_syndrome[0x8]; 720 u8 reserved_at_1b8[0x8]; 721 722 u8 reserved_at_1c0[0x40]; 723 }; 724 725 struct mlx5_ifc_fte_match_set_misc3_bits { 726 u8 inner_tcp_seq_num[0x20]; 727 728 u8 outer_tcp_seq_num[0x20]; 729 730 u8 inner_tcp_ack_num[0x20]; 731 732 u8 outer_tcp_ack_num[0x20]; 733 734 u8 reserved_at_80[0x8]; 735 u8 outer_vxlan_gpe_vni[0x18]; 736 737 u8 outer_vxlan_gpe_next_protocol[0x8]; 738 u8 outer_vxlan_gpe_flags[0x8]; 739 u8 reserved_at_b0[0x10]; 740 741 u8 icmp_header_data[0x20]; 742 743 u8 icmpv6_header_data[0x20]; 744 745 u8 icmp_type[0x8]; 746 u8 icmp_code[0x8]; 747 u8 icmpv6_type[0x8]; 748 u8 icmpv6_code[0x8]; 749 750 u8 geneve_tlv_option_0_data[0x20]; 751 752 u8 gtpu_teid[0x20]; 753 754 u8 gtpu_msg_type[0x8]; 755 u8 gtpu_msg_flags[0x8]; 756 u8 reserved_at_170[0x10]; 757 758 u8 gtpu_dw_2[0x20]; 759 760 u8 gtpu_first_ext_dw_0[0x20]; 761 762 u8 gtpu_dw_0[0x20]; 763 764 u8 reserved_at_1e0[0x20]; 765 }; 766 767 struct mlx5_ifc_fte_match_set_misc4_bits { 768 u8 prog_sample_field_value_0[0x20]; 769 770 u8 prog_sample_field_id_0[0x20]; 771 772 u8 prog_sample_field_value_1[0x20]; 773 774 u8 prog_sample_field_id_1[0x20]; 775 776 u8 prog_sample_field_value_2[0x20]; 777 778 u8 prog_sample_field_id_2[0x20]; 779 780 u8 prog_sample_field_value_3[0x20]; 781 782 u8 prog_sample_field_id_3[0x20]; 783 784 u8 reserved_at_100[0x100]; 785 }; 786 787 struct mlx5_ifc_fte_match_set_misc5_bits { 788 u8 macsec_tag_0[0x20]; 789 790 u8 macsec_tag_1[0x20]; 791 792 u8 macsec_tag_2[0x20]; 793 794 u8 macsec_tag_3[0x20]; 795 796 u8 tunnel_header_0[0x20]; 797 798 u8 tunnel_header_1[0x20]; 799 800 u8 tunnel_header_2[0x20]; 801 802 u8 tunnel_header_3[0x20]; 803 804 u8 reserved_at_100[0x100]; 805 }; 806 807 struct mlx5_ifc_cmd_pas_bits { 808 u8 pa_h[0x20]; 809 810 u8 pa_l[0x14]; 811 u8 reserved_0[0xc]; 812 }; 813 814 struct mlx5_ifc_uint64_bits { 815 u8 hi[0x20]; 816 817 u8 lo[0x20]; 818 }; 819 820 struct mlx5_ifc_application_prio_entry_bits { 821 u8 reserved_0[0x8]; 822 u8 priority[0x3]; 823 u8 reserved_1[0x2]; 824 u8 sel[0x3]; 825 u8 protocol_id[0x10]; 826 }; 827 828 struct mlx5_ifc_nodnic_ring_doorbell_bits { 829 u8 reserved_0[0x8]; 830 u8 ring_pi[0x10]; 831 u8 reserved_1[0x8]; 832 }; 833 834 enum { 835 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 836 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 837 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 838 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 839 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 840 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 841 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 842 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 843 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 844 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 845 }; 846 847 struct mlx5_ifc_ads_bits { 848 u8 fl[0x1]; 849 u8 free_ar[0x1]; 850 u8 reserved_0[0xe]; 851 u8 pkey_index[0x10]; 852 853 u8 reserved_1[0x8]; 854 u8 grh[0x1]; 855 u8 mlid[0x7]; 856 u8 rlid[0x10]; 857 858 u8 ack_timeout[0x5]; 859 u8 reserved_2[0x3]; 860 u8 src_addr_index[0x8]; 861 u8 log_rtm[0x4]; 862 u8 stat_rate[0x4]; 863 u8 hop_limit[0x8]; 864 865 u8 reserved_3[0x4]; 866 u8 tclass[0x8]; 867 u8 flow_label[0x14]; 868 869 u8 rgid_rip[16][0x8]; 870 871 u8 reserved_4[0x4]; 872 u8 f_dscp[0x1]; 873 u8 f_ecn[0x1]; 874 u8 reserved_5[0x1]; 875 u8 f_eth_prio[0x1]; 876 u8 ecn[0x2]; 877 u8 dscp[0x6]; 878 u8 udp_sport[0x10]; 879 880 u8 dei_cfi[0x1]; 881 u8 eth_prio[0x3]; 882 u8 sl[0x4]; 883 u8 port[0x8]; 884 u8 rmac_47_32[0x10]; 885 886 u8 rmac_31_0[0x20]; 887 }; 888 889 struct mlx5_ifc_diagnostic_counter_cap_bits { 890 u8 sync[0x1]; 891 u8 reserved_0[0xf]; 892 u8 counter_id[0x10]; 893 }; 894 895 struct mlx5_ifc_debug_cap_bits { 896 u8 reserved_0[0x18]; 897 u8 log_max_samples[0x8]; 898 899 u8 single[0x1]; 900 u8 repetitive[0x1]; 901 u8 health_mon_rx_activity[0x1]; 902 u8 reserved_1[0x15]; 903 u8 log_min_sample_period[0x8]; 904 905 u8 reserved_2[0x1c0]; 906 907 struct mlx5_ifc_diagnostic_counter_cap_bits diagnostic_counter[0x1f0]; 908 }; 909 910 struct mlx5_ifc_qos_cap_bits { 911 u8 packet_pacing[0x1]; 912 u8 esw_scheduling[0x1]; 913 u8 esw_bw_share[0x1]; 914 u8 esw_rate_limit[0x1]; 915 u8 hll[0x1]; 916 u8 packet_pacing_burst_bound[0x1]; 917 u8 packet_pacing_typical_size[0x1]; 918 u8 reserved_at_7[0x19]; 919 920 u8 reserved_at_20[0xA]; 921 u8 qos_remap_pp[0x1]; 922 u8 reserved_at_2b[0x15]; 923 924 u8 packet_pacing_max_rate[0x20]; 925 926 u8 packet_pacing_min_rate[0x20]; 927 928 u8 reserved_at_80[0x10]; 929 u8 packet_pacing_rate_table_size[0x10]; 930 931 u8 esw_element_type[0x10]; 932 u8 esw_tsar_type[0x10]; 933 934 u8 reserved_at_c0[0x10]; 935 u8 max_qos_para_vport[0x10]; 936 937 u8 max_tsar_bw_share[0x20]; 938 939 u8 reserved_at_100[0x700]; 940 }; 941 942 struct mlx5_ifc_snapshot_cap_bits { 943 u8 reserved_0[0x1d]; 944 u8 suspend_qp_uc[0x1]; 945 u8 suspend_qp_ud[0x1]; 946 u8 suspend_qp_rc[0x1]; 947 948 u8 reserved_1[0x1c]; 949 u8 restore_pd[0x1]; 950 u8 restore_uar[0x1]; 951 u8 restore_mkey[0x1]; 952 u8 restore_qp[0x1]; 953 954 u8 reserved_2[0x1e]; 955 u8 named_mkey[0x1]; 956 u8 named_qp[0x1]; 957 958 u8 reserved_3[0x7a0]; 959 }; 960 961 struct mlx5_ifc_e_switch_cap_bits { 962 u8 vport_svlan_strip[0x1]; 963 u8 vport_cvlan_strip[0x1]; 964 u8 vport_svlan_insert[0x1]; 965 u8 vport_cvlan_insert_if_not_exist[0x1]; 966 u8 vport_cvlan_insert_overwrite[0x1]; 967 u8 reserved_at_5[0x1]; 968 u8 vport_cvlan_insert_always[0x1]; 969 u8 esw_shared_ingress_acl[0x1]; 970 u8 esw_uplink_ingress_acl[0x1]; 971 u8 root_ft_on_other_esw[0x1]; 972 u8 reserved_at_a[0xf]; 973 u8 esw_functions_changed[0x1]; 974 u8 reserved_at_1a[0x1]; 975 u8 ecpf_vport_exists[0x1]; 976 u8 counter_eswitch_affinity[0x1]; 977 u8 merged_eswitch[0x1]; 978 u8 nic_vport_node_guid_modify[0x1]; 979 u8 nic_vport_port_guid_modify[0x1]; 980 981 u8 vxlan_encap_decap[0x1]; 982 u8 nvgre_encap_decap[0x1]; 983 u8 reserved_at_22[0x1]; 984 u8 log_max_fdb_encap_uplink[0x5]; 985 u8 reserved_at_21[0x3]; 986 u8 log_max_packet_reformat_context[0x5]; 987 u8 reserved_2b[0x6]; 988 u8 max_encap_header_size[0xa]; 989 990 u8 reserved_at_40[0xb]; 991 u8 log_max_esw_sf[0x5]; 992 u8 esw_sf_base_id[0x10]; 993 994 u8 reserved_at_60[0x7a0]; 995 996 }; 997 998 struct mlx5_ifc_flow_table_eswitch_cap_bits { 999 u8 reserved_0[0x200]; 1000 1001 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 1002 1003 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 1004 1005 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 1006 1007 u8 reserved_1[0x7800]; 1008 }; 1009 1010 struct mlx5_ifc_flow_table_nic_cap_bits { 1011 u8 nic_rx_multi_path_tirs[0x1]; 1012 u8 nic_rx_multi_path_tirs_fts[0x1]; 1013 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 1014 u8 reserved_at_3[0x4]; 1015 u8 sw_owner_reformat_supported[0x1]; 1016 u8 reserved_at_8[0x18]; 1017 1018 u8 encap_general_header[0x1]; 1019 u8 reserved_at_21[0xa]; 1020 u8 log_max_packet_reformat_context[0x5]; 1021 u8 reserved_at_30[0x6]; 1022 u8 max_encap_header_size[0xa]; 1023 u8 reserved_at_40[0x1c0]; 1024 1025 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 1026 1027 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 1028 1029 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 1030 1031 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 1032 1033 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 1034 1035 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 1036 1037 u8 reserved_1[0x7200]; 1038 }; 1039 1040 struct mlx5_ifc_port_selection_cap_bits { 1041 u8 reserved_at_0[0x10]; 1042 u8 port_select_flow_table[0x1]; 1043 u8 reserved_at_11[0x1]; 1044 u8 port_select_flow_table_bypass[0x1]; 1045 u8 reserved_at_13[0xd]; 1046 1047 u8 reserved_at_20[0x1e0]; 1048 1049 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 1050 1051 u8 reserved_at_400[0x7c00]; 1052 }; 1053 1054 struct mlx5_ifc_pddr_module_info_bits { 1055 u8 cable_technology[0x8]; 1056 u8 cable_breakout[0x8]; 1057 u8 ext_ethernet_compliance_code[0x8]; 1058 u8 ethernet_compliance_code[0x8]; 1059 1060 u8 cable_type[0x4]; 1061 u8 cable_vendor[0x4]; 1062 u8 cable_length[0x8]; 1063 u8 cable_identifier[0x8]; 1064 u8 cable_power_class[0x8]; 1065 1066 u8 reserved_at_40[0x8]; 1067 u8 cable_rx_amp[0x8]; 1068 u8 cable_rx_emphasis[0x8]; 1069 u8 cable_tx_equalization[0x8]; 1070 1071 u8 reserved_at_60[0x8]; 1072 u8 cable_attenuation_12g[0x8]; 1073 u8 cable_attenuation_7g[0x8]; 1074 u8 cable_attenuation_5g[0x8]; 1075 1076 u8 reserved_at_80[0x8]; 1077 u8 rx_cdr_cap[0x4]; 1078 u8 tx_cdr_cap[0x4]; 1079 u8 reserved_at_90[0x4]; 1080 u8 rx_cdr_state[0x4]; 1081 u8 reserved_at_98[0x4]; 1082 u8 tx_cdr_state[0x4]; 1083 1084 u8 vendor_name[16][0x8]; 1085 1086 u8 vendor_pn[16][0x8]; 1087 1088 u8 vendor_rev[0x20]; 1089 1090 u8 fw_version[0x20]; 1091 1092 u8 vendor_sn[16][0x8]; 1093 1094 u8 temperature[0x10]; 1095 u8 voltage[0x10]; 1096 1097 u8 rx_power_lane0[0x10]; 1098 u8 rx_power_lane1[0x10]; 1099 1100 u8 rx_power_lane2[0x10]; 1101 u8 rx_power_lane3[0x10]; 1102 1103 u8 reserved_at_2c0[0x40]; 1104 1105 u8 tx_power_lane0[0x10]; 1106 u8 tx_power_lane1[0x10]; 1107 1108 u8 tx_power_lane2[0x10]; 1109 u8 tx_power_lane3[0x10]; 1110 1111 u8 reserved_at_340[0x40]; 1112 1113 u8 tx_bias_lane0[0x10]; 1114 u8 tx_bias_lane1[0x10]; 1115 1116 u8 tx_bias_lane2[0x10]; 1117 u8 tx_bias_lane3[0x10]; 1118 1119 u8 reserved_at_3c0[0x40]; 1120 1121 u8 temperature_high_th[0x10]; 1122 u8 temperature_low_th[0x10]; 1123 1124 u8 voltage_high_th[0x10]; 1125 u8 voltage_low_th[0x10]; 1126 1127 u8 rx_power_high_th[0x10]; 1128 u8 rx_power_low_th[0x10]; 1129 1130 u8 tx_power_high_th[0x10]; 1131 u8 tx_power_low_th[0x10]; 1132 1133 u8 tx_bias_high_th[0x10]; 1134 u8 tx_bias_low_th[0x10]; 1135 1136 u8 reserved_at_4a0[0x10]; 1137 u8 wavelength[0x10]; 1138 1139 u8 reserved_at_4c0[0x300]; 1140 }; 1141 1142 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1143 u8 csum_cap[0x1]; 1144 u8 vlan_cap[0x1]; 1145 u8 lro_cap[0x1]; 1146 u8 lro_psh_flag[0x1]; 1147 u8 lro_time_stamp[0x1]; 1148 u8 lro_max_msg_sz_mode[0x2]; 1149 u8 wqe_vlan_insert[0x1]; 1150 u8 self_lb_en_modifiable[0x1]; 1151 u8 self_lb_mc[0x1]; 1152 u8 self_lb_uc[0x1]; 1153 u8 max_lso_cap[0x5]; 1154 u8 multi_pkt_send_wqe[0x2]; 1155 u8 wqe_inline_mode[0x2]; 1156 u8 rss_ind_tbl_cap[0x4]; 1157 u8 reg_umr_sq[0x1]; 1158 u8 scatter_fcs[0x1]; 1159 u8 enhanced_multi_pkt_send_wqe[0x1]; 1160 u8 tunnel_lso_const_out_ip_id[0x1]; 1161 u8 tunnel_lro_gre[0x1]; 1162 u8 tunnel_lro_vxlan[0x1]; 1163 u8 tunnel_statless_gre[0x1]; 1164 u8 tunnel_stateless_vxlan[0x1]; 1165 1166 u8 swp[0x1]; 1167 u8 swp_csum[0x1]; 1168 u8 swp_lso[0x1]; 1169 u8 reserved_2[0x1b]; 1170 u8 max_geneve_opt_len[0x1]; 1171 u8 tunnel_stateless_geneve_rx[0x1]; 1172 1173 u8 reserved_3[0x10]; 1174 u8 lro_min_mss_size[0x10]; 1175 1176 u8 reserved_4[0x120]; 1177 1178 u8 lro_timer_supported_periods[4][0x20]; 1179 1180 u8 reserved_5[0x600]; 1181 }; 1182 1183 enum { 1184 MLX5_ROCE_CAP_L3_TYPE_GRH = 0x1, 1185 MLX5_ROCE_CAP_L3_TYPE_IPV4 = 0x2, 1186 MLX5_ROCE_CAP_L3_TYPE_IPV6 = 0x4, 1187 }; 1188 1189 enum { 1190 MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1191 MLX5_QP_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1192 MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1193 }; 1194 1195 struct mlx5_ifc_roce_cap_bits { 1196 u8 roce_apm[0x1]; 1197 u8 rts2rts_primary_eth_prio[0x1]; 1198 u8 roce_rx_allow_untagged[0x1]; 1199 u8 rts2rts_src_addr_index_for_vlan_valid_vlan_id[0x1]; 1200 u8 reserved_at_4[0x1a]; 1201 u8 qp_ts_format[0x2]; 1202 1203 u8 reserved_1[0x60]; 1204 1205 u8 reserved_2[0xc]; 1206 u8 l3_type[0x4]; 1207 u8 reserved_3[0x8]; 1208 u8 roce_version[0x8]; 1209 1210 u8 reserved_4[0x10]; 1211 u8 r_roce_dest_udp_port[0x10]; 1212 1213 u8 r_roce_max_src_udp_port[0x10]; 1214 u8 r_roce_min_src_udp_port[0x10]; 1215 1216 u8 reserved_5[0x10]; 1217 u8 roce_address_table_size[0x10]; 1218 1219 u8 reserved_6[0x700]; 1220 }; 1221 1222 struct mlx5_ifc_device_event_cap_bits { 1223 u8 user_affiliated_events[4][0x40]; 1224 1225 u8 user_unaffiliated_events[4][0x40]; 1226 }; 1227 1228 enum { 1229 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x1, 1230 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1231 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1232 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1233 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1234 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1235 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1236 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1237 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1238 }; 1239 1240 enum { 1241 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1242 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1243 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1244 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1245 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1246 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1247 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1248 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1249 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1250 }; 1251 1252 struct mlx5_ifc_atomic_caps_bits { 1253 u8 reserved_0[0x40]; 1254 1255 u8 atomic_req_8B_endianess_mode[0x2]; 1256 u8 reserved_1[0x4]; 1257 u8 supported_atomic_req_8B_endianess_mode_1[0x1]; 1258 1259 u8 reserved_2[0x19]; 1260 1261 u8 reserved_3[0x20]; 1262 1263 u8 reserved_4[0x10]; 1264 u8 atomic_operations[0x10]; 1265 1266 u8 reserved_5[0x10]; 1267 u8 atomic_size_qp[0x10]; 1268 1269 u8 reserved_6[0x10]; 1270 u8 atomic_size_dc[0x10]; 1271 1272 u8 reserved_7[0x720]; 1273 }; 1274 1275 struct mlx5_ifc_odp_cap_bits { 1276 u8 reserved_0[0x40]; 1277 1278 u8 sig[0x1]; 1279 u8 reserved_1[0x1f]; 1280 1281 u8 reserved_2[0x20]; 1282 1283 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1284 1285 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1286 1287 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1288 1289 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1290 1291 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1292 1293 u8 reserved_3[0x6e0]; 1294 }; 1295 1296 enum { 1297 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1298 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1299 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1300 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1301 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1302 }; 1303 1304 enum { 1305 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1306 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1307 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1308 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1309 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1310 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1311 }; 1312 1313 enum { 1314 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1315 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1316 }; 1317 1318 enum { 1319 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1320 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1321 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1322 }; 1323 1324 enum { 1325 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1326 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1327 }; 1328 1329 enum { 1330 MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1331 MLX5_SQ_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1332 MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1333 }; 1334 1335 enum { 1336 MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1337 MLX5_RQ_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1338 MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1339 }; 1340 1341 struct mlx5_ifc_cmd_hca_cap_bits { 1342 u8 reserved_0[0x20]; 1343 1344 u8 hca_cap_2[0x1]; 1345 u8 create_lag_when_not_master_up[0x1]; 1346 u8 dtor[0x1]; 1347 u8 event_on_vhca_state_teardown_request[0x1]; 1348 u8 event_on_vhca_state_in_use[0x1]; 1349 u8 event_on_vhca_state_active[0x1]; 1350 u8 event_on_vhca_state_allocated[0x1]; 1351 u8 event_on_vhca_state_invalid[0x1]; 1352 u8 reserved_at_28[0x8]; 1353 u8 vhca_id[0x10]; 1354 1355 u8 reserved_at_40[0x40]; 1356 1357 u8 log_max_srq_sz[0x8]; 1358 u8 log_max_qp_sz[0x8]; 1359 u8 event_cap[0x1]; 1360 u8 reserved_1[0xa]; 1361 u8 log_max_qp[0x5]; 1362 1363 u8 reserved_2[0xb]; 1364 u8 log_max_srq[0x5]; 1365 u8 reserved_3[0x10]; 1366 1367 u8 reserved_4[0x8]; 1368 u8 log_max_cq_sz[0x8]; 1369 u8 relaxed_ordering_write_umr[0x1]; 1370 u8 relaxed_ordering_read_umr[0x1]; 1371 u8 reserved_5[0x9]; 1372 u8 log_max_cq[0x5]; 1373 1374 u8 log_max_eq_sz[0x8]; 1375 u8 relaxed_ordering_write[0x1]; 1376 u8 relaxed_ordering_read[0x1]; 1377 u8 log_max_mkey[0x6]; 1378 u8 reserved_7[0xb]; 1379 u8 fast_teardown[0x1]; 1380 u8 log_max_eq[0x4]; 1381 1382 u8 max_indirection[0x8]; 1383 u8 reserved_8[0x1]; 1384 u8 log_max_mrw_sz[0x7]; 1385 u8 force_teardown[0x1]; 1386 u8 reserved_9[0x1]; 1387 u8 log_max_bsf_list_size[0x6]; 1388 u8 reserved_10[0x2]; 1389 u8 log_max_klm_list_size[0x6]; 1390 1391 u8 reserved_11[0xa]; 1392 u8 log_max_ra_req_dc[0x6]; 1393 u8 reserved_12[0xa]; 1394 u8 log_max_ra_res_dc[0x6]; 1395 1396 u8 reserved_13[0xa]; 1397 u8 log_max_ra_req_qp[0x6]; 1398 u8 reserved_14[0xa]; 1399 u8 log_max_ra_res_qp[0x6]; 1400 1401 u8 pad_cap[0x1]; 1402 u8 cc_query_allowed[0x1]; 1403 u8 cc_modify_allowed[0x1]; 1404 u8 start_pad[0x1]; 1405 u8 cache_line_128byte[0x1]; 1406 u8 reserved_at_165[0xa]; 1407 u8 qcam_reg[0x1]; 1408 u8 gid_table_size[0x10]; 1409 1410 u8 out_of_seq_cnt[0x1]; 1411 u8 vport_counters[0x1]; 1412 u8 retransmission_q_counters[0x1]; 1413 u8 debug[0x1]; 1414 u8 modify_rq_counters_set_id[0x1]; 1415 u8 rq_delay_drop[0x1]; 1416 u8 max_qp_cnt[0xa]; 1417 u8 pkey_table_size[0x10]; 1418 1419 u8 vport_group_manager[0x1]; 1420 u8 vhca_group_manager[0x1]; 1421 u8 ib_virt[0x1]; 1422 u8 eth_virt[0x1]; 1423 u8 reserved_17[0x1]; 1424 u8 ets[0x1]; 1425 u8 nic_flow_table[0x1]; 1426 u8 eswitch_flow_table[0x1]; 1427 u8 reserved_18[0x1]; 1428 u8 mcam_reg[0x1]; 1429 u8 pcam_reg[0x1]; 1430 u8 local_ca_ack_delay[0x5]; 1431 u8 port_module_event[0x1]; 1432 u8 reserved_19[0x5]; 1433 u8 port_type[0x2]; 1434 u8 num_ports[0x8]; 1435 1436 u8 snapshot[0x1]; 1437 u8 reserved_20[0x2]; 1438 u8 log_max_msg[0x5]; 1439 u8 reserved_21[0x4]; 1440 u8 max_tc[0x4]; 1441 u8 temp_warn_event[0x1]; 1442 u8 dcbx[0x1]; 1443 u8 general_notification_event[0x1]; 1444 u8 reserved_at_1d3[0x2]; 1445 u8 fpga[0x1]; 1446 u8 rol_s[0x1]; 1447 u8 rol_g[0x1]; 1448 u8 reserved_23[0x1]; 1449 u8 wol_s[0x1]; 1450 u8 wol_g[0x1]; 1451 u8 wol_a[0x1]; 1452 u8 wol_b[0x1]; 1453 u8 wol_m[0x1]; 1454 u8 wol_u[0x1]; 1455 u8 wol_p[0x1]; 1456 1457 u8 stat_rate_support[0x10]; 1458 u8 reserved_24[0xc]; 1459 u8 cqe_version[0x4]; 1460 1461 u8 compact_address_vector[0x1]; 1462 u8 striding_rq[0x1]; 1463 u8 reserved_25[0x1]; 1464 u8 ipoib_enhanced_offloads[0x1]; 1465 u8 ipoib_ipoib_offloads[0x1]; 1466 u8 reserved_26[0x8]; 1467 u8 dc_connect_qp[0x1]; 1468 u8 dc_cnak_trace[0x1]; 1469 u8 drain_sigerr[0x1]; 1470 u8 cmdif_checksum[0x2]; 1471 u8 sigerr_cqe[0x1]; 1472 u8 reserved_27[0x1]; 1473 u8 wq_signature[0x1]; 1474 u8 sctr_data_cqe[0x1]; 1475 u8 reserved_28[0x1]; 1476 u8 sho[0x1]; 1477 u8 tph[0x1]; 1478 u8 rf[0x1]; 1479 u8 dct[0x1]; 1480 u8 qos[0x1]; 1481 u8 eth_net_offloads[0x1]; 1482 u8 roce[0x1]; 1483 u8 atomic[0x1]; 1484 u8 reserved_30[0x1]; 1485 1486 u8 cq_oi[0x1]; 1487 u8 cq_resize[0x1]; 1488 u8 cq_moderation[0x1]; 1489 u8 cq_period_mode_modify[0x1]; 1490 u8 cq_invalidate[0x1]; 1491 u8 reserved_at_225[0x1]; 1492 u8 cq_eq_remap[0x1]; 1493 u8 pg[0x1]; 1494 u8 block_lb_mc[0x1]; 1495 u8 exponential_backoff[0x1]; 1496 u8 scqe_break_moderation[0x1]; 1497 u8 cq_period_start_from_cqe[0x1]; 1498 u8 cd[0x1]; 1499 u8 atm[0x1]; 1500 u8 apm[0x1]; 1501 u8 imaicl[0x1]; 1502 u8 reserved_32[0x6]; 1503 u8 qkv[0x1]; 1504 u8 pkv[0x1]; 1505 u8 set_deth_sqpn[0x1]; 1506 u8 reserved_33[0x3]; 1507 u8 xrc[0x1]; 1508 u8 ud[0x1]; 1509 u8 uc[0x1]; 1510 u8 rc[0x1]; 1511 1512 u8 uar_4k[0x1]; 1513 u8 reserved_at_241[0x9]; 1514 u8 uar_sz[0x6]; 1515 u8 reserved_35[0x8]; 1516 u8 log_pg_sz[0x8]; 1517 1518 u8 bf[0x1]; 1519 u8 driver_version[0x1]; 1520 u8 pad_tx_eth_packet[0x1]; 1521 u8 reserved_36[0x8]; 1522 u8 log_bf_reg_size[0x5]; 1523 u8 reserved_37[0x10]; 1524 1525 u8 num_of_diagnostic_counters[0x10]; 1526 u8 max_wqe_sz_sq[0x10]; 1527 1528 u8 reserved_38[0x10]; 1529 u8 max_wqe_sz_rq[0x10]; 1530 1531 u8 reserved_39[0x10]; 1532 u8 max_wqe_sz_sq_dc[0x10]; 1533 1534 u8 reserved_40[0x7]; 1535 u8 max_qp_mcg[0x19]; 1536 1537 u8 reserved_41[0x10]; 1538 u8 flow_counter_bulk_alloc[0x8]; 1539 u8 log_max_mcg[0x8]; 1540 1541 u8 reserved_42[0x3]; 1542 u8 log_max_transport_domain[0x5]; 1543 u8 reserved_43[0x3]; 1544 u8 log_max_pd[0x5]; 1545 u8 reserved_44[0xb]; 1546 u8 log_max_xrcd[0x5]; 1547 1548 u8 nic_receive_steering_discard[0x1]; 1549 u8 reserved_45[0x7]; 1550 u8 log_max_flow_counter_bulk[0x8]; 1551 u8 max_flow_counter[0x10]; 1552 1553 u8 reserved_46[0x3]; 1554 u8 log_max_rq[0x5]; 1555 u8 reserved_47[0x3]; 1556 u8 log_max_sq[0x5]; 1557 u8 reserved_48[0x3]; 1558 u8 log_max_tir[0x5]; 1559 u8 reserved_49[0x3]; 1560 u8 log_max_tis[0x5]; 1561 1562 u8 basic_cyclic_rcv_wqe[0x1]; 1563 u8 reserved_50[0x2]; 1564 u8 log_max_rmp[0x5]; 1565 u8 reserved_51[0x3]; 1566 u8 log_max_rqt[0x5]; 1567 u8 reserved_52[0x3]; 1568 u8 log_max_rqt_size[0x5]; 1569 u8 reserved_53[0x3]; 1570 u8 log_max_tis_per_sq[0x5]; 1571 1572 u8 reserved_54[0x3]; 1573 u8 log_max_stride_sz_rq[0x5]; 1574 u8 reserved_55[0x3]; 1575 u8 log_min_stride_sz_rq[0x5]; 1576 u8 reserved_56[0x3]; 1577 u8 log_max_stride_sz_sq[0x5]; 1578 u8 reserved_57[0x3]; 1579 u8 log_min_stride_sz_sq[0x5]; 1580 1581 u8 reserved_58[0x1b]; 1582 u8 log_max_wq_sz[0x5]; 1583 1584 u8 nic_vport_change_event[0x1]; 1585 u8 disable_local_lb_uc[0x1]; 1586 u8 disable_local_lb_mc[0x1]; 1587 u8 reserved_59[0x8]; 1588 u8 log_max_vlan_list[0x5]; 1589 u8 reserved_60[0x3]; 1590 u8 log_max_current_mc_list[0x5]; 1591 u8 reserved_61[0x3]; 1592 u8 log_max_current_uc_list[0x5]; 1593 1594 u8 general_obj_types[0x40]; 1595 1596 u8 sq_ts_format[0x2]; 1597 u8 rq_ts_format[0x2]; 1598 u8 reserved_at_444[0x4]; 1599 u8 create_qp_start_hint[0x18]; 1600 1601 u8 reserved_at_460[0x3]; 1602 u8 log_max_uctx[0x5]; 1603 u8 reserved_at_468[0x2]; 1604 u8 ipsec_offload[0x1]; 1605 u8 log_max_umem[0x5]; 1606 u8 max_num_eqs[0x10]; 1607 1608 u8 reserved_at_480[0x1]; 1609 u8 tls_tx[0x1]; 1610 u8 tls_rx[0x1]; 1611 u8 log_max_l2_table[0x5]; 1612 u8 reserved_64[0x8]; 1613 u8 log_uar_page_sz[0x10]; 1614 1615 u8 reserved_65[0x20]; 1616 1617 u8 device_frequency_mhz[0x20]; 1618 1619 u8 device_frequency_khz[0x20]; 1620 1621 u8 reserved_at_500[0x20]; 1622 u8 num_of_uars_per_page[0x20]; 1623 u8 reserved_at_540[0x40]; 1624 1625 u8 log_max_atomic_size_qp[0x8]; 1626 u8 reserved_67[0x10]; 1627 u8 log_max_atomic_size_dc[0x8]; 1628 1629 u8 reserved_at_5a0[0x13]; 1630 u8 log_max_dek[0x5]; 1631 u8 reserved_at_5b8[0x4]; 1632 u8 mini_cqe_resp_stride_index[0x1]; 1633 u8 cqe_128_always[0x1]; 1634 u8 cqe_compression_128b[0x1]; 1635 1636 u8 cqe_compression[0x1]; 1637 1638 u8 cqe_compression_timeout[0x10]; 1639 u8 cqe_compression_max_num[0x10]; 1640 1641 u8 reserved_5e0[0xc0]; 1642 1643 u8 uctx_cap[0x20]; 1644 1645 u8 reserved_6c0[0xc0]; 1646 1647 u8 vhca_tunnel_commands[0x40]; 1648 u8 reserved_at_7c0[0x40]; 1649 }; 1650 1651 struct mlx5_ifc_cmd_hca_cap_2_bits { 1652 u8 reserved_at_0[0x80]; 1653 1654 u8 migratable[0x1]; 1655 u8 reserved_at_81[0x1f]; 1656 1657 u8 max_reformat_insert_size[0x8]; 1658 u8 max_reformat_insert_offset[0x8]; 1659 u8 max_reformat_remove_size[0x8]; 1660 u8 max_reformat_remove_offset[0x8]; 1661 1662 u8 reserved_at_c0[0x8]; 1663 u8 migration_multi_load[0x1]; 1664 u8 migration_tracking_state[0x1]; 1665 u8 reserved_at_ca[0x16]; 1666 1667 u8 reserved_at_e0[0xc0]; 1668 1669 u8 flow_table_type_2_type[0x8]; 1670 u8 reserved_at_1a8[0x3]; 1671 u8 log_min_mkey_entity_size[0x5]; 1672 u8 reserved_at_1b0[0x10]; 1673 1674 u8 reserved_at_1c0[0x60]; 1675 1676 u8 reserved_at_220[0x1]; 1677 u8 sw_vhca_id_valid[0x1]; 1678 u8 sw_vhca_id[0xe]; 1679 u8 reserved_at_230[0x10]; 1680 1681 u8 reserved_at_240[0xb]; 1682 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 1683 u8 reserved_at_250[0x10]; 1684 1685 u8 reserved_at_260[0x5a0]; 1686 }; 1687 1688 enum mlx5_ifc_flow_destination_type { 1689 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1690 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1691 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 1692 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 1693 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 1694 MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE = 0xA, 1695 }; 1696 1697 enum mlx5_flow_table_miss_action { 1698 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1699 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 1700 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 1701 }; 1702 1703 struct mlx5_ifc_extended_dest_format_bits { 1704 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1705 1706 u8 packet_reformat_id[0x20]; 1707 1708 u8 reserved_at_60[0x20]; 1709 }; 1710 1711 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1712 struct mlx5_ifc_dest_format_struct_bits dest_format_struct; 1713 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1714 u8 reserved_0[0x40]; 1715 }; 1716 1717 struct mlx5_ifc_fte_match_param_bits { 1718 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1719 1720 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1721 1722 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1723 1724 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1725 1726 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1727 1728 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 1729 1730 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 1731 1732 u8 reserved_at_e00[0x200]; 1733 }; 1734 1735 enum { 1736 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1737 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1738 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1739 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1740 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1741 }; 1742 1743 struct mlx5_ifc_rx_hash_field_select_bits { 1744 u8 l3_prot_type[0x1]; 1745 u8 l4_prot_type[0x1]; 1746 u8 selected_fields[0x1e]; 1747 }; 1748 1749 struct mlx5_ifc_tls_capabilities_bits { 1750 u8 tls_1_2_aes_gcm_128[0x1]; 1751 u8 tls_1_3_aes_gcm_128[0x1]; 1752 u8 tls_1_2_aes_gcm_256[0x1]; 1753 u8 tls_1_3_aes_gcm_256[0x1]; 1754 u8 reserved_at_4[0x1c]; 1755 1756 u8 reserved_at_20[0x7e0]; 1757 }; 1758 1759 enum { 1760 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1761 MLX5_WQ_TYPE_CYCLIC = 0x1, 1762 MLX5_WQ_TYPE_STRQ_LINKED_LIST = 0x2, 1763 MLX5_WQ_TYPE_STRQ_CYCLIC = 0x3, 1764 }; 1765 1766 enum rq_type { 1767 RQ_TYPE_NONE, 1768 RQ_TYPE_STRIDE, 1769 }; 1770 1771 enum { 1772 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1773 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1774 }; 1775 1776 struct mlx5_ifc_wq_bits { 1777 u8 wq_type[0x4]; 1778 u8 wq_signature[0x1]; 1779 u8 end_padding_mode[0x2]; 1780 u8 cd_slave[0x1]; 1781 u8 reserved_0[0x18]; 1782 1783 u8 hds_skip_first_sge[0x1]; 1784 u8 log2_hds_buf_size[0x3]; 1785 u8 reserved_1[0x7]; 1786 u8 page_offset[0x5]; 1787 u8 lwm[0x10]; 1788 1789 u8 reserved_2[0x8]; 1790 u8 pd[0x18]; 1791 1792 u8 reserved_3[0x8]; 1793 u8 uar_page[0x18]; 1794 1795 u8 dbr_addr[0x40]; 1796 1797 u8 hw_counter[0x20]; 1798 1799 u8 sw_counter[0x20]; 1800 1801 u8 reserved_4[0xc]; 1802 u8 log_wq_stride[0x4]; 1803 u8 reserved_5[0x3]; 1804 u8 log_wq_pg_sz[0x5]; 1805 u8 reserved_6[0x3]; 1806 u8 log_wq_sz[0x5]; 1807 1808 u8 dbr_umem_valid[0x1]; 1809 u8 wq_umem_valid[0x1]; 1810 u8 reserved_7[0x13]; 1811 u8 single_wqe_log_num_of_strides[0x3]; 1812 u8 two_byte_shift_en[0x1]; 1813 u8 reserved_8[0x4]; 1814 u8 single_stride_log_num_of_bytes[0x3]; 1815 1816 u8 reserved_9[0x4c0]; 1817 1818 struct mlx5_ifc_cmd_pas_bits pas[0]; 1819 }; 1820 1821 struct mlx5_ifc_rq_num_bits { 1822 u8 reserved_0[0x8]; 1823 u8 rq_num[0x18]; 1824 }; 1825 1826 struct mlx5_ifc_mac_address_layout_bits { 1827 u8 reserved_0[0x10]; 1828 u8 mac_addr_47_32[0x10]; 1829 1830 u8 mac_addr_31_0[0x20]; 1831 }; 1832 1833 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 1834 u8 reserved_0[0xa0]; 1835 1836 u8 min_time_between_cnps[0x20]; 1837 1838 u8 reserved_1[0x12]; 1839 u8 cnp_dscp[0x6]; 1840 u8 reserved_2[0x4]; 1841 u8 cnp_prio_mode[0x1]; 1842 u8 cnp_802p_prio[0x3]; 1843 1844 u8 reserved_3[0x720]; 1845 }; 1846 1847 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 1848 u8 reserved_0[0x60]; 1849 1850 u8 reserved_1[0x4]; 1851 u8 clamp_tgt_rate[0x1]; 1852 u8 reserved_2[0x3]; 1853 u8 clamp_tgt_rate_after_time_inc[0x1]; 1854 u8 reserved_3[0x17]; 1855 1856 u8 reserved_4[0x20]; 1857 1858 u8 rpg_time_reset[0x20]; 1859 1860 u8 rpg_byte_reset[0x20]; 1861 1862 u8 rpg_threshold[0x20]; 1863 1864 u8 rpg_max_rate[0x20]; 1865 1866 u8 rpg_ai_rate[0x20]; 1867 1868 u8 rpg_hai_rate[0x20]; 1869 1870 u8 rpg_gd[0x20]; 1871 1872 u8 rpg_min_dec_fac[0x20]; 1873 1874 u8 rpg_min_rate[0x20]; 1875 1876 u8 reserved_5[0xe0]; 1877 1878 u8 rate_to_set_on_first_cnp[0x20]; 1879 1880 u8 dce_tcp_g[0x20]; 1881 1882 u8 dce_tcp_rtt[0x20]; 1883 1884 u8 rate_reduce_monitor_period[0x20]; 1885 1886 u8 reserved_6[0x20]; 1887 1888 u8 initial_alpha_value[0x20]; 1889 1890 u8 reserved_7[0x4a0]; 1891 }; 1892 1893 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 1894 u8 reserved_0[0x80]; 1895 1896 u8 rppp_max_rps[0x20]; 1897 1898 u8 rpg_time_reset[0x20]; 1899 1900 u8 rpg_byte_reset[0x20]; 1901 1902 u8 rpg_threshold[0x20]; 1903 1904 u8 rpg_max_rate[0x20]; 1905 1906 u8 rpg_ai_rate[0x20]; 1907 1908 u8 rpg_hai_rate[0x20]; 1909 1910 u8 rpg_gd[0x20]; 1911 1912 u8 rpg_min_dec_fac[0x20]; 1913 1914 u8 rpg_min_rate[0x20]; 1915 1916 u8 reserved_1[0x640]; 1917 }; 1918 1919 enum { 1920 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 1921 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 1922 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 1923 }; 1924 1925 struct mlx5_ifc_resize_field_select_bits { 1926 u8 resize_field_select[0x20]; 1927 }; 1928 1929 enum { 1930 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 1931 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 1932 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 1933 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 1934 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD_MODE = 0x10, 1935 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_STATUS = 0x20, 1936 }; 1937 1938 struct mlx5_ifc_modify_field_select_bits { 1939 u8 modify_field_select[0x20]; 1940 }; 1941 1942 struct mlx5_ifc_field_select_r_roce_np_bits { 1943 u8 field_select_r_roce_np[0x20]; 1944 }; 1945 1946 enum { 1947 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE = 0x2, 1948 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE_AFTER_TIME_INC = 0x4, 1949 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_TIME_RESET = 0x8, 1950 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_BYTE_RESET = 0x10, 1951 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_THRESHOLD = 0x20, 1952 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MAX_RATE = 0x40, 1953 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_AI_RATE = 0x80, 1954 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_HAI_RATE = 0x100, 1955 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_DEC_FAC = 0x200, 1956 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_RATE = 0x400, 1957 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_TO_SET_ON_FIRST_CNP = 0x800, 1958 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_G = 0x1000, 1959 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_RTT = 0x2000, 1960 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_REDUCE_MONITOR_PERIOD = 0x4000, 1961 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_INITIAL_ALPHA_VALUE = 0x8000, 1962 }; 1963 1964 struct mlx5_ifc_field_select_r_roce_rp_bits { 1965 u8 field_select_r_roce_rp[0x20]; 1966 }; 1967 1968 enum { 1969 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 1970 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 1971 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 1972 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 1973 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 1974 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 1975 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 1976 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 1977 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 1978 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 1979 }; 1980 1981 struct mlx5_ifc_field_select_802_1qau_rp_bits { 1982 u8 field_select_8021qaurp[0x20]; 1983 }; 1984 1985 struct mlx5_ifc_pptb_reg_bits { 1986 u8 reserved_at_0[0x2]; 1987 u8 mm[0x2]; 1988 u8 reserved_at_4[0x4]; 1989 u8 local_port[0x8]; 1990 u8 reserved_at_10[0x6]; 1991 u8 cm[0x1]; 1992 u8 um[0x1]; 1993 u8 pm[0x8]; 1994 1995 u8 prio_x_buff[0x20]; 1996 1997 u8 pm_msb[0x8]; 1998 u8 reserved_at_48[0x10]; 1999 u8 ctrl_buff[0x4]; 2000 u8 untagged_buff[0x4]; 2001 }; 2002 2003 struct mlx5_ifc_dcbx_app_reg_bits { 2004 u8 reserved_0[0x8]; 2005 u8 port_number[0x8]; 2006 u8 reserved_1[0x10]; 2007 2008 u8 reserved_2[0x1a]; 2009 u8 num_app_prio[0x6]; 2010 2011 u8 reserved_3[0x40]; 2012 2013 struct mlx5_ifc_application_prio_entry_bits app_prio[0]; 2014 }; 2015 2016 struct mlx5_ifc_dcbx_param_reg_bits { 2017 u8 dcbx_cee_cap[0x1]; 2018 u8 dcbx_ieee_cap[0x1]; 2019 u8 dcbx_standby_cap[0x1]; 2020 u8 reserved_0[0x5]; 2021 u8 port_number[0x8]; 2022 u8 reserved_1[0xa]; 2023 u8 max_application_table_size[0x6]; 2024 2025 u8 reserved_2[0x15]; 2026 u8 version_oper[0x3]; 2027 u8 reserved_3[0x5]; 2028 u8 version_admin[0x3]; 2029 2030 u8 willing_admin[0x1]; 2031 u8 reserved_4[0x3]; 2032 u8 pfc_cap_oper[0x4]; 2033 u8 reserved_5[0x4]; 2034 u8 pfc_cap_admin[0x4]; 2035 u8 reserved_6[0x4]; 2036 u8 num_of_tc_oper[0x4]; 2037 u8 reserved_7[0x4]; 2038 u8 num_of_tc_admin[0x4]; 2039 2040 u8 remote_willing[0x1]; 2041 u8 reserved_8[0x3]; 2042 u8 remote_pfc_cap[0x4]; 2043 u8 reserved_9[0x14]; 2044 u8 remote_num_of_tc[0x4]; 2045 2046 u8 reserved_10[0x18]; 2047 u8 error[0x8]; 2048 2049 u8 reserved_11[0x160]; 2050 }; 2051 2052 struct mlx5_ifc_qhll_bits { 2053 u8 reserved_at_0[0x8]; 2054 u8 local_port[0x8]; 2055 u8 reserved_at_10[0x10]; 2056 2057 u8 reserved_at_20[0x1b]; 2058 u8 hll_time[0x5]; 2059 2060 u8 stall_en[0x1]; 2061 u8 reserved_at_41[0x1c]; 2062 u8 stall_cnt[0x3]; 2063 }; 2064 2065 struct mlx5_ifc_qetcr_reg_bits { 2066 u8 operation_type[0x2]; 2067 u8 cap_local_admin[0x1]; 2068 u8 cap_remote_admin[0x1]; 2069 u8 reserved_0[0x4]; 2070 u8 port_number[0x8]; 2071 u8 reserved_1[0x10]; 2072 2073 u8 reserved_2[0x20]; 2074 2075 u8 tc[8][0x40]; 2076 2077 u8 global_configuration[0x40]; 2078 }; 2079 2080 struct mlx5_ifc_nodnic_ring_config_reg_bits { 2081 u8 queue_address_63_32[0x20]; 2082 2083 u8 queue_address_31_12[0x14]; 2084 u8 reserved_0[0x6]; 2085 u8 log_size[0x6]; 2086 2087 struct mlx5_ifc_nodnic_ring_doorbell_bits doorbell; 2088 2089 u8 reserved_1[0x8]; 2090 u8 queue_number[0x18]; 2091 2092 u8 q_key[0x20]; 2093 2094 u8 reserved_2[0x10]; 2095 u8 pkey_index[0x10]; 2096 2097 u8 reserved_3[0x40]; 2098 }; 2099 2100 struct mlx5_ifc_nodnic_cq_arming_word_bits { 2101 u8 reserved_0[0x8]; 2102 u8 cq_ci[0x10]; 2103 u8 reserved_1[0x8]; 2104 }; 2105 2106 enum { 2107 MLX5_NODNIC_EVENT_WORD_LINK_TYPE_INFINIBAND = 0x0, 2108 MLX5_NODNIC_EVENT_WORD_LINK_TYPE_ETHERNET = 0x1, 2109 }; 2110 2111 enum { 2112 MLX5_NODNIC_EVENT_WORD_PORT_STATE_DOWN = 0x0, 2113 MLX5_NODNIC_EVENT_WORD_PORT_STATE_INITIALIZE = 0x1, 2114 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ARMED = 0x2, 2115 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ACTIVE = 0x3, 2116 }; 2117 2118 struct mlx5_ifc_nodnic_event_word_bits { 2119 u8 driver_reset_needed[0x1]; 2120 u8 port_management_change_event[0x1]; 2121 u8 reserved_0[0x19]; 2122 u8 link_type[0x1]; 2123 u8 port_state[0x4]; 2124 }; 2125 2126 struct mlx5_ifc_nic_vport_change_event_bits { 2127 u8 reserved_0[0x10]; 2128 u8 vport_num[0x10]; 2129 2130 u8 reserved_1[0xc0]; 2131 }; 2132 2133 struct mlx5_ifc_pages_req_event_bits { 2134 u8 reserved_0[0x10]; 2135 u8 function_id[0x10]; 2136 2137 u8 num_pages[0x20]; 2138 2139 u8 reserved_1[0xa0]; 2140 }; 2141 2142 struct mlx5_ifc_cmd_inter_comp_event_bits { 2143 u8 command_completion_vector[0x20]; 2144 2145 u8 reserved_0[0xc0]; 2146 }; 2147 2148 struct mlx5_ifc_stall_vl_event_bits { 2149 u8 reserved_0[0x18]; 2150 u8 port_num[0x1]; 2151 u8 reserved_1[0x3]; 2152 u8 vl[0x4]; 2153 2154 u8 reserved_2[0xa0]; 2155 }; 2156 2157 struct mlx5_ifc_db_bf_congestion_event_bits { 2158 u8 event_subtype[0x8]; 2159 u8 reserved_0[0x8]; 2160 u8 congestion_level[0x8]; 2161 u8 reserved_1[0x8]; 2162 2163 u8 reserved_2[0xa0]; 2164 }; 2165 2166 struct mlx5_ifc_gpio_event_bits { 2167 u8 reserved_0[0x60]; 2168 2169 u8 gpio_event_hi[0x20]; 2170 2171 u8 gpio_event_lo[0x20]; 2172 2173 u8 reserved_1[0x40]; 2174 }; 2175 2176 struct mlx5_ifc_port_state_change_event_bits { 2177 u8 reserved_0[0x40]; 2178 2179 u8 port_num[0x4]; 2180 u8 reserved_1[0x1c]; 2181 2182 u8 reserved_2[0x80]; 2183 }; 2184 2185 struct mlx5_ifc_dropped_packet_logged_bits { 2186 u8 reserved_0[0xe0]; 2187 }; 2188 2189 enum { 2190 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 2191 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 2192 }; 2193 2194 struct mlx5_ifc_cq_error_bits { 2195 u8 reserved_0[0x8]; 2196 u8 cqn[0x18]; 2197 2198 u8 reserved_1[0x20]; 2199 2200 u8 reserved_2[0x18]; 2201 u8 syndrome[0x8]; 2202 2203 u8 reserved_3[0x80]; 2204 }; 2205 2206 struct mlx5_ifc_rdma_page_fault_event_bits { 2207 u8 bytes_commited[0x20]; 2208 2209 u8 r_key[0x20]; 2210 2211 u8 reserved_0[0x10]; 2212 u8 packet_len[0x10]; 2213 2214 u8 rdma_op_len[0x20]; 2215 2216 u8 rdma_va[0x40]; 2217 2218 u8 reserved_1[0x5]; 2219 u8 rdma[0x1]; 2220 u8 write[0x1]; 2221 u8 requestor[0x1]; 2222 u8 qp_number[0x18]; 2223 }; 2224 2225 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 2226 u8 bytes_committed[0x20]; 2227 2228 u8 reserved_0[0x10]; 2229 u8 wqe_index[0x10]; 2230 2231 u8 reserved_1[0x10]; 2232 u8 len[0x10]; 2233 2234 u8 reserved_2[0x60]; 2235 2236 u8 reserved_3[0x5]; 2237 u8 rdma[0x1]; 2238 u8 write_read[0x1]; 2239 u8 requestor[0x1]; 2240 u8 qpn[0x18]; 2241 }; 2242 2243 enum { 2244 MLX5_QP_EVENTS_TYPE_QP = 0x0, 2245 MLX5_QP_EVENTS_TYPE_RQ = 0x1, 2246 MLX5_QP_EVENTS_TYPE_SQ = 0x2, 2247 }; 2248 2249 struct mlx5_ifc_qp_events_bits { 2250 u8 reserved_0[0xa0]; 2251 2252 u8 type[0x8]; 2253 u8 reserved_1[0x18]; 2254 2255 u8 reserved_2[0x8]; 2256 u8 qpn_rqn_sqn[0x18]; 2257 }; 2258 2259 struct mlx5_ifc_dct_events_bits { 2260 u8 reserved_0[0xc0]; 2261 2262 u8 reserved_1[0x8]; 2263 u8 dct_number[0x18]; 2264 }; 2265 2266 struct mlx5_ifc_comp_event_bits { 2267 u8 reserved_0[0xc0]; 2268 2269 u8 reserved_1[0x8]; 2270 u8 cq_number[0x18]; 2271 }; 2272 2273 struct mlx5_ifc_fw_version_bits { 2274 u8 major[0x10]; 2275 u8 reserved_0[0x10]; 2276 2277 u8 minor[0x10]; 2278 u8 subminor[0x10]; 2279 2280 u8 second[0x8]; 2281 u8 minute[0x8]; 2282 u8 hour[0x8]; 2283 u8 reserved_1[0x8]; 2284 2285 u8 year[0x10]; 2286 u8 month[0x8]; 2287 u8 day[0x8]; 2288 }; 2289 2290 enum { 2291 MLX5_QPC_STATE_RST = 0x0, 2292 MLX5_QPC_STATE_INIT = 0x1, 2293 MLX5_QPC_STATE_RTR = 0x2, 2294 MLX5_QPC_STATE_RTS = 0x3, 2295 MLX5_QPC_STATE_SQER = 0x4, 2296 MLX5_QPC_STATE_SQD = 0x5, 2297 MLX5_QPC_STATE_ERR = 0x6, 2298 MLX5_QPC_STATE_SUSPENDED = 0x9, 2299 }; 2300 2301 enum { 2302 MLX5_QPC_ST_RC = 0x0, 2303 MLX5_QPC_ST_UC = 0x1, 2304 MLX5_QPC_ST_UD = 0x2, 2305 MLX5_QPC_ST_XRC = 0x3, 2306 MLX5_QPC_ST_DCI = 0x5, 2307 MLX5_QPC_ST_QP0 = 0x7, 2308 MLX5_QPC_ST_QP1 = 0x8, 2309 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 2310 MLX5_QPC_ST_REG_UMR = 0xc, 2311 }; 2312 2313 enum { 2314 MLX5_QP_PM_ARMED = 0x0, 2315 MLX5_QP_PM_REARM = 0x1, 2316 MLX5_QPC_PM_STATE_RESERVED = 0x2, 2317 MLX5_QP_PM_MIGRATED = 0x3, 2318 }; 2319 2320 enum { 2321 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 2322 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 2323 }; 2324 2325 enum { 2326 MLX5_QPC_MTU_256_BYTES = 0x1, 2327 MLX5_QPC_MTU_512_BYTES = 0x2, 2328 MLX5_QPC_MTU_1K_BYTES = 0x3, 2329 MLX5_QPC_MTU_2K_BYTES = 0x4, 2330 MLX5_QPC_MTU_4K_BYTES = 0x5, 2331 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 2332 }; 2333 2334 enum { 2335 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 2336 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 2337 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 2338 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 2339 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 2340 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 2341 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 2342 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 2343 }; 2344 2345 enum { 2346 MLX5_QPC_CS_REQ_DISABLE = 0x0, 2347 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 2348 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 2349 }; 2350 2351 enum { 2352 MLX5_QPC_CS_RES_DISABLE = 0x0, 2353 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 2354 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 2355 }; 2356 2357 enum { 2358 MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 2359 MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT = 0x1, 2360 MLX5_QPC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 2361 }; 2362 2363 struct mlx5_ifc_qpc_bits { 2364 u8 state[0x4]; 2365 u8 lag_tx_port_affinity[0x4]; 2366 u8 st[0x8]; 2367 u8 reserved_1[0x3]; 2368 u8 pm_state[0x2]; 2369 u8 reserved_2[0x7]; 2370 u8 end_padding_mode[0x2]; 2371 u8 reserved_3[0x2]; 2372 2373 u8 wq_signature[0x1]; 2374 u8 block_lb_mc[0x1]; 2375 u8 atomic_like_write_en[0x1]; 2376 u8 latency_sensitive[0x1]; 2377 u8 reserved_4[0x1]; 2378 u8 drain_sigerr[0x1]; 2379 u8 reserved_5[0x2]; 2380 u8 pd[0x18]; 2381 2382 u8 mtu[0x3]; 2383 u8 log_msg_max[0x5]; 2384 u8 reserved_6[0x1]; 2385 u8 log_rq_size[0x4]; 2386 u8 log_rq_stride[0x3]; 2387 u8 no_sq[0x1]; 2388 u8 log_sq_size[0x4]; 2389 u8 reserved_at_55[0x3]; 2390 u8 ts_format[0x2]; 2391 u8 reserved_at_5a[0x1]; 2392 u8 rlky[0x1]; 2393 u8 ulp_stateless_offload_mode[0x4]; 2394 2395 u8 counter_set_id[0x8]; 2396 u8 uar_page[0x18]; 2397 2398 u8 reserved_8[0x8]; 2399 u8 user_index[0x18]; 2400 2401 u8 reserved_9[0x3]; 2402 u8 log_page_size[0x5]; 2403 u8 remote_qpn[0x18]; 2404 2405 struct mlx5_ifc_ads_bits primary_address_path; 2406 2407 struct mlx5_ifc_ads_bits secondary_address_path; 2408 2409 u8 log_ack_req_freq[0x4]; 2410 u8 reserved_10[0x4]; 2411 u8 log_sra_max[0x3]; 2412 u8 reserved_11[0x2]; 2413 u8 retry_count[0x3]; 2414 u8 rnr_retry[0x3]; 2415 u8 reserved_12[0x1]; 2416 u8 fre[0x1]; 2417 u8 cur_rnr_retry[0x3]; 2418 u8 cur_retry_count[0x3]; 2419 u8 reserved_13[0x5]; 2420 2421 u8 reserved_14[0x20]; 2422 2423 u8 reserved_15[0x8]; 2424 u8 next_send_psn[0x18]; 2425 2426 u8 reserved_16[0x8]; 2427 u8 cqn_snd[0x18]; 2428 2429 u8 reserved_at_400[0x8]; 2430 2431 u8 deth_sqpn[0x18]; 2432 u8 reserved_17[0x20]; 2433 2434 u8 reserved_18[0x8]; 2435 u8 last_acked_psn[0x18]; 2436 2437 u8 reserved_19[0x8]; 2438 u8 ssn[0x18]; 2439 2440 u8 reserved_20[0x8]; 2441 u8 log_rra_max[0x3]; 2442 u8 reserved_21[0x1]; 2443 u8 atomic_mode[0x4]; 2444 u8 rre[0x1]; 2445 u8 rwe[0x1]; 2446 u8 rae[0x1]; 2447 u8 reserved_22[0x1]; 2448 u8 page_offset[0x6]; 2449 u8 reserved_23[0x3]; 2450 u8 cd_slave_receive[0x1]; 2451 u8 cd_slave_send[0x1]; 2452 u8 cd_master[0x1]; 2453 2454 u8 reserved_24[0x3]; 2455 u8 min_rnr_nak[0x5]; 2456 u8 next_rcv_psn[0x18]; 2457 2458 u8 reserved_25[0x8]; 2459 u8 xrcd[0x18]; 2460 2461 u8 reserved_26[0x8]; 2462 u8 cqn_rcv[0x18]; 2463 2464 u8 dbr_addr[0x40]; 2465 2466 u8 q_key[0x20]; 2467 2468 u8 reserved_27[0x5]; 2469 u8 rq_type[0x3]; 2470 u8 srqn_rmpn[0x18]; 2471 2472 u8 reserved_28[0x8]; 2473 u8 rmsn[0x18]; 2474 2475 u8 hw_sq_wqebb_counter[0x10]; 2476 u8 sw_sq_wqebb_counter[0x10]; 2477 2478 u8 hw_rq_counter[0x20]; 2479 2480 u8 sw_rq_counter[0x20]; 2481 2482 u8 reserved_29[0x20]; 2483 2484 u8 reserved_30[0xf]; 2485 u8 cgs[0x1]; 2486 u8 cs_req[0x8]; 2487 u8 cs_res[0x8]; 2488 2489 u8 dc_access_key[0x40]; 2490 2491 u8 reserved_at_680[0x3]; 2492 u8 dbr_umem_valid[0x1]; 2493 2494 u8 reserved_at_684[0xbc]; 2495 }; 2496 2497 struct mlx5_ifc_roce_addr_layout_bits { 2498 u8 source_l3_address[16][0x8]; 2499 2500 u8 reserved_0[0x3]; 2501 u8 vlan_valid[0x1]; 2502 u8 vlan_id[0xc]; 2503 u8 source_mac_47_32[0x10]; 2504 2505 u8 source_mac_31_0[0x20]; 2506 2507 u8 reserved_1[0x14]; 2508 u8 roce_l3_type[0x4]; 2509 u8 roce_version[0x8]; 2510 2511 u8 reserved_2[0x20]; 2512 }; 2513 2514 struct mlx5_ifc_rdbc_bits { 2515 u8 reserved_0[0x1c]; 2516 u8 type[0x4]; 2517 2518 u8 reserved_1[0x20]; 2519 2520 u8 reserved_2[0x8]; 2521 u8 psn[0x18]; 2522 2523 u8 rkey[0x20]; 2524 2525 u8 address[0x40]; 2526 2527 u8 byte_count[0x20]; 2528 2529 u8 reserved_3[0x20]; 2530 2531 u8 atomic_resp[32][0x8]; 2532 }; 2533 2534 struct mlx5_ifc_vlan_bits { 2535 u8 ethtype[0x10]; 2536 u8 prio[0x3]; 2537 u8 cfi[0x1]; 2538 u8 vid[0xc]; 2539 }; 2540 2541 enum { 2542 MLX5_FLOW_METER_COLOR_RED = 0x0, 2543 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 2544 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 2545 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 2546 }; 2547 2548 enum { 2549 MLX5_EXE_ASO_FLOW_METER = 0x2, 2550 }; 2551 2552 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 2553 u8 return_reg_id[0x4]; 2554 u8 aso_type[0x4]; 2555 u8 reserved_at_8[0x14]; 2556 u8 action[0x1]; 2557 u8 init_color[0x2]; 2558 u8 meter_id[0x1]; 2559 }; 2560 2561 union mlx5_ifc_exe_aso_ctrl { 2562 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 2563 }; 2564 2565 struct mlx5_ifc_execute_aso_bits { 2566 u8 valid[0x1]; 2567 u8 reserved_at_1[0x7]; 2568 u8 aso_object_id[0x18]; 2569 2570 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 2571 }; 2572 2573 enum { 2574 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0, 2575 }; 2576 2577 struct mlx5_ifc_flow_context_bits { 2578 struct mlx5_ifc_vlan_bits push_vlan; 2579 2580 u8 group_id[0x20]; 2581 2582 u8 reserved_at_40[0x8]; 2583 u8 flow_tag[0x18]; 2584 2585 u8 reserved_at_60[0x10]; 2586 u8 action[0x10]; 2587 2588 u8 extended_destination[0x1]; 2589 u8 reserved_at_81[0x1]; 2590 u8 flow_source[0x2]; 2591 u8 encrypt_decrypt_type[0x4]; 2592 u8 destination_list_size[0x18]; 2593 2594 u8 reserved_at_a0[0x8]; 2595 u8 flow_counter_list_size[0x18]; 2596 2597 u8 packet_reformat_id[0x20]; 2598 2599 u8 modify_header_id[0x20]; 2600 2601 struct mlx5_ifc_vlan_bits push_vlan_2; 2602 2603 u8 encrypt_decrypt_obj_id[0x20]; 2604 u8 reserved_at_140[0xc0]; 2605 2606 struct mlx5_ifc_fte_match_param_bits match_value; 2607 2608 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 2609 2610 u8 reserved_at_1300[0x500]; 2611 2612 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 2613 }; 2614 2615 enum { 2616 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 2617 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 2618 }; 2619 2620 struct mlx5_ifc_xrc_srqc_bits { 2621 u8 state[0x4]; 2622 u8 log_xrc_srq_size[0x4]; 2623 u8 reserved_0[0x18]; 2624 2625 u8 wq_signature[0x1]; 2626 u8 cont_srq[0x1]; 2627 u8 reserved_1[0x1]; 2628 u8 rlky[0x1]; 2629 u8 basic_cyclic_rcv_wqe[0x1]; 2630 u8 log_rq_stride[0x3]; 2631 u8 xrcd[0x18]; 2632 2633 u8 page_offset[0x6]; 2634 u8 reserved_at_46[0x1]; 2635 u8 dbr_umem_valid[0x1]; 2636 u8 cqn[0x18]; 2637 2638 u8 reserved_3[0x20]; 2639 2640 u8 reserved_4[0x2]; 2641 u8 log_page_size[0x6]; 2642 u8 user_index[0x18]; 2643 2644 u8 reserved_5[0x20]; 2645 2646 u8 reserved_6[0x8]; 2647 u8 pd[0x18]; 2648 2649 u8 lwm[0x10]; 2650 u8 wqe_cnt[0x10]; 2651 2652 u8 reserved_7[0x40]; 2653 2654 u8 db_record_addr_h[0x20]; 2655 2656 u8 db_record_addr_l[0x1e]; 2657 u8 reserved_8[0x2]; 2658 2659 u8 reserved_9[0x80]; 2660 }; 2661 2662 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 2663 u8 counter_error_queues[0x20]; 2664 2665 u8 total_error_queues[0x20]; 2666 2667 u8 send_queue_priority_update_flow[0x20]; 2668 2669 u8 reserved_at_60[0x20]; 2670 2671 u8 nic_receive_steering_discard[0x40]; 2672 2673 u8 receive_discard_vport_down[0x40]; 2674 2675 u8 transmit_discard_vport_down[0x40]; 2676 2677 u8 reserved_at_140[0xec0]; 2678 }; 2679 2680 struct mlx5_ifc_traffic_counter_bits { 2681 u8 packets[0x40]; 2682 2683 u8 octets[0x40]; 2684 }; 2685 2686 struct mlx5_ifc_tisc_bits { 2687 u8 strict_lag_tx_port_affinity[0x1]; 2688 u8 tls_en[0x1]; 2689 u8 reserved_at_2[0x2]; 2690 u8 lag_tx_port_affinity[0x04]; 2691 2692 u8 reserved_at_8[0x4]; 2693 u8 prio[0x4]; 2694 u8 reserved_1[0x10]; 2695 2696 u8 reserved_2[0x100]; 2697 2698 u8 reserved_3[0x8]; 2699 u8 transport_domain[0x18]; 2700 2701 u8 reserved_4[0x8]; 2702 u8 underlay_qpn[0x18]; 2703 2704 u8 reserved_5[0x8]; 2705 u8 pd[0x18]; 2706 2707 u8 reserved_6[0x380]; 2708 }; 2709 2710 enum { 2711 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 2712 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 2713 }; 2714 2715 enum { 2716 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, 2717 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, 2718 }; 2719 2720 enum { 2721 MLX5_TIRC_RX_HASH_FN_HASH_NONE = 0x0, 2722 MLX5_TIRC_RX_HASH_FN_HASH_INVERTED_XOR8 = 0x1, 2723 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ = 0x2, 2724 }; 2725 2726 enum { 2727 MLX5_TIRC_SELF_LB_EN_ENABLE_UNICAST = 0x1, 2728 MLX5_TIRC_SELF_LB_EN_ENABLE_MULTICAST = 0x2, 2729 }; 2730 2731 struct mlx5_ifc_tirc_bits { 2732 u8 reserved_0[0x20]; 2733 2734 u8 disp_type[0x4]; 2735 u8 tls_en[0x1]; 2736 u8 reserved_at_25[0x1b]; 2737 2738 u8 reserved_2[0x40]; 2739 2740 u8 reserved_3[0x4]; 2741 u8 lro_timeout_period_usecs[0x10]; 2742 u8 lro_enable_mask[0x4]; 2743 u8 lro_max_msg_sz[0x8]; 2744 2745 u8 reserved_4[0x40]; 2746 2747 u8 reserved_5[0x8]; 2748 u8 inline_rqn[0x18]; 2749 2750 u8 rx_hash_symmetric[0x1]; 2751 u8 reserved_6[0x1]; 2752 u8 tunneled_offload_en[0x1]; 2753 u8 reserved_7[0x5]; 2754 u8 indirect_table[0x18]; 2755 2756 u8 rx_hash_fn[0x4]; 2757 u8 reserved_8[0x2]; 2758 u8 self_lb_en[0x2]; 2759 u8 transport_domain[0x18]; 2760 2761 u8 rx_hash_toeplitz_key[10][0x20]; 2762 2763 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 2764 2765 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 2766 2767 u8 reserved_9[0x4c0]; 2768 }; 2769 2770 enum { 2771 MLX5_SRQC_STATE_GOOD = 0x0, 2772 MLX5_SRQC_STATE_ERROR = 0x1, 2773 }; 2774 2775 struct mlx5_ifc_srqc_bits { 2776 u8 state[0x4]; 2777 u8 log_srq_size[0x4]; 2778 u8 reserved_0[0x18]; 2779 2780 u8 wq_signature[0x1]; 2781 u8 cont_srq[0x1]; 2782 u8 reserved_1[0x1]; 2783 u8 rlky[0x1]; 2784 u8 reserved_2[0x1]; 2785 u8 log_rq_stride[0x3]; 2786 u8 xrcd[0x18]; 2787 2788 u8 page_offset[0x6]; 2789 u8 reserved_3[0x2]; 2790 u8 cqn[0x18]; 2791 2792 u8 reserved_4[0x20]; 2793 2794 u8 reserved_5[0x2]; 2795 u8 log_page_size[0x6]; 2796 u8 reserved_6[0x18]; 2797 2798 u8 reserved_7[0x20]; 2799 2800 u8 reserved_8[0x8]; 2801 u8 pd[0x18]; 2802 2803 u8 lwm[0x10]; 2804 u8 wqe_cnt[0x10]; 2805 2806 u8 reserved_9[0x40]; 2807 2808 u8 dbr_addr[0x40]; 2809 2810 u8 reserved_10[0x80]; 2811 }; 2812 2813 enum { 2814 MLX5_SQC_STATE_RST = 0x0, 2815 MLX5_SQC_STATE_RDY = 0x1, 2816 MLX5_SQC_STATE_ERR = 0x3, 2817 }; 2818 2819 enum { 2820 MLX5_SQC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 2821 MLX5_SQC_TIMESTAMP_FORMAT_DEFAULT = 0x1, 2822 MLX5_SQC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 2823 }; 2824 2825 struct mlx5_ifc_sqc_bits { 2826 u8 rlkey[0x1]; 2827 u8 cd_master[0x1]; 2828 u8 fre[0x1]; 2829 u8 flush_in_error_en[0x1]; 2830 u8 allow_multi_pkt_send_wqe[0x1]; 2831 u8 min_wqe_inline_mode[0x3]; 2832 u8 state[0x4]; 2833 u8 reg_umr[0x1]; 2834 u8 allow_swp[0x1]; 2835 u8 reserved_at_e[0x4]; 2836 u8 qos_remap_en[0x1]; 2837 u8 reserved_at_d[0x7]; 2838 u8 ts_format[0x2]; 2839 u8 reserved_at_1c[0x4]; 2840 2841 u8 reserved_1[0x8]; 2842 u8 user_index[0x18]; 2843 2844 u8 reserved_2[0x8]; 2845 u8 cqn[0x18]; 2846 2847 u8 reserved_3[0x80]; 2848 2849 u8 qos_para_vport_number[0x10]; 2850 u8 packet_pacing_rate_limit_index[0x10]; 2851 2852 u8 tis_lst_sz[0x10]; 2853 u8 qos_queue_group_id[0x10]; 2854 2855 u8 reserved_4[0x8]; 2856 u8 queue_handle[0x18]; 2857 2858 u8 reserved_5[0x20]; 2859 2860 u8 reserved_6[0x8]; 2861 u8 tis_num_0[0x18]; 2862 2863 struct mlx5_ifc_wq_bits wq; 2864 }; 2865 2866 struct mlx5_ifc_query_pp_rate_limit_in_bits { 2867 u8 opcode[0x10]; 2868 u8 uid[0x10]; 2869 2870 u8 reserved1[0x10]; 2871 u8 op_mod[0x10]; 2872 2873 u8 reserved2[0x10]; 2874 u8 rate_limit_index[0x10]; 2875 2876 u8 reserved_3[0x20]; 2877 }; 2878 2879 struct mlx5_ifc_pp_context_bits { 2880 u8 rate_limit[0x20]; 2881 2882 u8 burst_upper_bound[0x20]; 2883 2884 u8 reserved_1[0xc]; 2885 u8 rate_mode[0x4]; 2886 u8 typical_packet_size[0x10]; 2887 2888 u8 reserved_2[0x8]; 2889 u8 qos_handle[0x18]; 2890 2891 u8 reserved_3[0x40]; 2892 }; 2893 2894 struct mlx5_ifc_query_pp_rate_limit_out_bits { 2895 u8 status[0x8]; 2896 u8 reserved_1[0x18]; 2897 2898 u8 syndrome[0x20]; 2899 2900 u8 reserved_2[0x40]; 2901 2902 struct mlx5_ifc_pp_context_bits pp_context; 2903 }; 2904 2905 enum { 2906 MLX5_TSAR_TYPE_DWRR = 0, 2907 MLX5_TSAR_TYPE_ROUND_ROUBIN = 1, 2908 MLX5_TSAR_TYPE_ETS = 2 2909 }; 2910 2911 struct mlx5_ifc_tsar_element_attributes_bits { 2912 u8 reserved_0[0x8]; 2913 u8 tsar_type[0x8]; 2914 u8 reserved_1[0x10]; 2915 }; 2916 2917 struct mlx5_ifc_vport_element_attributes_bits { 2918 u8 reserved_0[0x10]; 2919 u8 vport_number[0x10]; 2920 }; 2921 2922 struct mlx5_ifc_vport_tc_element_attributes_bits { 2923 u8 traffic_class[0x10]; 2924 u8 vport_number[0x10]; 2925 }; 2926 2927 struct mlx5_ifc_para_vport_tc_element_attributes_bits { 2928 u8 reserved_0[0x0C]; 2929 u8 traffic_class[0x04]; 2930 u8 qos_para_vport_number[0x10]; 2931 }; 2932 2933 enum { 2934 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 2935 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 2936 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 2937 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 2938 }; 2939 2940 struct mlx5_ifc_scheduling_context_bits { 2941 u8 element_type[0x8]; 2942 u8 reserved_at_8[0x18]; 2943 2944 u8 element_attributes[0x20]; 2945 2946 u8 parent_element_id[0x20]; 2947 2948 u8 reserved_at_60[0x40]; 2949 2950 u8 bw_share[0x20]; 2951 2952 u8 max_average_bw[0x20]; 2953 2954 u8 reserved_at_e0[0x120]; 2955 }; 2956 2957 struct mlx5_ifc_rqtc_bits { 2958 u8 reserved_0[0xa0]; 2959 2960 u8 reserved_1[0x10]; 2961 u8 rqt_max_size[0x10]; 2962 2963 u8 reserved_2[0x10]; 2964 u8 rqt_actual_size[0x10]; 2965 2966 u8 reserved_3[0x6a0]; 2967 2968 struct mlx5_ifc_rq_num_bits rq_num[0]; 2969 }; 2970 2971 enum { 2972 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 2973 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 2974 }; 2975 2976 enum { 2977 MLX5_RQC_STATE_RST = 0x0, 2978 MLX5_RQC_STATE_RDY = 0x1, 2979 MLX5_RQC_STATE_ERR = 0x3, 2980 }; 2981 2982 enum { 2983 MLX5_RQC_DROPLESS_MODE_DISABLE = 0x0, 2984 MLX5_RQC_DROPLESS_MODE_ENABLE = 0x1, 2985 }; 2986 2987 enum { 2988 MLX5_RQC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 2989 MLX5_RQC_TIMESTAMP_FORMAT_DEFAULT = 0x1, 2990 MLX5_RQC_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 2991 }; 2992 2993 struct mlx5_ifc_rqc_bits { 2994 u8 rlkey[0x1]; 2995 u8 delay_drop_en[0x1]; 2996 u8 scatter_fcs[0x1]; 2997 u8 vlan_strip_disable[0x1]; 2998 u8 mem_rq_type[0x4]; 2999 u8 state[0x4]; 3000 u8 reserved_1[0x1]; 3001 u8 flush_in_error_en[0x1]; 3002 u8 reserved_at_e[0xc]; 3003 u8 ts_format[0x2]; 3004 u8 reserved_at_1c[0x4]; 3005 3006 u8 reserved_3[0x8]; 3007 u8 user_index[0x18]; 3008 3009 u8 reserved_4[0x8]; 3010 u8 cqn[0x18]; 3011 3012 u8 counter_set_id[0x8]; 3013 u8 reserved_5[0x18]; 3014 3015 u8 reserved_6[0x8]; 3016 u8 rmpn[0x18]; 3017 3018 u8 reserved_7[0xe0]; 3019 3020 struct mlx5_ifc_wq_bits wq; 3021 }; 3022 3023 enum { 3024 MLX5_RMPC_STATE_RDY = 0x1, 3025 MLX5_RMPC_STATE_ERR = 0x3, 3026 }; 3027 3028 struct mlx5_ifc_rmpc_bits { 3029 u8 reserved_0[0x8]; 3030 u8 state[0x4]; 3031 u8 reserved_1[0x14]; 3032 3033 u8 basic_cyclic_rcv_wqe[0x1]; 3034 u8 reserved_2[0x1f]; 3035 3036 u8 reserved_3[0x140]; 3037 3038 struct mlx5_ifc_wq_bits wq; 3039 }; 3040 3041 enum { 3042 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS = 0x0, 3043 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_MC_MAC_ADDRESS = 0x1, 3044 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_VLAN_LIST = 0x2, 3045 }; 3046 3047 struct mlx5_ifc_nic_vport_context_bits { 3048 u8 reserved_0[0x5]; 3049 u8 min_wqe_inline_mode[0x3]; 3050 u8 reserved_1[0x15]; 3051 u8 disable_mc_local_lb[0x1]; 3052 u8 disable_uc_local_lb[0x1]; 3053 u8 roce_en[0x1]; 3054 3055 u8 arm_change_event[0x1]; 3056 u8 reserved_2[0x1a]; 3057 u8 event_on_mtu[0x1]; 3058 u8 event_on_promisc_change[0x1]; 3059 u8 event_on_vlan_change[0x1]; 3060 u8 event_on_mc_address_change[0x1]; 3061 u8 event_on_uc_address_change[0x1]; 3062 3063 u8 reserved_3[0xe0]; 3064 3065 u8 reserved_4[0x10]; 3066 u8 mtu[0x10]; 3067 3068 u8 system_image_guid[0x40]; 3069 3070 u8 port_guid[0x40]; 3071 3072 u8 node_guid[0x40]; 3073 3074 u8 reserved_5[0x140]; 3075 3076 u8 qkey_violation_counter[0x10]; 3077 u8 reserved_6[0x10]; 3078 3079 u8 reserved_7[0x420]; 3080 3081 u8 promisc_uc[0x1]; 3082 u8 promisc_mc[0x1]; 3083 u8 promisc_all[0x1]; 3084 u8 reserved_8[0x2]; 3085 u8 allowed_list_type[0x3]; 3086 u8 reserved_9[0xc]; 3087 u8 allowed_list_size[0xc]; 3088 3089 struct mlx5_ifc_mac_address_layout_bits permanent_address; 3090 3091 u8 reserved_10[0x20]; 3092 3093 u8 current_uc_mac_address[0][0x40]; 3094 }; 3095 3096 enum { 3097 MLX5_ACCESS_MODE_PA = 0x0, 3098 MLX5_ACCESS_MODE_MTT = 0x1, 3099 MLX5_ACCESS_MODE_KLM = 0x2, 3100 MLX5_ACCESS_MODE_KSM = 0x3, 3101 MLX5_ACCESS_MODE_SW_ICM = 0x4, 3102 MLX5_ACCESS_MODE_MEMIC = 0x5, 3103 }; 3104 3105 struct mlx5_ifc_mkc_bits { 3106 u8 reserved_at_0[0x1]; 3107 u8 free[0x1]; 3108 u8 reserved_at_2[0x1]; 3109 u8 access_mode_4_2[0x3]; 3110 u8 reserved_at_6[0x7]; 3111 u8 relaxed_ordering_write[0x1]; 3112 u8 reserved_at_e[0x1]; 3113 u8 small_fence_on_rdma_read_response[0x1]; 3114 u8 umr_en[0x1]; 3115 u8 a[0x1]; 3116 u8 rw[0x1]; 3117 u8 rr[0x1]; 3118 u8 lw[0x1]; 3119 u8 lr[0x1]; 3120 u8 access_mode[0x2]; 3121 u8 reserved_2[0x8]; 3122 3123 u8 qpn[0x18]; 3124 u8 mkey_7_0[0x8]; 3125 3126 u8 reserved_3[0x20]; 3127 3128 u8 length64[0x1]; 3129 u8 bsf_en[0x1]; 3130 u8 sync_umr[0x1]; 3131 u8 reserved_4[0x2]; 3132 u8 expected_sigerr_count[0x1]; 3133 u8 reserved_5[0x1]; 3134 u8 en_rinval[0x1]; 3135 u8 pd[0x18]; 3136 3137 u8 start_addr[0x40]; 3138 3139 u8 len[0x40]; 3140 3141 u8 bsf_octword_size[0x20]; 3142 3143 u8 reserved_6[0x80]; 3144 3145 u8 translations_octword_size[0x20]; 3146 3147 u8 reserved_at_1c0[0x19]; 3148 u8 relaxed_ordering_read[0x1]; 3149 u8 reserved_at_1d9[0x1]; 3150 u8 log_page_size[0x5]; 3151 3152 u8 reserved_8[0x20]; 3153 }; 3154 3155 struct mlx5_ifc_pkey_bits { 3156 u8 reserved_0[0x10]; 3157 u8 pkey[0x10]; 3158 }; 3159 3160 struct mlx5_ifc_array128_auto_bits { 3161 u8 array128_auto[16][0x8]; 3162 }; 3163 3164 enum { 3165 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_PORT_GUID = 0x0, 3166 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_NODE_GUID = 0x1, 3167 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_VPORT_STATE_POLICY = 0x2, 3168 }; 3169 3170 enum { 3171 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_SLEEP = 0x1, 3172 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_POLLING = 0x2, 3173 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_DISABLED = 0x3, 3174 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PORTCONFIGURATIONTRAINING = 0x4, 3175 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKUP = 0x5, 3176 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKERRORRECOVERY = 0x6, 3177 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PHYTEST = 0x7, 3178 }; 3179 3180 enum { 3181 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_DOWN = 0x0, 3182 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_UP = 0x1, 3183 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_FOLLOW = 0x2, 3184 }; 3185 3186 enum { 3187 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_DOWN = 0x1, 3188 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_INIT = 0x2, 3189 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ARM = 0x3, 3190 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ACTIVE = 0x4, 3191 }; 3192 3193 enum { 3194 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_DOWN = 0x1, 3195 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_INIT = 0x2, 3196 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ARM = 0x3, 3197 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ACTIVE = 0x4, 3198 }; 3199 3200 struct mlx5_ifc_hca_vport_context_bits { 3201 u8 field_select[0x20]; 3202 3203 u8 reserved_0[0xe0]; 3204 3205 u8 sm_virt_aware[0x1]; 3206 u8 has_smi[0x1]; 3207 u8 has_raw[0x1]; 3208 u8 grh_required[0x1]; 3209 u8 reserved_1[0x1]; 3210 u8 min_wqe_inline_mode[0x3]; 3211 u8 reserved_2[0x8]; 3212 u8 port_physical_state[0x4]; 3213 u8 vport_state_policy[0x4]; 3214 u8 port_state[0x4]; 3215 u8 vport_state[0x4]; 3216 3217 u8 reserved_3[0x20]; 3218 3219 u8 system_image_guid[0x40]; 3220 3221 u8 port_guid[0x40]; 3222 3223 u8 node_guid[0x40]; 3224 3225 u8 cap_mask1[0x20]; 3226 3227 u8 cap_mask1_field_select[0x20]; 3228 3229 u8 cap_mask2[0x20]; 3230 3231 u8 cap_mask2_field_select[0x20]; 3232 3233 u8 reserved_4[0x80]; 3234 3235 u8 lid[0x10]; 3236 u8 reserved_5[0x4]; 3237 u8 init_type_reply[0x4]; 3238 u8 lmc[0x3]; 3239 u8 subnet_timeout[0x5]; 3240 3241 u8 sm_lid[0x10]; 3242 u8 sm_sl[0x4]; 3243 u8 reserved_6[0xc]; 3244 3245 u8 qkey_violation_counter[0x10]; 3246 u8 pkey_violation_counter[0x10]; 3247 3248 u8 reserved_7[0xca0]; 3249 }; 3250 3251 union mlx5_ifc_hca_cap_union_bits { 3252 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3253 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3254 struct mlx5_ifc_odp_cap_bits odp_cap; 3255 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3256 struct mlx5_ifc_roce_cap_bits roce_cap; 3257 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3258 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3259 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3260 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3261 struct mlx5_ifc_snapshot_cap_bits snapshot_cap; 3262 struct mlx5_ifc_debug_cap_bits diagnostic_counters_cap; 3263 struct mlx5_ifc_qos_cap_bits qos_cap; 3264 struct mlx5_ifc_tls_capabilities_bits tls_capabilities; 3265 u8 reserved_0[0x8000]; 3266 }; 3267 3268 enum { 3269 MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_DEFAULT = 0x0, 3270 MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_IDENTIFIED = 0x1, 3271 }; 3272 3273 struct mlx5_ifc_flow_table_context_bits { 3274 u8 reformat_en[0x1]; 3275 u8 decap_en[0x1]; 3276 u8 sw_owner[0x1]; 3277 u8 termination_table[0x1]; 3278 u8 table_miss_action[0x4]; 3279 u8 level[0x8]; 3280 u8 reserved_at_10[0x8]; 3281 u8 log_size[0x8]; 3282 3283 u8 reserved_at_20[0x8]; 3284 u8 table_miss_id[0x18]; 3285 3286 u8 reserved_at_40[0x8]; 3287 u8 lag_master_next_table_id[0x18]; 3288 3289 u8 reserved_at_60[0x60]; 3290 3291 u8 sw_owner_icm_root_1[0x40]; 3292 3293 u8 sw_owner_icm_root_0[0x40]; 3294 3295 }; 3296 3297 struct mlx5_ifc_esw_vport_context_bits { 3298 u8 reserved_0[0x3]; 3299 u8 vport_svlan_strip[0x1]; 3300 u8 vport_cvlan_strip[0x1]; 3301 u8 vport_svlan_insert[0x1]; 3302 u8 vport_cvlan_insert[0x2]; 3303 u8 reserved_1[0x18]; 3304 3305 u8 reserved_2[0x20]; 3306 3307 u8 svlan_cfi[0x1]; 3308 u8 svlan_pcp[0x3]; 3309 u8 svlan_id[0xc]; 3310 u8 cvlan_cfi[0x1]; 3311 u8 cvlan_pcp[0x3]; 3312 u8 cvlan_id[0xc]; 3313 3314 u8 reserved_3[0x7a0]; 3315 }; 3316 3317 enum { 3318 MLX5_EQC_STATUS_OK = 0x0, 3319 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 3320 }; 3321 3322 enum { 3323 MLX5_EQ_STATE_ARMED = 0x9, 3324 MLX5_EQ_STATE_FIRED = 0xa, 3325 }; 3326 3327 struct mlx5_ifc_eqc_bits { 3328 u8 status[0x4]; 3329 u8 reserved_0[0x9]; 3330 u8 ec[0x1]; 3331 u8 oi[0x1]; 3332 u8 reserved_1[0x5]; 3333 u8 st[0x4]; 3334 u8 reserved_2[0x8]; 3335 3336 u8 reserved_3[0x20]; 3337 3338 u8 reserved_4[0x14]; 3339 u8 page_offset[0x6]; 3340 u8 reserved_5[0x6]; 3341 3342 u8 reserved_6[0x3]; 3343 u8 log_eq_size[0x5]; 3344 u8 uar_page[0x18]; 3345 3346 u8 reserved_7[0x20]; 3347 3348 u8 reserved_8[0x18]; 3349 u8 intr[0x8]; 3350 3351 u8 reserved_9[0x3]; 3352 u8 log_page_size[0x5]; 3353 u8 reserved_10[0x18]; 3354 3355 u8 reserved_11[0x60]; 3356 3357 u8 reserved_12[0x8]; 3358 u8 consumer_counter[0x18]; 3359 3360 u8 reserved_13[0x8]; 3361 u8 producer_counter[0x18]; 3362 3363 u8 reserved_14[0x80]; 3364 }; 3365 3366 enum { 3367 MLX5_DCTC_STATE_ACTIVE = 0x0, 3368 MLX5_DCTC_STATE_DRAINING = 0x1, 3369 MLX5_DCTC_STATE_DRAINED = 0x2, 3370 }; 3371 3372 enum { 3373 MLX5_DCTC_CS_RES_DISABLE = 0x0, 3374 MLX5_DCTC_CS_RES_NA = 0x1, 3375 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 3376 }; 3377 3378 enum { 3379 MLX5_DCTC_MTU_256_BYTES = 0x1, 3380 MLX5_DCTC_MTU_512_BYTES = 0x2, 3381 MLX5_DCTC_MTU_1K_BYTES = 0x3, 3382 MLX5_DCTC_MTU_2K_BYTES = 0x4, 3383 MLX5_DCTC_MTU_4K_BYTES = 0x5, 3384 }; 3385 3386 struct mlx5_ifc_dctc_bits { 3387 u8 reserved_0[0x4]; 3388 u8 state[0x4]; 3389 u8 reserved_1[0x18]; 3390 3391 u8 reserved_2[0x8]; 3392 u8 user_index[0x18]; 3393 3394 u8 reserved_3[0x8]; 3395 u8 cqn[0x18]; 3396 3397 u8 counter_set_id[0x8]; 3398 u8 atomic_mode[0x4]; 3399 u8 rre[0x1]; 3400 u8 rwe[0x1]; 3401 u8 rae[0x1]; 3402 u8 atomic_like_write_en[0x1]; 3403 u8 latency_sensitive[0x1]; 3404 u8 rlky[0x1]; 3405 u8 reserved_4[0xe]; 3406 3407 u8 reserved_5[0x8]; 3408 u8 cs_res[0x8]; 3409 u8 reserved_6[0x3]; 3410 u8 min_rnr_nak[0x5]; 3411 u8 reserved_7[0x8]; 3412 3413 u8 reserved_8[0x8]; 3414 u8 srqn[0x18]; 3415 3416 u8 reserved_9[0x8]; 3417 u8 pd[0x18]; 3418 3419 u8 tclass[0x8]; 3420 u8 reserved_10[0x4]; 3421 u8 flow_label[0x14]; 3422 3423 u8 dc_access_key[0x40]; 3424 3425 u8 reserved_11[0x5]; 3426 u8 mtu[0x3]; 3427 u8 port[0x8]; 3428 u8 pkey_index[0x10]; 3429 3430 u8 reserved_12[0x8]; 3431 u8 my_addr_index[0x8]; 3432 u8 reserved_13[0x8]; 3433 u8 hop_limit[0x8]; 3434 3435 u8 dc_access_key_violation_count[0x20]; 3436 3437 u8 reserved_14[0x14]; 3438 u8 dei_cfi[0x1]; 3439 u8 eth_prio[0x3]; 3440 u8 ecn[0x2]; 3441 u8 dscp[0x6]; 3442 3443 u8 reserved_15[0x40]; 3444 }; 3445 3446 enum { 3447 MLX5_CQC_STATUS_OK = 0x0, 3448 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 3449 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 3450 }; 3451 3452 enum { 3453 CQE_SIZE_64 = 0x0, 3454 CQE_SIZE_128 = 0x1, 3455 }; 3456 3457 enum { 3458 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 3459 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 3460 }; 3461 3462 enum { 3463 MLX5_CQ_STATE_SOLICITED_ARMED = 0x6, 3464 MLX5_CQ_STATE_ARMED = 0x9, 3465 MLX5_CQ_STATE_FIRED = 0xa, 3466 }; 3467 3468 struct mlx5_ifc_cqc_bits { 3469 u8 status[0x4]; 3470 u8 reserved_at_4[0x2]; 3471 u8 dbr_umem_valid[0x1]; 3472 u8 reserved_at_7[0x1]; 3473 u8 cqe_sz[0x3]; 3474 u8 cc[0x1]; 3475 u8 reserved_1[0x1]; 3476 u8 scqe_break_moderation_en[0x1]; 3477 u8 oi[0x1]; 3478 u8 cq_period_mode[0x2]; 3479 u8 cqe_compression_en[0x1]; 3480 u8 mini_cqe_res_format[0x2]; 3481 u8 st[0x4]; 3482 u8 reserved_2[0x8]; 3483 3484 u8 reserved_3[0x20]; 3485 3486 u8 reserved_4[0x14]; 3487 u8 page_offset[0x6]; 3488 u8 reserved_5[0x6]; 3489 3490 u8 reserved_6[0x3]; 3491 u8 log_cq_size[0x5]; 3492 u8 uar_page[0x18]; 3493 3494 u8 reserved_7[0x4]; 3495 u8 cq_period[0xc]; 3496 u8 cq_max_count[0x10]; 3497 3498 u8 reserved_8[0x18]; 3499 u8 c_eqn[0x8]; 3500 3501 u8 reserved_9[0x3]; 3502 u8 log_page_size[0x5]; 3503 u8 reserved_10[0x18]; 3504 3505 u8 reserved_11[0x20]; 3506 3507 u8 reserved_12[0x8]; 3508 u8 last_notified_index[0x18]; 3509 3510 u8 reserved_13[0x8]; 3511 u8 last_solicit_index[0x18]; 3512 3513 u8 reserved_14[0x8]; 3514 u8 consumer_counter[0x18]; 3515 3516 u8 reserved_15[0x8]; 3517 u8 producer_counter[0x18]; 3518 3519 u8 reserved_16[0x40]; 3520 3521 u8 dbr_addr[0x40]; 3522 }; 3523 3524 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 3525 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 3526 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 3527 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 3528 u8 reserved_0[0x800]; 3529 }; 3530 3531 struct mlx5_ifc_query_adapter_param_block_bits { 3532 u8 reserved_0[0xc0]; 3533 3534 u8 reserved_1[0x8]; 3535 u8 ieee_vendor_id[0x18]; 3536 3537 u8 reserved_2[0x10]; 3538 u8 vsd_vendor_id[0x10]; 3539 3540 u8 vsd[208][0x8]; 3541 3542 u8 vsd_contd_psid[16][0x8]; 3543 }; 3544 3545 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 3546 struct mlx5_ifc_modify_field_select_bits modify_field_select; 3547 struct mlx5_ifc_resize_field_select_bits resize_field_select; 3548 u8 reserved_0[0x20]; 3549 }; 3550 3551 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 3552 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 3553 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 3554 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 3555 u8 reserved_0[0x20]; 3556 }; 3557 3558 struct mlx5_ifc_bufferx_reg_bits { 3559 u8 reserved_0[0x6]; 3560 u8 lossy[0x1]; 3561 u8 epsb[0x1]; 3562 u8 reserved_1[0xc]; 3563 u8 size[0xc]; 3564 3565 u8 xoff_threshold[0x10]; 3566 u8 xon_threshold[0x10]; 3567 }; 3568 3569 struct mlx5_ifc_config_item_bits { 3570 u8 valid[0x2]; 3571 u8 reserved_0[0x2]; 3572 u8 header_type[0x2]; 3573 u8 reserved_1[0x2]; 3574 u8 default_location[0x1]; 3575 u8 reserved_2[0x7]; 3576 u8 version[0x4]; 3577 u8 reserved_3[0x3]; 3578 u8 length[0x9]; 3579 3580 u8 type[0x20]; 3581 3582 u8 reserved_4[0x10]; 3583 u8 crc16[0x10]; 3584 }; 3585 3586 enum { 3587 MLX5_XRQC_STATE_GOOD = 0x0, 3588 MLX5_XRQC_STATE_ERROR = 0x1, 3589 }; 3590 3591 enum { 3592 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 3593 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 3594 }; 3595 3596 enum { 3597 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 3598 }; 3599 3600 struct mlx5_ifc_tag_matching_topology_context_bits { 3601 u8 log_matching_list_sz[0x4]; 3602 u8 reserved_at_4[0xc]; 3603 u8 append_next_index[0x10]; 3604 3605 u8 sw_phase_cnt[0x10]; 3606 u8 hw_phase_cnt[0x10]; 3607 3608 u8 reserved_at_40[0x40]; 3609 }; 3610 3611 struct mlx5_ifc_xrqc_bits { 3612 u8 state[0x4]; 3613 u8 rlkey[0x1]; 3614 u8 reserved_at_5[0xf]; 3615 u8 topology[0x4]; 3616 u8 reserved_at_18[0x4]; 3617 u8 offload[0x4]; 3618 3619 u8 reserved_at_20[0x8]; 3620 u8 user_index[0x18]; 3621 3622 u8 reserved_at_40[0x8]; 3623 u8 cqn[0x18]; 3624 3625 u8 reserved_at_60[0xa0]; 3626 3627 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 3628 3629 u8 reserved_at_180[0x280]; 3630 3631 struct mlx5_ifc_wq_bits wq; 3632 }; 3633 3634 struct mlx5_ifc_nodnic_port_config_reg_bits { 3635 struct mlx5_ifc_nodnic_event_word_bits event; 3636 3637 u8 network_en[0x1]; 3638 u8 dma_en[0x1]; 3639 u8 promisc_en[0x1]; 3640 u8 promisc_multicast_en[0x1]; 3641 u8 reserved_0[0x17]; 3642 u8 receive_filter_en[0x5]; 3643 3644 u8 reserved_1[0x10]; 3645 u8 mac_47_32[0x10]; 3646 3647 u8 mac_31_0[0x20]; 3648 3649 u8 receive_filters_mgid_mac[64][0x8]; 3650 3651 u8 gid[16][0x8]; 3652 3653 u8 reserved_2[0x10]; 3654 u8 lid[0x10]; 3655 3656 u8 reserved_3[0xc]; 3657 u8 sm_sl[0x4]; 3658 u8 sm_lid[0x10]; 3659 3660 u8 completion_address_63_32[0x20]; 3661 3662 u8 completion_address_31_12[0x14]; 3663 u8 reserved_4[0x6]; 3664 u8 log_cq_size[0x6]; 3665 3666 u8 working_buffer_address_63_32[0x20]; 3667 3668 u8 working_buffer_address_31_12[0x14]; 3669 u8 reserved_5[0xc]; 3670 3671 struct mlx5_ifc_nodnic_cq_arming_word_bits arm_cq; 3672 3673 u8 pkey_index[0x10]; 3674 u8 pkey[0x10]; 3675 3676 struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring0; 3677 3678 struct mlx5_ifc_nodnic_ring_config_reg_bits send_ring1; 3679 3680 struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring0; 3681 3682 struct mlx5_ifc_nodnic_ring_config_reg_bits receive_ring1; 3683 3684 u8 reserved_6[0x400]; 3685 }; 3686 3687 union mlx5_ifc_event_auto_bits { 3688 struct mlx5_ifc_comp_event_bits comp_event; 3689 struct mlx5_ifc_dct_events_bits dct_events; 3690 struct mlx5_ifc_qp_events_bits qp_events; 3691 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 3692 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 3693 struct mlx5_ifc_cq_error_bits cq_error; 3694 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 3695 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 3696 struct mlx5_ifc_gpio_event_bits gpio_event; 3697 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 3698 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 3699 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 3700 struct mlx5_ifc_pages_req_event_bits pages_req_event; 3701 struct mlx5_ifc_nic_vport_change_event_bits nic_vport_change_event; 3702 u8 reserved_0[0xe0]; 3703 }; 3704 3705 struct mlx5_ifc_health_buffer_bits { 3706 u8 reserved_0[0x100]; 3707 3708 u8 assert_existptr[0x20]; 3709 3710 u8 assert_callra[0x20]; 3711 3712 u8 reserved_1[0x40]; 3713 3714 u8 fw_version[0x20]; 3715 3716 u8 hw_id[0x20]; 3717 3718 u8 reserved_2[0x20]; 3719 3720 u8 irisc_index[0x8]; 3721 u8 synd[0x8]; 3722 u8 ext_synd[0x10]; 3723 }; 3724 3725 struct mlx5_ifc_register_loopback_control_bits { 3726 u8 no_lb[0x1]; 3727 u8 reserved_0[0x7]; 3728 u8 port[0x8]; 3729 u8 reserved_1[0x10]; 3730 3731 u8 reserved_2[0x60]; 3732 }; 3733 3734 struct mlx5_ifc_lrh_bits { 3735 u8 vl[4]; 3736 u8 lver[4]; 3737 u8 sl[4]; 3738 u8 reserved2[2]; 3739 u8 lnh[2]; 3740 u8 dlid[16]; 3741 u8 reserved5[5]; 3742 u8 pkt_len[11]; 3743 u8 slid[16]; 3744 }; 3745 3746 struct mlx5_ifc_icmd_set_wol_rol_out_bits { 3747 u8 reserved_0[0x40]; 3748 3749 u8 reserved_1[0x10]; 3750 u8 rol_mode[0x8]; 3751 u8 wol_mode[0x8]; 3752 }; 3753 3754 struct mlx5_ifc_icmd_set_wol_rol_in_bits { 3755 u8 reserved_0[0x40]; 3756 3757 u8 rol_mode_valid[0x1]; 3758 u8 wol_mode_valid[0x1]; 3759 u8 reserved_1[0xe]; 3760 u8 rol_mode[0x8]; 3761 u8 wol_mode[0x8]; 3762 3763 u8 reserved_2[0x7a0]; 3764 }; 3765 3766 struct mlx5_ifc_icmd_set_virtual_mac_in_bits { 3767 u8 virtual_mac_en[0x1]; 3768 u8 mac_aux_v[0x1]; 3769 u8 reserved_0[0x1e]; 3770 3771 u8 reserved_1[0x40]; 3772 3773 struct mlx5_ifc_mac_address_layout_bits virtual_mac; 3774 3775 u8 reserved_2[0x760]; 3776 }; 3777 3778 struct mlx5_ifc_icmd_query_virtual_mac_out_bits { 3779 u8 virtual_mac_en[0x1]; 3780 u8 mac_aux_v[0x1]; 3781 u8 reserved_0[0x1e]; 3782 3783 struct mlx5_ifc_mac_address_layout_bits permanent_mac; 3784 3785 struct mlx5_ifc_mac_address_layout_bits virtual_mac; 3786 3787 u8 reserved_1[0x760]; 3788 }; 3789 3790 struct mlx5_ifc_icmd_query_fw_info_out_bits { 3791 struct mlx5_ifc_fw_version_bits fw_version; 3792 3793 u8 reserved_0[0x10]; 3794 u8 hash_signature[0x10]; 3795 3796 u8 psid[16][0x8]; 3797 3798 u8 reserved_1[0x6e0]; 3799 }; 3800 3801 struct mlx5_ifc_icmd_query_cap_in_bits { 3802 u8 reserved_0[0x10]; 3803 u8 capability_group[0x10]; 3804 }; 3805 3806 struct mlx5_ifc_icmd_query_cap_general_bits { 3807 u8 nv_access[0x1]; 3808 u8 fw_info_psid[0x1]; 3809 u8 reserved_0[0x1e]; 3810 3811 u8 reserved_1[0x16]; 3812 u8 rol_s[0x1]; 3813 u8 rol_g[0x1]; 3814 u8 reserved_2[0x1]; 3815 u8 wol_s[0x1]; 3816 u8 wol_g[0x1]; 3817 u8 wol_a[0x1]; 3818 u8 wol_b[0x1]; 3819 u8 wol_m[0x1]; 3820 u8 wol_u[0x1]; 3821 u8 wol_p[0x1]; 3822 }; 3823 3824 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits { 3825 u8 status[0x8]; 3826 u8 reserved_0[0x18]; 3827 3828 u8 reserved_1[0x7e0]; 3829 }; 3830 3831 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits { 3832 u8 status[0x8]; 3833 u8 reserved_0[0x18]; 3834 3835 u8 reserved_1[0x7e0]; 3836 }; 3837 3838 struct mlx5_ifc_icmd_ocbb_init_in_bits { 3839 u8 address_hi[0x20]; 3840 3841 u8 address_lo[0x20]; 3842 3843 u8 reserved_0[0x7c0]; 3844 }; 3845 3846 struct mlx5_ifc_icmd_init_ocsd_in_bits { 3847 u8 reserved_0[0x20]; 3848 3849 u8 address_hi[0x20]; 3850 3851 u8 address_lo[0x20]; 3852 3853 u8 reserved_1[0x7a0]; 3854 }; 3855 3856 struct mlx5_ifc_icmd_access_reg_out_bits { 3857 u8 reserved_0[0x11]; 3858 u8 status[0x7]; 3859 u8 reserved_1[0x8]; 3860 3861 u8 register_id[0x10]; 3862 u8 reserved_2[0x10]; 3863 3864 u8 reserved_3[0x40]; 3865 3866 u8 reserved_4[0x5]; 3867 u8 len[0xb]; 3868 u8 reserved_5[0x10]; 3869 3870 u8 register_data[0][0x20]; 3871 }; 3872 3873 enum { 3874 MLX5_ICMD_ACCESS_REG_IN_METHOD_QUERY = 0x1, 3875 MLX5_ICMD_ACCESS_REG_IN_METHOD_WRITE = 0x2, 3876 }; 3877 3878 struct mlx5_ifc_icmd_access_reg_in_bits { 3879 u8 constant_1[0x5]; 3880 u8 constant_2[0xb]; 3881 u8 reserved_0[0x10]; 3882 3883 u8 register_id[0x10]; 3884 u8 reserved_1[0x1]; 3885 u8 method[0x7]; 3886 u8 constant_3[0x8]; 3887 3888 u8 reserved_2[0x40]; 3889 3890 u8 constant_4[0x5]; 3891 u8 len[0xb]; 3892 u8 reserved_3[0x10]; 3893 3894 u8 register_data[0][0x20]; 3895 }; 3896 3897 enum { 3898 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 3899 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 3900 }; 3901 3902 struct mlx5_ifc_teardown_hca_out_bits { 3903 u8 status[0x8]; 3904 u8 reserved_0[0x18]; 3905 3906 u8 syndrome[0x20]; 3907 3908 u8 reserved_1[0x3f]; 3909 3910 u8 state[0x1]; 3911 }; 3912 3913 enum { 3914 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 3915 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 3916 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 3917 }; 3918 3919 struct mlx5_ifc_teardown_hca_in_bits { 3920 u8 opcode[0x10]; 3921 u8 reserved_0[0x10]; 3922 3923 u8 reserved_1[0x10]; 3924 u8 op_mod[0x10]; 3925 3926 u8 reserved_2[0x10]; 3927 u8 profile[0x10]; 3928 3929 u8 reserved_3[0x20]; 3930 }; 3931 3932 struct mlx5_ifc_set_delay_drop_params_out_bits { 3933 u8 status[0x8]; 3934 u8 reserved_at_8[0x18]; 3935 3936 u8 syndrome[0x20]; 3937 3938 u8 reserved_at_40[0x40]; 3939 }; 3940 3941 struct mlx5_ifc_set_delay_drop_params_in_bits { 3942 u8 opcode[0x10]; 3943 u8 reserved_at_10[0x10]; 3944 3945 u8 reserved_at_20[0x10]; 3946 u8 op_mod[0x10]; 3947 3948 u8 reserved_at_40[0x20]; 3949 3950 u8 reserved_at_60[0x10]; 3951 u8 delay_drop_timeout[0x10]; 3952 }; 3953 3954 struct mlx5_ifc_query_delay_drop_params_out_bits { 3955 u8 status[0x8]; 3956 u8 reserved_at_8[0x18]; 3957 3958 u8 syndrome[0x20]; 3959 3960 u8 reserved_at_40[0x20]; 3961 3962 u8 reserved_at_60[0x10]; 3963 u8 delay_drop_timeout[0x10]; 3964 }; 3965 3966 struct mlx5_ifc_query_delay_drop_params_in_bits { 3967 u8 opcode[0x10]; 3968 u8 reserved_at_10[0x10]; 3969 3970 u8 reserved_at_20[0x10]; 3971 u8 op_mod[0x10]; 3972 3973 u8 reserved_at_40[0x40]; 3974 }; 3975 3976 struct mlx5_ifc_suspend_qp_out_bits { 3977 u8 status[0x8]; 3978 u8 reserved_0[0x18]; 3979 3980 u8 syndrome[0x20]; 3981 3982 u8 reserved_1[0x40]; 3983 }; 3984 3985 struct mlx5_ifc_suspend_qp_in_bits { 3986 u8 opcode[0x10]; 3987 u8 reserved_0[0x10]; 3988 3989 u8 reserved_1[0x10]; 3990 u8 op_mod[0x10]; 3991 3992 u8 reserved_2[0x8]; 3993 u8 qpn[0x18]; 3994 3995 u8 reserved_3[0x20]; 3996 }; 3997 3998 struct mlx5_ifc_sqerr2rts_qp_out_bits { 3999 u8 status[0x8]; 4000 u8 reserved_0[0x18]; 4001 4002 u8 syndrome[0x20]; 4003 4004 u8 reserved_1[0x40]; 4005 }; 4006 4007 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4008 u8 opcode[0x10]; 4009 u8 uid[0x10]; 4010 4011 u8 reserved_1[0x10]; 4012 u8 op_mod[0x10]; 4013 4014 u8 reserved_2[0x8]; 4015 u8 qpn[0x18]; 4016 4017 u8 reserved_3[0x20]; 4018 4019 u8 opt_param_mask[0x20]; 4020 4021 u8 reserved_4[0x20]; 4022 4023 struct mlx5_ifc_qpc_bits qpc; 4024 4025 u8 reserved_5[0x80]; 4026 }; 4027 4028 struct mlx5_ifc_sqd2rts_qp_out_bits { 4029 u8 status[0x8]; 4030 u8 reserved_0[0x18]; 4031 4032 u8 syndrome[0x20]; 4033 4034 u8 reserved_1[0x40]; 4035 }; 4036 4037 struct mlx5_ifc_sqd2rts_qp_in_bits { 4038 u8 opcode[0x10]; 4039 u8 uid[0x10]; 4040 4041 u8 reserved_1[0x10]; 4042 u8 op_mod[0x10]; 4043 4044 u8 reserved_2[0x8]; 4045 u8 qpn[0x18]; 4046 4047 u8 reserved_3[0x20]; 4048 4049 u8 opt_param_mask[0x20]; 4050 4051 u8 reserved_4[0x20]; 4052 4053 struct mlx5_ifc_qpc_bits qpc; 4054 4055 u8 reserved_5[0x80]; 4056 }; 4057 4058 struct mlx5_ifc_set_wol_rol_out_bits { 4059 u8 status[0x8]; 4060 u8 reserved_0[0x18]; 4061 4062 u8 syndrome[0x20]; 4063 4064 u8 reserved_1[0x40]; 4065 }; 4066 4067 struct mlx5_ifc_set_wol_rol_in_bits { 4068 u8 opcode[0x10]; 4069 u8 reserved_0[0x10]; 4070 4071 u8 reserved_1[0x10]; 4072 u8 op_mod[0x10]; 4073 4074 u8 rol_mode_valid[0x1]; 4075 u8 wol_mode_valid[0x1]; 4076 u8 reserved_2[0xe]; 4077 u8 rol_mode[0x8]; 4078 u8 wol_mode[0x8]; 4079 4080 u8 reserved_3[0x20]; 4081 }; 4082 4083 struct mlx5_ifc_set_roce_address_out_bits { 4084 u8 status[0x8]; 4085 u8 reserved_0[0x18]; 4086 4087 u8 syndrome[0x20]; 4088 4089 u8 reserved_1[0x40]; 4090 }; 4091 4092 struct mlx5_ifc_set_roce_address_in_bits { 4093 u8 opcode[0x10]; 4094 u8 reserved_0[0x10]; 4095 4096 u8 reserved_1[0x10]; 4097 u8 op_mod[0x10]; 4098 4099 u8 roce_address_index[0x10]; 4100 u8 reserved_2[0x10]; 4101 4102 u8 reserved_3[0x20]; 4103 4104 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4105 }; 4106 4107 struct mlx5_ifc_set_rdb_out_bits { 4108 u8 status[0x8]; 4109 u8 reserved_0[0x18]; 4110 4111 u8 syndrome[0x20]; 4112 4113 u8 reserved_1[0x40]; 4114 }; 4115 4116 struct mlx5_ifc_set_rdb_in_bits { 4117 u8 opcode[0x10]; 4118 u8 reserved_0[0x10]; 4119 4120 u8 reserved_1[0x10]; 4121 u8 op_mod[0x10]; 4122 4123 u8 reserved_2[0x8]; 4124 u8 qpn[0x18]; 4125 4126 u8 reserved_3[0x18]; 4127 u8 rdb_list_size[0x8]; 4128 4129 struct mlx5_ifc_rdbc_bits rdb_context[0]; 4130 }; 4131 4132 struct mlx5_ifc_set_mad_demux_out_bits { 4133 u8 status[0x8]; 4134 u8 reserved_0[0x18]; 4135 4136 u8 syndrome[0x20]; 4137 4138 u8 reserved_1[0x40]; 4139 }; 4140 4141 enum { 4142 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4143 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4144 }; 4145 4146 struct mlx5_ifc_set_mad_demux_in_bits { 4147 u8 opcode[0x10]; 4148 u8 reserved_0[0x10]; 4149 4150 u8 reserved_1[0x10]; 4151 u8 op_mod[0x10]; 4152 4153 u8 reserved_2[0x20]; 4154 4155 u8 reserved_3[0x6]; 4156 u8 demux_mode[0x2]; 4157 u8 reserved_4[0x18]; 4158 }; 4159 4160 struct mlx5_ifc_set_l2_table_entry_out_bits { 4161 u8 status[0x8]; 4162 u8 reserved_0[0x18]; 4163 4164 u8 syndrome[0x20]; 4165 4166 u8 reserved_1[0x40]; 4167 }; 4168 4169 struct mlx5_ifc_set_l2_table_entry_in_bits { 4170 u8 opcode[0x10]; 4171 u8 reserved_0[0x10]; 4172 4173 u8 reserved_1[0x10]; 4174 u8 op_mod[0x10]; 4175 4176 u8 reserved_2[0x60]; 4177 4178 u8 reserved_3[0x8]; 4179 u8 table_index[0x18]; 4180 4181 u8 reserved_4[0x20]; 4182 4183 u8 reserved_5[0x13]; 4184 u8 vlan_valid[0x1]; 4185 u8 vlan[0xc]; 4186 4187 struct mlx5_ifc_mac_address_layout_bits mac_address; 4188 4189 u8 reserved_6[0xc0]; 4190 }; 4191 4192 struct mlx5_ifc_set_issi_out_bits { 4193 u8 status[0x8]; 4194 u8 reserved_0[0x18]; 4195 4196 u8 syndrome[0x20]; 4197 4198 u8 reserved_1[0x40]; 4199 }; 4200 4201 struct mlx5_ifc_set_issi_in_bits { 4202 u8 opcode[0x10]; 4203 u8 reserved_0[0x10]; 4204 4205 u8 reserved_1[0x10]; 4206 u8 op_mod[0x10]; 4207 4208 u8 reserved_2[0x10]; 4209 u8 current_issi[0x10]; 4210 4211 u8 reserved_3[0x20]; 4212 }; 4213 4214 struct mlx5_ifc_set_hca_cap_out_bits { 4215 u8 status[0x8]; 4216 u8 reserved_0[0x18]; 4217 4218 u8 syndrome[0x20]; 4219 4220 u8 reserved_1[0x40]; 4221 }; 4222 4223 struct mlx5_ifc_set_hca_cap_in_bits { 4224 u8 opcode[0x10]; 4225 u8 reserved_0[0x10]; 4226 4227 u8 reserved_1[0x10]; 4228 u8 op_mod[0x10]; 4229 4230 u8 reserved_2[0x40]; 4231 4232 union mlx5_ifc_hca_cap_union_bits capability; 4233 }; 4234 4235 enum { 4236 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4237 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4238 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4239 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 4240 }; 4241 4242 struct mlx5_ifc_set_flow_table_root_out_bits { 4243 u8 status[0x8]; 4244 u8 reserved_0[0x18]; 4245 4246 u8 syndrome[0x20]; 4247 4248 u8 reserved_1[0x40]; 4249 }; 4250 4251 struct mlx5_ifc_set_flow_table_root_in_bits { 4252 u8 opcode[0x10]; 4253 u8 reserved_at_10[0x10]; 4254 4255 u8 reserved_at_20[0x10]; 4256 u8 op_mod[0x10]; 4257 4258 u8 other_vport[0x1]; 4259 u8 reserved_at_41[0xf]; 4260 u8 vport_number[0x10]; 4261 4262 u8 reserved_at_60[0x20]; 4263 4264 u8 table_type[0x8]; 4265 u8 reserved_at_88[0x7]; 4266 u8 table_of_other_vport[0x1]; 4267 u8 table_vport_number[0x10]; 4268 4269 u8 reserved_at_a0[0x8]; 4270 u8 table_id[0x18]; 4271 4272 u8 reserved_at_c0[0x8]; 4273 u8 underlay_qpn[0x18]; 4274 u8 table_eswitch_owner_vhca_id_valid[0x1]; 4275 u8 reserved_at_e1[0xf]; 4276 u8 table_eswitch_owner_vhca_id[0x10]; 4277 u8 reserved_at_100[0x100]; 4278 }; 4279 4280 struct mlx5_ifc_set_fte_out_bits { 4281 u8 status[0x8]; 4282 u8 reserved_0[0x18]; 4283 4284 u8 syndrome[0x20]; 4285 4286 u8 reserved_1[0x40]; 4287 }; 4288 4289 struct mlx5_ifc_set_fte_in_bits { 4290 u8 opcode[0x10]; 4291 u8 reserved_at_10[0x10]; 4292 4293 u8 reserved_at_20[0x10]; 4294 u8 op_mod[0x10]; 4295 4296 u8 other_vport[0x1]; 4297 u8 reserved_at_41[0xf]; 4298 u8 vport_number[0x10]; 4299 4300 u8 reserved_at_60[0x20]; 4301 4302 u8 table_type[0x8]; 4303 u8 reserved_at_88[0x18]; 4304 4305 u8 reserved_at_a0[0x8]; 4306 u8 table_id[0x18]; 4307 4308 u8 ignore_flow_level[0x1]; 4309 u8 reserved_at_c1[0x17]; 4310 u8 modify_enable_mask[0x8]; 4311 4312 u8 reserved_at_e0[0x20]; 4313 4314 u8 flow_index[0x20]; 4315 4316 u8 reserved_at_120[0xe0]; 4317 4318 struct mlx5_ifc_flow_context_bits flow_context; 4319 }; 4320 4321 struct mlx5_ifc_set_driver_version_out_bits { 4322 u8 status[0x8]; 4323 u8 reserved_0[0x18]; 4324 4325 u8 syndrome[0x20]; 4326 4327 u8 reserved_1[0x40]; 4328 }; 4329 4330 struct mlx5_ifc_set_driver_version_in_bits { 4331 u8 opcode[0x10]; 4332 u8 reserved_0[0x10]; 4333 4334 u8 reserved_1[0x10]; 4335 u8 op_mod[0x10]; 4336 4337 u8 reserved_2[0x40]; 4338 4339 u8 driver_version[64][0x8]; 4340 }; 4341 4342 struct mlx5_ifc_set_dc_cnak_trace_out_bits { 4343 u8 status[0x8]; 4344 u8 reserved_0[0x18]; 4345 4346 u8 syndrome[0x20]; 4347 4348 u8 reserved_1[0x40]; 4349 }; 4350 4351 struct mlx5_ifc_set_dc_cnak_trace_in_bits { 4352 u8 opcode[0x10]; 4353 u8 reserved_0[0x10]; 4354 4355 u8 reserved_1[0x10]; 4356 u8 op_mod[0x10]; 4357 4358 u8 enable[0x1]; 4359 u8 reserved_2[0x1f]; 4360 4361 u8 reserved_3[0x160]; 4362 4363 struct mlx5_ifc_cmd_pas_bits pas; 4364 }; 4365 4366 struct mlx5_ifc_set_burst_size_out_bits { 4367 u8 status[0x8]; 4368 u8 reserved_0[0x18]; 4369 4370 u8 syndrome[0x20]; 4371 4372 u8 reserved_1[0x40]; 4373 }; 4374 4375 struct mlx5_ifc_set_burst_size_in_bits { 4376 u8 opcode[0x10]; 4377 u8 reserved_0[0x10]; 4378 4379 u8 reserved_1[0x10]; 4380 u8 op_mod[0x10]; 4381 4382 u8 reserved_2[0x20]; 4383 4384 u8 reserved_3[0x9]; 4385 u8 device_burst_size[0x17]; 4386 }; 4387 4388 struct mlx5_ifc_rts2rts_qp_out_bits { 4389 u8 status[0x8]; 4390 u8 reserved_0[0x18]; 4391 4392 u8 syndrome[0x20]; 4393 4394 u8 reserved_1[0x40]; 4395 }; 4396 4397 struct mlx5_ifc_rts2rts_qp_in_bits { 4398 u8 opcode[0x10]; 4399 u8 uid[0x10]; 4400 4401 u8 reserved_1[0x10]; 4402 u8 op_mod[0x10]; 4403 4404 u8 reserved_2[0x8]; 4405 u8 qpn[0x18]; 4406 4407 u8 reserved_3[0x20]; 4408 4409 u8 opt_param_mask[0x20]; 4410 4411 u8 reserved_4[0x20]; 4412 4413 struct mlx5_ifc_qpc_bits qpc; 4414 4415 u8 reserved_5[0x80]; 4416 }; 4417 4418 struct mlx5_ifc_rtr2rts_qp_out_bits { 4419 u8 status[0x8]; 4420 u8 reserved_0[0x18]; 4421 4422 u8 syndrome[0x20]; 4423 4424 u8 reserved_1[0x40]; 4425 }; 4426 4427 struct mlx5_ifc_rtr2rts_qp_in_bits { 4428 u8 opcode[0x10]; 4429 u8 uid[0x10]; 4430 4431 u8 reserved_1[0x10]; 4432 u8 op_mod[0x10]; 4433 4434 u8 reserved_2[0x8]; 4435 u8 qpn[0x18]; 4436 4437 u8 reserved_3[0x20]; 4438 4439 u8 opt_param_mask[0x20]; 4440 4441 u8 reserved_4[0x20]; 4442 4443 struct mlx5_ifc_qpc_bits qpc; 4444 4445 u8 reserved_5[0x80]; 4446 }; 4447 4448 struct mlx5_ifc_rst2init_qp_out_bits { 4449 u8 status[0x8]; 4450 u8 reserved_0[0x18]; 4451 4452 u8 syndrome[0x20]; 4453 4454 u8 reserved_1[0x40]; 4455 }; 4456 4457 struct mlx5_ifc_rst2init_qp_in_bits { 4458 u8 opcode[0x10]; 4459 u8 uid[0x10]; 4460 4461 u8 reserved_1[0x10]; 4462 u8 op_mod[0x10]; 4463 4464 u8 reserved_2[0x8]; 4465 u8 qpn[0x18]; 4466 4467 u8 reserved_3[0x20]; 4468 4469 u8 opt_param_mask[0x20]; 4470 4471 u8 reserved_4[0x20]; 4472 4473 struct mlx5_ifc_qpc_bits qpc; 4474 4475 u8 reserved_5[0x80]; 4476 }; 4477 4478 struct mlx5_ifc_query_xrq_out_bits { 4479 u8 status[0x8]; 4480 u8 reserved_at_8[0x18]; 4481 4482 u8 syndrome[0x20]; 4483 4484 u8 reserved_at_40[0x40]; 4485 4486 struct mlx5_ifc_xrqc_bits xrq_context; 4487 }; 4488 4489 struct mlx5_ifc_query_xrq_in_bits { 4490 u8 opcode[0x10]; 4491 u8 reserved_at_10[0x10]; 4492 4493 u8 reserved_at_20[0x10]; 4494 u8 op_mod[0x10]; 4495 4496 u8 reserved_at_40[0x8]; 4497 u8 xrqn[0x18]; 4498 4499 u8 reserved_at_60[0x20]; 4500 }; 4501 4502 struct mlx5_ifc_resume_qp_out_bits { 4503 u8 status[0x8]; 4504 u8 reserved_0[0x18]; 4505 4506 u8 syndrome[0x20]; 4507 4508 u8 reserved_1[0x40]; 4509 }; 4510 4511 struct mlx5_ifc_resume_qp_in_bits { 4512 u8 opcode[0x10]; 4513 u8 reserved_0[0x10]; 4514 4515 u8 reserved_1[0x10]; 4516 u8 op_mod[0x10]; 4517 4518 u8 reserved_2[0x8]; 4519 u8 qpn[0x18]; 4520 4521 u8 reserved_3[0x20]; 4522 }; 4523 4524 struct mlx5_ifc_query_xrc_srq_out_bits { 4525 u8 status[0x8]; 4526 u8 reserved_0[0x18]; 4527 4528 u8 syndrome[0x20]; 4529 4530 u8 reserved_1[0x40]; 4531 4532 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4533 4534 u8 reserved_2[0x600]; 4535 4536 u8 pas[0][0x40]; 4537 }; 4538 4539 struct mlx5_ifc_query_xrc_srq_in_bits { 4540 u8 opcode[0x10]; 4541 u8 uid[0x10]; 4542 4543 u8 reserved_1[0x10]; 4544 u8 op_mod[0x10]; 4545 4546 u8 reserved_2[0x8]; 4547 u8 xrc_srqn[0x18]; 4548 4549 u8 reserved_3[0x20]; 4550 }; 4551 4552 struct mlx5_ifc_query_wol_rol_out_bits { 4553 u8 status[0x8]; 4554 u8 reserved_0[0x18]; 4555 4556 u8 syndrome[0x20]; 4557 4558 u8 reserved_1[0x10]; 4559 u8 rol_mode[0x8]; 4560 u8 wol_mode[0x8]; 4561 4562 u8 reserved_2[0x20]; 4563 }; 4564 4565 struct mlx5_ifc_query_wol_rol_in_bits { 4566 u8 opcode[0x10]; 4567 u8 reserved_0[0x10]; 4568 4569 u8 reserved_1[0x10]; 4570 u8 op_mod[0x10]; 4571 4572 u8 reserved_2[0x40]; 4573 }; 4574 4575 enum { 4576 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4577 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4578 }; 4579 4580 struct mlx5_ifc_query_vport_state_out_bits { 4581 u8 status[0x8]; 4582 u8 reserved_0[0x18]; 4583 4584 u8 syndrome[0x20]; 4585 4586 u8 reserved_1[0x20]; 4587 4588 u8 reserved_2[0x18]; 4589 u8 admin_state[0x4]; 4590 u8 state[0x4]; 4591 }; 4592 4593 enum { 4594 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0, 4595 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 4596 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_UPLINK = 0x2, 4597 }; 4598 4599 enum { 4600 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 4601 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 4602 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 4603 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 4604 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 4605 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 4606 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 4607 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 4608 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 4609 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 4610 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 4611 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000, 4612 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000, 4613 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 4614 }; 4615 4616 struct mlx5_ifc_query_vport_state_in_bits { 4617 u8 opcode[0x10]; 4618 u8 reserved_0[0x10]; 4619 4620 u8 reserved_1[0x10]; 4621 u8 op_mod[0x10]; 4622 4623 u8 other_vport[0x1]; 4624 u8 reserved_2[0xf]; 4625 u8 vport_number[0x10]; 4626 4627 u8 reserved_3[0x20]; 4628 }; 4629 4630 struct mlx5_ifc_query_vnic_env_out_bits { 4631 u8 status[0x8]; 4632 u8 reserved_at_8[0x18]; 4633 4634 u8 syndrome[0x20]; 4635 4636 u8 reserved_at_40[0x40]; 4637 4638 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4639 }; 4640 4641 enum { 4642 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 4643 }; 4644 4645 struct mlx5_ifc_query_vnic_env_in_bits { 4646 u8 opcode[0x10]; 4647 u8 reserved_at_10[0x10]; 4648 4649 u8 reserved_at_20[0x10]; 4650 u8 op_mod[0x10]; 4651 4652 u8 other_vport[0x1]; 4653 u8 reserved_at_41[0xf]; 4654 u8 vport_number[0x10]; 4655 4656 u8 reserved_at_60[0x20]; 4657 }; 4658 4659 struct mlx5_ifc_query_vport_counter_out_bits { 4660 u8 status[0x8]; 4661 u8 reserved_0[0x18]; 4662 4663 u8 syndrome[0x20]; 4664 4665 u8 reserved_1[0x40]; 4666 4667 struct mlx5_ifc_traffic_counter_bits received_errors; 4668 4669 struct mlx5_ifc_traffic_counter_bits transmit_errors; 4670 4671 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 4672 4673 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 4674 4675 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 4676 4677 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 4678 4679 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 4680 4681 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 4682 4683 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 4684 4685 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 4686 4687 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 4688 4689 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 4690 4691 u8 reserved_2[0xa00]; 4692 }; 4693 4694 enum { 4695 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 4696 }; 4697 4698 struct mlx5_ifc_query_vport_counter_in_bits { 4699 u8 opcode[0x10]; 4700 u8 reserved_0[0x10]; 4701 4702 u8 reserved_1[0x10]; 4703 u8 op_mod[0x10]; 4704 4705 u8 other_vport[0x1]; 4706 u8 reserved_2[0xb]; 4707 u8 port_num[0x4]; 4708 u8 vport_number[0x10]; 4709 4710 u8 reserved_3[0x60]; 4711 4712 u8 clear[0x1]; 4713 u8 reserved_4[0x1f]; 4714 4715 u8 reserved_5[0x20]; 4716 }; 4717 4718 struct mlx5_ifc_query_tis_out_bits { 4719 u8 status[0x8]; 4720 u8 reserved_0[0x18]; 4721 4722 u8 syndrome[0x20]; 4723 4724 u8 reserved_1[0x40]; 4725 4726 struct mlx5_ifc_tisc_bits tis_context; 4727 }; 4728 4729 struct mlx5_ifc_query_tis_in_bits { 4730 u8 opcode[0x10]; 4731 u8 reserved_0[0x10]; 4732 4733 u8 reserved_1[0x10]; 4734 u8 op_mod[0x10]; 4735 4736 u8 reserved_2[0x8]; 4737 u8 tisn[0x18]; 4738 4739 u8 reserved_3[0x20]; 4740 }; 4741 4742 struct mlx5_ifc_query_tir_out_bits { 4743 u8 status[0x8]; 4744 u8 reserved_0[0x18]; 4745 4746 u8 syndrome[0x20]; 4747 4748 u8 reserved_1[0xc0]; 4749 4750 struct mlx5_ifc_tirc_bits tir_context; 4751 }; 4752 4753 struct mlx5_ifc_query_tir_in_bits { 4754 u8 opcode[0x10]; 4755 u8 reserved_0[0x10]; 4756 4757 u8 reserved_1[0x10]; 4758 u8 op_mod[0x10]; 4759 4760 u8 reserved_2[0x8]; 4761 u8 tirn[0x18]; 4762 4763 u8 reserved_3[0x20]; 4764 }; 4765 4766 struct mlx5_ifc_query_srq_out_bits { 4767 u8 status[0x8]; 4768 u8 reserved_0[0x18]; 4769 4770 u8 syndrome[0x20]; 4771 4772 u8 reserved_1[0x40]; 4773 4774 struct mlx5_ifc_srqc_bits srq_context_entry; 4775 4776 u8 reserved_2[0x600]; 4777 4778 u8 pas[0][0x40]; 4779 }; 4780 4781 struct mlx5_ifc_query_srq_in_bits { 4782 u8 opcode[0x10]; 4783 u8 reserved_0[0x10]; 4784 4785 u8 reserved_1[0x10]; 4786 u8 op_mod[0x10]; 4787 4788 u8 reserved_2[0x8]; 4789 u8 srqn[0x18]; 4790 4791 u8 reserved_3[0x20]; 4792 }; 4793 4794 struct mlx5_ifc_query_sq_out_bits { 4795 u8 status[0x8]; 4796 u8 reserved_0[0x18]; 4797 4798 u8 syndrome[0x20]; 4799 4800 u8 reserved_1[0xc0]; 4801 4802 struct mlx5_ifc_sqc_bits sq_context; 4803 }; 4804 4805 struct mlx5_ifc_query_sq_in_bits { 4806 u8 opcode[0x10]; 4807 u8 reserved_0[0x10]; 4808 4809 u8 reserved_1[0x10]; 4810 u8 op_mod[0x10]; 4811 4812 u8 reserved_2[0x8]; 4813 u8 sqn[0x18]; 4814 4815 u8 reserved_3[0x20]; 4816 }; 4817 4818 struct mlx5_ifc_query_special_contexts_out_bits { 4819 u8 status[0x8]; 4820 u8 reserved_0[0x18]; 4821 4822 u8 syndrome[0x20]; 4823 4824 u8 dump_fill_mkey[0x20]; 4825 4826 u8 resd_lkey[0x20]; 4827 }; 4828 4829 struct mlx5_ifc_query_special_contexts_in_bits { 4830 u8 opcode[0x10]; 4831 u8 reserved_0[0x10]; 4832 4833 u8 reserved_1[0x10]; 4834 u8 op_mod[0x10]; 4835 4836 u8 reserved_2[0x40]; 4837 }; 4838 4839 struct mlx5_ifc_query_scheduling_element_out_bits { 4840 u8 status[0x8]; 4841 u8 reserved_at_8[0x18]; 4842 4843 u8 syndrome[0x20]; 4844 4845 u8 reserved_at_40[0xc0]; 4846 4847 struct mlx5_ifc_scheduling_context_bits scheduling_context; 4848 4849 u8 reserved_at_300[0x100]; 4850 }; 4851 4852 enum { 4853 MLX5_SCHEDULING_ELEMENT_IN_HIERARCHY_E_SWITCH = 0x2, 4854 }; 4855 4856 struct mlx5_ifc_query_scheduling_element_in_bits { 4857 u8 opcode[0x10]; 4858 u8 reserved_at_10[0x10]; 4859 4860 u8 reserved_at_20[0x10]; 4861 u8 op_mod[0x10]; 4862 4863 u8 scheduling_hierarchy[0x8]; 4864 u8 reserved_at_48[0x18]; 4865 4866 u8 scheduling_element_id[0x20]; 4867 4868 u8 reserved_at_80[0x180]; 4869 }; 4870 4871 struct mlx5_ifc_query_rqt_out_bits { 4872 u8 status[0x8]; 4873 u8 reserved_0[0x18]; 4874 4875 u8 syndrome[0x20]; 4876 4877 u8 reserved_1[0xc0]; 4878 4879 struct mlx5_ifc_rqtc_bits rqt_context; 4880 }; 4881 4882 struct mlx5_ifc_query_rqt_in_bits { 4883 u8 opcode[0x10]; 4884 u8 reserved_0[0x10]; 4885 4886 u8 reserved_1[0x10]; 4887 u8 op_mod[0x10]; 4888 4889 u8 reserved_2[0x8]; 4890 u8 rqtn[0x18]; 4891 4892 u8 reserved_3[0x20]; 4893 }; 4894 4895 struct mlx5_ifc_query_rq_out_bits { 4896 u8 status[0x8]; 4897 u8 reserved_0[0x18]; 4898 4899 u8 syndrome[0x20]; 4900 4901 u8 reserved_1[0xc0]; 4902 4903 struct mlx5_ifc_rqc_bits rq_context; 4904 }; 4905 4906 struct mlx5_ifc_query_rq_in_bits { 4907 u8 opcode[0x10]; 4908 u8 reserved_0[0x10]; 4909 4910 u8 reserved_1[0x10]; 4911 u8 op_mod[0x10]; 4912 4913 u8 reserved_2[0x8]; 4914 u8 rqn[0x18]; 4915 4916 u8 reserved_3[0x20]; 4917 }; 4918 4919 struct mlx5_ifc_query_roce_address_out_bits { 4920 u8 status[0x8]; 4921 u8 reserved_0[0x18]; 4922 4923 u8 syndrome[0x20]; 4924 4925 u8 reserved_1[0x40]; 4926 4927 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4928 }; 4929 4930 struct mlx5_ifc_query_roce_address_in_bits { 4931 u8 opcode[0x10]; 4932 u8 reserved_0[0x10]; 4933 4934 u8 reserved_1[0x10]; 4935 u8 op_mod[0x10]; 4936 4937 u8 roce_address_index[0x10]; 4938 u8 reserved_2[0x10]; 4939 4940 u8 reserved_3[0x20]; 4941 }; 4942 4943 struct mlx5_ifc_query_rmp_out_bits { 4944 u8 status[0x8]; 4945 u8 reserved_0[0x18]; 4946 4947 u8 syndrome[0x20]; 4948 4949 u8 reserved_1[0xc0]; 4950 4951 struct mlx5_ifc_rmpc_bits rmp_context; 4952 }; 4953 4954 struct mlx5_ifc_query_rmp_in_bits { 4955 u8 opcode[0x10]; 4956 u8 reserved_0[0x10]; 4957 4958 u8 reserved_1[0x10]; 4959 u8 op_mod[0x10]; 4960 4961 u8 reserved_2[0x8]; 4962 u8 rmpn[0x18]; 4963 4964 u8 reserved_3[0x20]; 4965 }; 4966 4967 struct mlx5_ifc_query_rdb_out_bits { 4968 u8 status[0x8]; 4969 u8 reserved_0[0x18]; 4970 4971 u8 syndrome[0x20]; 4972 4973 u8 reserved_1[0x20]; 4974 4975 u8 reserved_2[0x18]; 4976 u8 rdb_list_size[0x8]; 4977 4978 struct mlx5_ifc_rdbc_bits rdb_context[0]; 4979 }; 4980 4981 struct mlx5_ifc_query_rdb_in_bits { 4982 u8 opcode[0x10]; 4983 u8 reserved_0[0x10]; 4984 4985 u8 reserved_1[0x10]; 4986 u8 op_mod[0x10]; 4987 4988 u8 reserved_2[0x8]; 4989 u8 qpn[0x18]; 4990 4991 u8 reserved_3[0x20]; 4992 }; 4993 4994 struct mlx5_ifc_query_qp_out_bits { 4995 u8 status[0x8]; 4996 u8 reserved_0[0x18]; 4997 4998 u8 syndrome[0x20]; 4999 5000 u8 reserved_1[0x40]; 5001 5002 u8 opt_param_mask[0x20]; 5003 5004 u8 reserved_2[0x20]; 5005 5006 struct mlx5_ifc_qpc_bits qpc; 5007 5008 u8 reserved_3[0x80]; 5009 5010 u8 pas[0][0x40]; 5011 }; 5012 5013 struct mlx5_ifc_query_qp_in_bits { 5014 u8 opcode[0x10]; 5015 u8 reserved_0[0x10]; 5016 5017 u8 reserved_1[0x10]; 5018 u8 op_mod[0x10]; 5019 5020 u8 reserved_2[0x8]; 5021 u8 qpn[0x18]; 5022 5023 u8 reserved_3[0x20]; 5024 }; 5025 5026 struct mlx5_ifc_query_q_counter_out_bits { 5027 u8 status[0x8]; 5028 u8 reserved_0[0x18]; 5029 5030 u8 syndrome[0x20]; 5031 5032 u8 reserved_1[0x40]; 5033 5034 u8 rx_write_requests[0x20]; 5035 5036 u8 reserved_2[0x20]; 5037 5038 u8 rx_read_requests[0x20]; 5039 5040 u8 reserved_3[0x20]; 5041 5042 u8 rx_atomic_requests[0x20]; 5043 5044 u8 reserved_4[0x20]; 5045 5046 u8 rx_dct_connect[0x20]; 5047 5048 u8 reserved_5[0x20]; 5049 5050 u8 out_of_buffer[0x20]; 5051 5052 u8 reserved_7[0x20]; 5053 5054 u8 out_of_sequence[0x20]; 5055 5056 u8 reserved_8[0x20]; 5057 5058 u8 duplicate_request[0x20]; 5059 5060 u8 reserved_9[0x20]; 5061 5062 u8 rnr_nak_retry_err[0x20]; 5063 5064 u8 reserved_10[0x20]; 5065 5066 u8 packet_seq_err[0x20]; 5067 5068 u8 reserved_11[0x20]; 5069 5070 u8 implied_nak_seq_err[0x20]; 5071 5072 u8 reserved_12[0x20]; 5073 5074 u8 local_ack_timeout_err[0x20]; 5075 5076 u8 reserved_13[0x20]; 5077 5078 u8 resp_rnr_nak[0x20]; 5079 5080 u8 reserved_14[0x20]; 5081 5082 u8 req_rnr_retries_exceeded[0x20]; 5083 5084 u8 reserved_15[0x460]; 5085 }; 5086 5087 struct mlx5_ifc_query_q_counter_in_bits { 5088 u8 opcode[0x10]; 5089 u8 reserved_0[0x10]; 5090 5091 u8 reserved_1[0x10]; 5092 u8 op_mod[0x10]; 5093 5094 u8 reserved_2[0x80]; 5095 5096 u8 clear[0x1]; 5097 u8 reserved_3[0x1f]; 5098 5099 u8 reserved_4[0x18]; 5100 u8 counter_set_id[0x8]; 5101 }; 5102 5103 struct mlx5_ifc_query_pages_out_bits { 5104 u8 status[0x8]; 5105 u8 reserved_0[0x18]; 5106 5107 u8 syndrome[0x20]; 5108 5109 u8 reserved_1[0x10]; 5110 u8 function_id[0x10]; 5111 5112 u8 num_pages[0x20]; 5113 }; 5114 5115 enum { 5116 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5117 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5118 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5119 }; 5120 5121 struct mlx5_ifc_query_pages_in_bits { 5122 u8 opcode[0x10]; 5123 u8 reserved_0[0x10]; 5124 5125 u8 reserved_1[0x10]; 5126 u8 op_mod[0x10]; 5127 5128 u8 reserved_2[0x10]; 5129 u8 function_id[0x10]; 5130 5131 u8 reserved_3[0x20]; 5132 }; 5133 5134 struct mlx5_ifc_query_nic_vport_context_out_bits { 5135 u8 status[0x8]; 5136 u8 reserved_0[0x18]; 5137 5138 u8 syndrome[0x20]; 5139 5140 u8 reserved_1[0x40]; 5141 5142 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5143 }; 5144 5145 struct mlx5_ifc_query_nic_vport_context_in_bits { 5146 u8 opcode[0x10]; 5147 u8 reserved_0[0x10]; 5148 5149 u8 reserved_1[0x10]; 5150 u8 op_mod[0x10]; 5151 5152 u8 other_vport[0x1]; 5153 u8 reserved_2[0xf]; 5154 u8 vport_number[0x10]; 5155 5156 u8 reserved_3[0x5]; 5157 u8 allowed_list_type[0x3]; 5158 u8 reserved_4[0x18]; 5159 }; 5160 5161 struct mlx5_ifc_query_mkey_out_bits { 5162 u8 status[0x8]; 5163 u8 reserved_0[0x18]; 5164 5165 u8 syndrome[0x20]; 5166 5167 u8 reserved_1[0x40]; 5168 5169 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5170 5171 u8 reserved_2[0x600]; 5172 5173 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5174 5175 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5176 }; 5177 5178 struct mlx5_ifc_query_mkey_in_bits { 5179 u8 opcode[0x10]; 5180 u8 reserved_0[0x10]; 5181 5182 u8 reserved_1[0x10]; 5183 u8 op_mod[0x10]; 5184 5185 u8 reserved_2[0x8]; 5186 u8 mkey_index[0x18]; 5187 5188 u8 pg_access[0x1]; 5189 u8 reserved_3[0x1f]; 5190 }; 5191 5192 struct mlx5_ifc_query_mad_demux_out_bits { 5193 u8 status[0x8]; 5194 u8 reserved_0[0x18]; 5195 5196 u8 syndrome[0x20]; 5197 5198 u8 reserved_1[0x40]; 5199 5200 u8 mad_dumux_parameters_block[0x20]; 5201 }; 5202 5203 struct mlx5_ifc_query_mad_demux_in_bits { 5204 u8 opcode[0x10]; 5205 u8 reserved_0[0x10]; 5206 5207 u8 reserved_1[0x10]; 5208 u8 op_mod[0x10]; 5209 5210 u8 reserved_2[0x40]; 5211 }; 5212 5213 struct mlx5_ifc_query_l2_table_entry_out_bits { 5214 u8 status[0x8]; 5215 u8 reserved_0[0x18]; 5216 5217 u8 syndrome[0x20]; 5218 5219 u8 reserved_1[0xa0]; 5220 5221 u8 reserved_2[0x13]; 5222 u8 vlan_valid[0x1]; 5223 u8 vlan[0xc]; 5224 5225 struct mlx5_ifc_mac_address_layout_bits mac_address; 5226 5227 u8 reserved_3[0xc0]; 5228 }; 5229 5230 struct mlx5_ifc_query_l2_table_entry_in_bits { 5231 u8 opcode[0x10]; 5232 u8 reserved_0[0x10]; 5233 5234 u8 reserved_1[0x10]; 5235 u8 op_mod[0x10]; 5236 5237 u8 reserved_2[0x60]; 5238 5239 u8 reserved_3[0x8]; 5240 u8 table_index[0x18]; 5241 5242 u8 reserved_4[0x140]; 5243 }; 5244 5245 struct mlx5_ifc_query_issi_out_bits { 5246 u8 status[0x8]; 5247 u8 reserved_0[0x18]; 5248 5249 u8 syndrome[0x20]; 5250 5251 u8 reserved_1[0x10]; 5252 u8 current_issi[0x10]; 5253 5254 u8 reserved_2[0xa0]; 5255 5256 u8 supported_issi_reserved[76][0x8]; 5257 u8 supported_issi_dw0[0x20]; 5258 }; 5259 5260 struct mlx5_ifc_query_issi_in_bits { 5261 u8 opcode[0x10]; 5262 u8 reserved_0[0x10]; 5263 5264 u8 reserved_1[0x10]; 5265 u8 op_mod[0x10]; 5266 5267 u8 reserved_2[0x40]; 5268 }; 5269 5270 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5271 u8 status[0x8]; 5272 u8 reserved_0[0x18]; 5273 5274 u8 syndrome[0x20]; 5275 5276 u8 reserved_1[0x40]; 5277 5278 struct mlx5_ifc_pkey_bits pkey[0]; 5279 }; 5280 5281 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5282 u8 opcode[0x10]; 5283 u8 reserved_0[0x10]; 5284 5285 u8 reserved_1[0x10]; 5286 u8 op_mod[0x10]; 5287 5288 u8 other_vport[0x1]; 5289 u8 reserved_2[0xb]; 5290 u8 port_num[0x4]; 5291 u8 vport_number[0x10]; 5292 5293 u8 reserved_3[0x10]; 5294 u8 pkey_index[0x10]; 5295 }; 5296 5297 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5298 u8 status[0x8]; 5299 u8 reserved_0[0x18]; 5300 5301 u8 syndrome[0x20]; 5302 5303 u8 reserved_1[0x20]; 5304 5305 u8 gids_num[0x10]; 5306 u8 reserved_2[0x10]; 5307 5308 struct mlx5_ifc_array128_auto_bits gid[0]; 5309 }; 5310 5311 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5312 u8 opcode[0x10]; 5313 u8 reserved_0[0x10]; 5314 5315 u8 reserved_1[0x10]; 5316 u8 op_mod[0x10]; 5317 5318 u8 other_vport[0x1]; 5319 u8 reserved_2[0xb]; 5320 u8 port_num[0x4]; 5321 u8 vport_number[0x10]; 5322 5323 u8 reserved_3[0x10]; 5324 u8 gid_index[0x10]; 5325 }; 5326 5327 struct mlx5_ifc_query_hca_vport_context_out_bits { 5328 u8 status[0x8]; 5329 u8 reserved_0[0x18]; 5330 5331 u8 syndrome[0x20]; 5332 5333 u8 reserved_1[0x40]; 5334 5335 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5336 }; 5337 5338 struct mlx5_ifc_query_hca_vport_context_in_bits { 5339 u8 opcode[0x10]; 5340 u8 reserved_0[0x10]; 5341 5342 u8 reserved_1[0x10]; 5343 u8 op_mod[0x10]; 5344 5345 u8 other_vport[0x1]; 5346 u8 reserved_2[0xb]; 5347 u8 port_num[0x4]; 5348 u8 vport_number[0x10]; 5349 5350 u8 reserved_3[0x20]; 5351 }; 5352 5353 struct mlx5_ifc_query_hca_cap_out_bits { 5354 u8 status[0x8]; 5355 u8 reserved_0[0x18]; 5356 5357 u8 syndrome[0x20]; 5358 5359 u8 reserved_1[0x40]; 5360 5361 union mlx5_ifc_hca_cap_union_bits capability; 5362 }; 5363 5364 struct mlx5_ifc_query_hca_cap_in_bits { 5365 u8 opcode[0x10]; 5366 u8 reserved_0[0x10]; 5367 5368 u8 reserved_1[0x10]; 5369 u8 op_mod[0x10]; 5370 5371 u8 reserved_2[0x40]; 5372 }; 5373 5374 struct mlx5_ifc_query_flow_table_out_bits { 5375 u8 status[0x8]; 5376 u8 reserved_at_8[0x18]; 5377 5378 u8 syndrome[0x20]; 5379 5380 u8 reserved_at_40[0x80]; 5381 5382 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5383 }; 5384 5385 struct mlx5_ifc_query_flow_table_in_bits { 5386 u8 opcode[0x10]; 5387 u8 reserved_0[0x10]; 5388 5389 u8 reserved_1[0x10]; 5390 u8 op_mod[0x10]; 5391 5392 u8 other_vport[0x1]; 5393 u8 reserved_2[0xf]; 5394 u8 vport_number[0x10]; 5395 5396 u8 reserved_3[0x20]; 5397 5398 u8 table_type[0x8]; 5399 u8 reserved_4[0x18]; 5400 5401 u8 reserved_5[0x8]; 5402 u8 table_id[0x18]; 5403 5404 u8 reserved_6[0x140]; 5405 }; 5406 5407 struct mlx5_ifc_query_fte_out_bits { 5408 u8 status[0x8]; 5409 u8 reserved_0[0x18]; 5410 5411 u8 syndrome[0x20]; 5412 5413 u8 reserved_1[0x1c0]; 5414 5415 struct mlx5_ifc_flow_context_bits flow_context; 5416 }; 5417 5418 struct mlx5_ifc_query_fte_in_bits { 5419 u8 opcode[0x10]; 5420 u8 reserved_0[0x10]; 5421 5422 u8 reserved_1[0x10]; 5423 u8 op_mod[0x10]; 5424 5425 u8 other_vport[0x1]; 5426 u8 reserved_2[0xf]; 5427 u8 vport_number[0x10]; 5428 5429 u8 reserved_3[0x20]; 5430 5431 u8 table_type[0x8]; 5432 u8 reserved_4[0x18]; 5433 5434 u8 reserved_5[0x8]; 5435 u8 table_id[0x18]; 5436 5437 u8 reserved_6[0x40]; 5438 5439 u8 flow_index[0x20]; 5440 5441 u8 reserved_7[0xe0]; 5442 }; 5443 5444 enum { 5445 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 5446 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 5447 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 5448 }; 5449 5450 struct mlx5_ifc_query_flow_group_out_bits { 5451 u8 status[0x8]; 5452 u8 reserved_0[0x18]; 5453 5454 u8 syndrome[0x20]; 5455 5456 u8 reserved_1[0xa0]; 5457 5458 u8 start_flow_index[0x20]; 5459 5460 u8 reserved_2[0x20]; 5461 5462 u8 end_flow_index[0x20]; 5463 5464 u8 reserved_3[0xa0]; 5465 5466 u8 reserved_4[0x18]; 5467 u8 match_criteria_enable[0x8]; 5468 5469 struct mlx5_ifc_fte_match_param_bits match_criteria; 5470 5471 u8 reserved_5[0xe00]; 5472 }; 5473 5474 struct mlx5_ifc_query_flow_group_in_bits { 5475 u8 opcode[0x10]; 5476 u8 reserved_0[0x10]; 5477 5478 u8 reserved_1[0x10]; 5479 u8 op_mod[0x10]; 5480 5481 u8 other_vport[0x1]; 5482 u8 reserved_2[0xf]; 5483 u8 vport_number[0x10]; 5484 5485 u8 reserved_3[0x20]; 5486 5487 u8 table_type[0x8]; 5488 u8 reserved_4[0x18]; 5489 5490 u8 reserved_5[0x8]; 5491 u8 table_id[0x18]; 5492 5493 u8 group_id[0x20]; 5494 5495 u8 reserved_6[0x120]; 5496 }; 5497 5498 struct mlx5_ifc_query_flow_counter_out_bits { 5499 u8 status[0x8]; 5500 u8 reserved_at_8[0x18]; 5501 5502 u8 syndrome[0x20]; 5503 5504 u8 reserved_at_40[0x40]; 5505 5506 struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; 5507 }; 5508 5509 struct mlx5_ifc_query_flow_counter_in_bits { 5510 u8 opcode[0x10]; 5511 u8 reserved_at_10[0x10]; 5512 5513 u8 reserved_at_20[0x10]; 5514 u8 op_mod[0x10]; 5515 5516 u8 reserved_at_40[0x80]; 5517 5518 u8 clear[0x1]; 5519 u8 reserved_at_c1[0xf]; 5520 u8 num_of_counters[0x10]; 5521 5522 u8 reserved_at_e0[0x10]; 5523 u8 flow_counter_id[0x10]; 5524 }; 5525 5526 struct mlx5_ifc_query_esw_vport_context_out_bits { 5527 u8 status[0x8]; 5528 u8 reserved_0[0x18]; 5529 5530 u8 syndrome[0x20]; 5531 5532 u8 reserved_1[0x40]; 5533 5534 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 5535 }; 5536 5537 struct mlx5_ifc_query_esw_vport_context_in_bits { 5538 u8 opcode[0x10]; 5539 u8 reserved_0[0x10]; 5540 5541 u8 reserved_1[0x10]; 5542 u8 op_mod[0x10]; 5543 5544 u8 other_vport[0x1]; 5545 u8 reserved_2[0xf]; 5546 u8 vport_number[0x10]; 5547 5548 u8 reserved_3[0x20]; 5549 }; 5550 5551 struct mlx5_ifc_query_eq_out_bits { 5552 u8 status[0x8]; 5553 u8 reserved_0[0x18]; 5554 5555 u8 syndrome[0x20]; 5556 5557 u8 reserved_1[0x40]; 5558 5559 struct mlx5_ifc_eqc_bits eq_context_entry; 5560 5561 u8 reserved_2[0x40]; 5562 5563 u8 event_bitmask[0x40]; 5564 5565 u8 reserved_3[0x580]; 5566 5567 u8 pas[0][0x40]; 5568 }; 5569 5570 struct mlx5_ifc_query_eq_in_bits { 5571 u8 opcode[0x10]; 5572 u8 reserved_0[0x10]; 5573 5574 u8 reserved_1[0x10]; 5575 u8 op_mod[0x10]; 5576 5577 u8 reserved_2[0x18]; 5578 u8 eq_number[0x8]; 5579 5580 u8 reserved_3[0x20]; 5581 }; 5582 5583 struct mlx5_ifc_set_action_in_bits { 5584 u8 action_type[0x4]; 5585 u8 field[0xc]; 5586 u8 reserved_at_10[0x3]; 5587 u8 offset[0x5]; 5588 u8 reserved_at_18[0x3]; 5589 u8 length[0x5]; 5590 5591 u8 data[0x20]; 5592 }; 5593 5594 struct mlx5_ifc_add_action_in_bits { 5595 u8 action_type[0x4]; 5596 u8 field[0xc]; 5597 u8 reserved_at_10[0x10]; 5598 5599 u8 data[0x20]; 5600 }; 5601 5602 struct mlx5_ifc_copy_action_in_bits { 5603 u8 action_type[0x4]; 5604 u8 src_field[0xc]; 5605 u8 reserved_at_10[0x3]; 5606 u8 src_offset[0x5]; 5607 u8 reserved_at_18[0x3]; 5608 u8 length[0x5]; 5609 5610 u8 reserved_at_20[0x4]; 5611 u8 dst_field[0xc]; 5612 u8 reserved_at_30[0x3]; 5613 u8 dst_offset[0x5]; 5614 u8 reserved_at_38[0x8]; 5615 }; 5616 5617 union mlx5_ifc_set_add_copy_action_in_auto_bits { 5618 struct mlx5_ifc_set_action_in_bits set_action_in; 5619 struct mlx5_ifc_add_action_in_bits add_action_in; 5620 struct mlx5_ifc_copy_action_in_bits copy_action_in; 5621 u8 reserved_at_0[0x40]; 5622 }; 5623 5624 enum { 5625 MLX5_ACTION_TYPE_SET = 0x1, 5626 MLX5_ACTION_TYPE_ADD = 0x2, 5627 MLX5_ACTION_TYPE_COPY = 0x3, 5628 }; 5629 5630 enum { 5631 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 5632 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 5633 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 5634 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 5635 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 5636 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 5637 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 5638 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 5639 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 5640 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 5641 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 5642 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 5643 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 5644 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 5645 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 5646 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 5647 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 5648 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 5649 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 5650 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 5651 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 5652 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 5653 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 5654 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 5655 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 5656 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 5657 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 5658 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 5659 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 5660 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 5661 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 5662 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 5663 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 5664 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 5665 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 5666 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 5667 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 5668 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 5669 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 5670 }; 5671 5672 struct mlx5_ifc_alloc_modify_header_context_out_bits { 5673 u8 status[0x8]; 5674 u8 reserved_at_8[0x18]; 5675 5676 u8 syndrome[0x20]; 5677 5678 u8 modify_header_id[0x20]; 5679 5680 u8 reserved_at_60[0x20]; 5681 }; 5682 5683 struct mlx5_ifc_alloc_modify_header_context_in_bits { 5684 u8 opcode[0x10]; 5685 u8 reserved_at_10[0x10]; 5686 5687 u8 reserved_at_20[0x10]; 5688 u8 op_mod[0x10]; 5689 5690 u8 reserved_at_40[0x20]; 5691 5692 u8 table_type[0x8]; 5693 u8 reserved_at_68[0x10]; 5694 u8 num_of_actions[0x8]; 5695 5696 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 5697 }; 5698 5699 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 5700 u8 status[0x8]; 5701 u8 reserved_at_8[0x18]; 5702 5703 u8 syndrome[0x20]; 5704 5705 u8 reserved_at_40[0x40]; 5706 }; 5707 5708 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 5709 u8 opcode[0x10]; 5710 u8 reserved_at_10[0x10]; 5711 5712 u8 reserved_at_20[0x10]; 5713 u8 op_mod[0x10]; 5714 5715 u8 modify_header_id[0x20]; 5716 5717 u8 reserved_at_60[0x20]; 5718 }; 5719 5720 struct mlx5_ifc_query_modify_header_context_in_bits { 5721 u8 opcode[0x10]; 5722 u8 uid[0x10]; 5723 5724 u8 reserved_at_20[0x10]; 5725 u8 op_mod[0x10]; 5726 5727 u8 modify_header_id[0x20]; 5728 5729 u8 reserved_at_60[0xa0]; 5730 }; 5731 5732 struct mlx5_ifc_query_dct_out_bits { 5733 u8 status[0x8]; 5734 u8 reserved_0[0x18]; 5735 5736 u8 syndrome[0x20]; 5737 5738 u8 reserved_1[0x40]; 5739 5740 struct mlx5_ifc_dctc_bits dct_context_entry; 5741 5742 u8 reserved_2[0x180]; 5743 }; 5744 5745 struct mlx5_ifc_query_dct_in_bits { 5746 u8 opcode[0x10]; 5747 u8 reserved_0[0x10]; 5748 5749 u8 reserved_1[0x10]; 5750 u8 op_mod[0x10]; 5751 5752 u8 reserved_2[0x8]; 5753 u8 dctn[0x18]; 5754 5755 u8 reserved_3[0x20]; 5756 }; 5757 5758 struct mlx5_ifc_query_dc_cnak_trace_out_bits { 5759 u8 status[0x8]; 5760 u8 reserved_0[0x18]; 5761 5762 u8 syndrome[0x20]; 5763 5764 u8 enable[0x1]; 5765 u8 reserved_1[0x1f]; 5766 5767 u8 reserved_2[0x160]; 5768 5769 struct mlx5_ifc_cmd_pas_bits pas; 5770 }; 5771 5772 struct mlx5_ifc_query_dc_cnak_trace_in_bits { 5773 u8 opcode[0x10]; 5774 u8 reserved_0[0x10]; 5775 5776 u8 reserved_1[0x10]; 5777 u8 op_mod[0x10]; 5778 5779 u8 reserved_2[0x40]; 5780 }; 5781 5782 struct mlx5_ifc_packet_reformat_context_in_bits { 5783 u8 reformat_type[0x8]; 5784 u8 reserved_at_8[0x4]; 5785 u8 reformat_param_0[0x4]; 5786 u8 reserved_at_10[0x6]; 5787 u8 reformat_data_size[0xa]; 5788 5789 u8 reformat_param_1[0x8]; 5790 u8 reserved_at_28[0x8]; 5791 u8 reformat_data[2][0x8]; 5792 5793 u8 more_reformat_data[][0x8]; 5794 }; 5795 5796 struct mlx5_ifc_query_packet_reformat_context_out_bits { 5797 u8 status[0x8]; 5798 u8 reserved_at_8[0x18]; 5799 5800 u8 syndrome[0x20]; 5801 5802 u8 reserved_at_40[0xa0]; 5803 5804 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0]; 5805 }; 5806 5807 struct mlx5_ifc_query_packet_reformat_context_in_bits { 5808 u8 opcode[0x10]; 5809 u8 reserved_at_10[0x10]; 5810 5811 u8 reserved_at_20[0x10]; 5812 u8 op_mod[0x10]; 5813 5814 u8 packet_reformat_id[0x20]; 5815 5816 u8 reserved_at_60[0xa0]; 5817 }; 5818 5819 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 5820 u8 status[0x8]; 5821 u8 reserved_at_8[0x18]; 5822 5823 u8 syndrome[0x20]; 5824 5825 u8 packet_reformat_id[0x20]; 5826 5827 u8 reserved_at_60[0x20]; 5828 }; 5829 5830 enum mlx5_reformat_ctx_type { 5831 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 5832 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 5833 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 5834 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 5835 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 5836 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5, 5837 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7, 5838 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8, 5839 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa, 5840 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb, 5841 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc, 5842 }; 5843 5844 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 5845 u8 opcode[0x10]; 5846 u8 reserved_at_10[0x10]; 5847 5848 u8 reserved_at_20[0x10]; 5849 u8 op_mod[0x10]; 5850 5851 u8 reserved_at_40[0xa0]; 5852 5853 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 5854 }; 5855 5856 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 5857 u8 status[0x8]; 5858 u8 reserved_at_8[0x18]; 5859 5860 u8 syndrome[0x20]; 5861 5862 u8 reserved_at_40[0x40]; 5863 }; 5864 5865 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 5866 u8 opcode[0x10]; 5867 u8 reserved_at_10[0x10]; 5868 5869 u8 reserved_20[0x10]; 5870 u8 op_mod[0x10]; 5871 5872 u8 packet_reformat_id[0x20]; 5873 5874 u8 reserved_60[0x20]; 5875 }; 5876 5877 struct mlx5_ifc_diagnostic_cntr_struct_bits { 5878 u8 counter_id[0x10]; 5879 u8 sample_id[0x10]; 5880 5881 u8 time_stamp_31_0[0x20]; 5882 5883 u8 counter_value_h[0x20]; 5884 5885 u8 counter_value_l[0x20]; 5886 }; 5887 5888 enum { 5889 MLX5_DIAGNOSTIC_PARAMS_CONTEXT_ENABLE_ENABLE = 0x1, 5890 MLX5_DIAGNOSTIC_PARAMS_CONTEXT_ENABLE_DISABLE = 0x0, 5891 }; 5892 5893 struct mlx5_ifc_query_cq_out_bits { 5894 u8 status[0x8]; 5895 u8 reserved_0[0x18]; 5896 5897 u8 syndrome[0x20]; 5898 5899 u8 reserved_1[0x40]; 5900 5901 struct mlx5_ifc_cqc_bits cq_context; 5902 5903 u8 reserved_2[0x600]; 5904 5905 u8 pas[0][0x40]; 5906 }; 5907 5908 struct mlx5_ifc_query_cq_in_bits { 5909 u8 opcode[0x10]; 5910 u8 reserved_0[0x10]; 5911 5912 u8 reserved_1[0x10]; 5913 u8 op_mod[0x10]; 5914 5915 u8 reserved_2[0x8]; 5916 u8 cqn[0x18]; 5917 5918 u8 reserved_3[0x20]; 5919 }; 5920 5921 struct mlx5_ifc_query_cong_status_out_bits { 5922 u8 status[0x8]; 5923 u8 reserved_0[0x18]; 5924 5925 u8 syndrome[0x20]; 5926 5927 u8 reserved_1[0x20]; 5928 5929 u8 enable[0x1]; 5930 u8 tag_enable[0x1]; 5931 u8 reserved_2[0x1e]; 5932 }; 5933 5934 struct mlx5_ifc_query_cong_status_in_bits { 5935 u8 opcode[0x10]; 5936 u8 reserved_0[0x10]; 5937 5938 u8 reserved_1[0x10]; 5939 u8 op_mod[0x10]; 5940 5941 u8 reserved_2[0x18]; 5942 u8 priority[0x4]; 5943 u8 cong_protocol[0x4]; 5944 5945 u8 reserved_3[0x20]; 5946 }; 5947 5948 struct mlx5_ifc_query_cong_statistics_out_bits { 5949 u8 status[0x8]; 5950 u8 reserved_0[0x18]; 5951 5952 u8 syndrome[0x20]; 5953 5954 u8 reserved_1[0x40]; 5955 5956 u8 rp_cur_flows[0x20]; 5957 5958 u8 sum_flows[0x20]; 5959 5960 u8 rp_cnp_ignored_high[0x20]; 5961 5962 u8 rp_cnp_ignored_low[0x20]; 5963 5964 u8 rp_cnp_handled_high[0x20]; 5965 5966 u8 rp_cnp_handled_low[0x20]; 5967 5968 u8 reserved_2[0x100]; 5969 5970 u8 time_stamp_high[0x20]; 5971 5972 u8 time_stamp_low[0x20]; 5973 5974 u8 accumulators_period[0x20]; 5975 5976 u8 np_ecn_marked_roce_packets_high[0x20]; 5977 5978 u8 np_ecn_marked_roce_packets_low[0x20]; 5979 5980 u8 np_cnp_sent_high[0x20]; 5981 5982 u8 np_cnp_sent_low[0x20]; 5983 5984 u8 reserved_3[0x560]; 5985 }; 5986 5987 struct mlx5_ifc_query_cong_statistics_in_bits { 5988 u8 opcode[0x10]; 5989 u8 reserved_0[0x10]; 5990 5991 u8 reserved_1[0x10]; 5992 u8 op_mod[0x10]; 5993 5994 u8 clear[0x1]; 5995 u8 reserved_2[0x1f]; 5996 5997 u8 reserved_3[0x20]; 5998 }; 5999 6000 struct mlx5_ifc_query_cong_params_out_bits { 6001 u8 status[0x8]; 6002 u8 reserved_0[0x18]; 6003 6004 u8 syndrome[0x20]; 6005 6006 u8 reserved_1[0x40]; 6007 6008 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6009 }; 6010 6011 struct mlx5_ifc_query_cong_params_in_bits { 6012 u8 opcode[0x10]; 6013 u8 reserved_0[0x10]; 6014 6015 u8 reserved_1[0x10]; 6016 u8 op_mod[0x10]; 6017 6018 u8 reserved_2[0x1c]; 6019 u8 cong_protocol[0x4]; 6020 6021 u8 reserved_3[0x20]; 6022 }; 6023 6024 struct mlx5_ifc_query_burst_size_out_bits { 6025 u8 status[0x8]; 6026 u8 reserved_0[0x18]; 6027 6028 u8 syndrome[0x20]; 6029 6030 u8 reserved_1[0x20]; 6031 6032 u8 reserved_2[0x9]; 6033 u8 device_burst_size[0x17]; 6034 }; 6035 6036 struct mlx5_ifc_query_burst_size_in_bits { 6037 u8 opcode[0x10]; 6038 u8 reserved_0[0x10]; 6039 6040 u8 reserved_1[0x10]; 6041 u8 op_mod[0x10]; 6042 6043 u8 reserved_2[0x40]; 6044 }; 6045 6046 struct mlx5_ifc_query_adapter_out_bits { 6047 u8 status[0x8]; 6048 u8 reserved_0[0x18]; 6049 6050 u8 syndrome[0x20]; 6051 6052 u8 reserved_1[0x40]; 6053 6054 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 6055 }; 6056 6057 struct mlx5_ifc_query_adapter_in_bits { 6058 u8 opcode[0x10]; 6059 u8 reserved_0[0x10]; 6060 6061 u8 reserved_1[0x10]; 6062 u8 op_mod[0x10]; 6063 6064 u8 reserved_2[0x40]; 6065 }; 6066 6067 struct mlx5_ifc_qp_2rst_out_bits { 6068 u8 status[0x8]; 6069 u8 reserved_0[0x18]; 6070 6071 u8 syndrome[0x20]; 6072 6073 u8 reserved_1[0x40]; 6074 }; 6075 6076 struct mlx5_ifc_qp_2rst_in_bits { 6077 u8 opcode[0x10]; 6078 u8 uid[0x10]; 6079 6080 u8 reserved_1[0x10]; 6081 u8 op_mod[0x10]; 6082 6083 u8 reserved_2[0x8]; 6084 u8 qpn[0x18]; 6085 6086 u8 reserved_3[0x20]; 6087 }; 6088 6089 struct mlx5_ifc_qp_2err_out_bits { 6090 u8 status[0x8]; 6091 u8 reserved_0[0x18]; 6092 6093 u8 syndrome[0x20]; 6094 6095 u8 reserved_1[0x40]; 6096 }; 6097 6098 struct mlx5_ifc_qp_2err_in_bits { 6099 u8 opcode[0x10]; 6100 u8 uid[0x10]; 6101 6102 u8 reserved_1[0x10]; 6103 u8 op_mod[0x10]; 6104 6105 u8 reserved_2[0x8]; 6106 u8 qpn[0x18]; 6107 6108 u8 reserved_3[0x20]; 6109 }; 6110 6111 struct mlx5_ifc_para_vport_element_bits { 6112 u8 reserved_at_0[0xc]; 6113 u8 traffic_class[0x4]; 6114 u8 qos_para_vport_number[0x10]; 6115 }; 6116 6117 struct mlx5_ifc_page_fault_resume_out_bits { 6118 u8 status[0x8]; 6119 u8 reserved_0[0x18]; 6120 6121 u8 syndrome[0x20]; 6122 6123 u8 reserved_1[0x40]; 6124 }; 6125 6126 struct mlx5_ifc_page_fault_resume_in_bits { 6127 u8 opcode[0x10]; 6128 u8 reserved_0[0x10]; 6129 6130 u8 reserved_1[0x10]; 6131 u8 op_mod[0x10]; 6132 6133 u8 error[0x1]; 6134 u8 reserved_2[0x4]; 6135 u8 rdma[0x1]; 6136 u8 read_write[0x1]; 6137 u8 req_res[0x1]; 6138 u8 qpn[0x18]; 6139 6140 u8 reserved_3[0x20]; 6141 }; 6142 6143 struct mlx5_ifc_nop_out_bits { 6144 u8 status[0x8]; 6145 u8 reserved_0[0x18]; 6146 6147 u8 syndrome[0x20]; 6148 6149 u8 reserved_1[0x40]; 6150 }; 6151 6152 struct mlx5_ifc_nop_in_bits { 6153 u8 opcode[0x10]; 6154 u8 reserved_0[0x10]; 6155 6156 u8 reserved_1[0x10]; 6157 u8 op_mod[0x10]; 6158 6159 u8 reserved_2[0x40]; 6160 }; 6161 6162 struct mlx5_ifc_modify_vport_state_out_bits { 6163 u8 status[0x8]; 6164 u8 reserved_0[0x18]; 6165 6166 u8 syndrome[0x20]; 6167 6168 u8 reserved_1[0x40]; 6169 }; 6170 6171 enum { 6172 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_NIC_VPORT = 0x0, 6173 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, 6174 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_UPLINK = 0x2, 6175 }; 6176 6177 enum { 6178 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_DOWN = 0x0, 6179 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_UP = 0x1, 6180 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_FOLLOW = 0x2, 6181 }; 6182 6183 struct mlx5_ifc_modify_vport_state_in_bits { 6184 u8 opcode[0x10]; 6185 u8 reserved_0[0x10]; 6186 6187 u8 reserved_1[0x10]; 6188 u8 op_mod[0x10]; 6189 6190 u8 other_vport[0x1]; 6191 u8 reserved_2[0xf]; 6192 u8 vport_number[0x10]; 6193 6194 u8 reserved_3[0x18]; 6195 u8 admin_state[0x4]; 6196 u8 reserved_4[0x4]; 6197 }; 6198 6199 struct mlx5_ifc_modify_tis_out_bits { 6200 u8 status[0x8]; 6201 u8 reserved_0[0x18]; 6202 6203 u8 syndrome[0x20]; 6204 6205 u8 reserved_1[0x40]; 6206 }; 6207 6208 struct mlx5_ifc_modify_tis_bitmask_bits { 6209 u8 reserved_at_0[0x20]; 6210 6211 u8 reserved_at_20[0x1d]; 6212 u8 lag_tx_port_affinity[0x1]; 6213 u8 strict_lag_tx_port_affinity[0x1]; 6214 u8 prio[0x1]; 6215 }; 6216 6217 struct mlx5_ifc_modify_tis_in_bits { 6218 u8 opcode[0x10]; 6219 u8 uid[0x10]; 6220 6221 u8 reserved_1[0x10]; 6222 u8 op_mod[0x10]; 6223 6224 u8 reserved_2[0x8]; 6225 u8 tisn[0x18]; 6226 6227 u8 reserved_3[0x20]; 6228 6229 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 6230 6231 u8 reserved_4[0x40]; 6232 6233 struct mlx5_ifc_tisc_bits ctx; 6234 }; 6235 6236 struct mlx5_ifc_modify_tir_out_bits { 6237 u8 status[0x8]; 6238 u8 reserved_0[0x18]; 6239 6240 u8 syndrome[0x20]; 6241 6242 u8 reserved_1[0x40]; 6243 }; 6244 6245 enum 6246 { 6247 MLX5_MODIFY_SQ_BITMASK_PACKET_PACING_RATE_LIMIT_INDEX = 0x1 << 0, 6248 MLX5_MODIFY_SQ_BITMASK_QOS_PARA_VPORT_NUMBER = 0x1 << 1 6249 }; 6250 6251 struct mlx5_ifc_modify_tir_in_bits { 6252 u8 opcode[0x10]; 6253 u8 uid[0x10]; 6254 6255 u8 reserved_1[0x10]; 6256 u8 op_mod[0x10]; 6257 6258 u8 reserved_2[0x8]; 6259 u8 tirn[0x18]; 6260 6261 u8 reserved_3[0x20]; 6262 6263 u8 modify_bitmask[0x40]; 6264 6265 u8 reserved_4[0x40]; 6266 6267 struct mlx5_ifc_tirc_bits tir_context; 6268 }; 6269 6270 struct mlx5_ifc_modify_sq_out_bits { 6271 u8 status[0x8]; 6272 u8 reserved_0[0x18]; 6273 6274 u8 syndrome[0x20]; 6275 6276 u8 reserved_1[0x40]; 6277 }; 6278 6279 struct mlx5_ifc_modify_sq_in_bits { 6280 u8 opcode[0x10]; 6281 u8 uid[0x10]; 6282 6283 u8 reserved_1[0x10]; 6284 u8 op_mod[0x10]; 6285 6286 u8 sq_state[0x4]; 6287 u8 reserved_2[0x4]; 6288 u8 sqn[0x18]; 6289 6290 u8 reserved_3[0x20]; 6291 6292 u8 modify_bitmask[0x40]; 6293 6294 u8 reserved_4[0x40]; 6295 6296 struct mlx5_ifc_sqc_bits ctx; 6297 }; 6298 6299 struct mlx5_ifc_modify_scheduling_element_out_bits { 6300 u8 status[0x8]; 6301 u8 reserved_at_8[0x18]; 6302 6303 u8 syndrome[0x20]; 6304 6305 u8 reserved_at_40[0x1c0]; 6306 }; 6307 6308 enum { 6309 MLX5_MODIFY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 6310 }; 6311 6312 enum { 6313 MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_BW_SHARE = 0x1, 6314 MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_MAX_AVERAGE_BW = 0x2, 6315 }; 6316 6317 struct mlx5_ifc_modify_scheduling_element_in_bits { 6318 u8 opcode[0x10]; 6319 u8 reserved_at_10[0x10]; 6320 6321 u8 reserved_at_20[0x10]; 6322 u8 op_mod[0x10]; 6323 6324 u8 scheduling_hierarchy[0x8]; 6325 u8 reserved_at_48[0x18]; 6326 6327 u8 scheduling_element_id[0x20]; 6328 6329 u8 reserved_at_80[0x20]; 6330 6331 u8 modify_bitmask[0x20]; 6332 6333 u8 reserved_at_c0[0x40]; 6334 6335 struct mlx5_ifc_scheduling_context_bits scheduling_context; 6336 6337 u8 reserved_at_300[0x100]; 6338 }; 6339 6340 struct mlx5_ifc_modify_rqt_out_bits { 6341 u8 status[0x8]; 6342 u8 reserved_0[0x18]; 6343 6344 u8 syndrome[0x20]; 6345 6346 u8 reserved_1[0x40]; 6347 }; 6348 6349 struct mlx5_ifc_rqt_bitmask_bits { 6350 u8 reserved_at_0[0x20]; 6351 6352 u8 reserved_at_20[0x1f]; 6353 u8 rqn_list[0x1]; 6354 }; 6355 6356 6357 struct mlx5_ifc_modify_rqt_in_bits { 6358 u8 opcode[0x10]; 6359 u8 uid[0x10]; 6360 6361 u8 reserved_1[0x10]; 6362 u8 op_mod[0x10]; 6363 6364 u8 reserved_2[0x8]; 6365 u8 rqtn[0x18]; 6366 6367 u8 reserved_3[0x20]; 6368 6369 struct mlx5_ifc_rqt_bitmask_bits bitmask; 6370 6371 u8 reserved_4[0x40]; 6372 6373 struct mlx5_ifc_rqtc_bits ctx; 6374 }; 6375 6376 struct mlx5_ifc_modify_rq_out_bits { 6377 u8 status[0x8]; 6378 u8 reserved_0[0x18]; 6379 6380 u8 syndrome[0x20]; 6381 6382 u8 reserved_1[0x40]; 6383 }; 6384 6385 enum { 6386 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 6387 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3, 6388 }; 6389 6390 struct mlx5_ifc_modify_rq_in_bits { 6391 u8 opcode[0x10]; 6392 u8 uid[0x10]; 6393 6394 u8 reserved_1[0x10]; 6395 u8 op_mod[0x10]; 6396 6397 u8 rq_state[0x4]; 6398 u8 reserved_2[0x4]; 6399 u8 rqn[0x18]; 6400 6401 u8 reserved_3[0x20]; 6402 6403 u8 modify_bitmask[0x40]; 6404 6405 u8 reserved_4[0x40]; 6406 6407 struct mlx5_ifc_rqc_bits ctx; 6408 }; 6409 6410 struct mlx5_ifc_modify_rmp_out_bits { 6411 u8 status[0x8]; 6412 u8 reserved_0[0x18]; 6413 6414 u8 syndrome[0x20]; 6415 6416 u8 reserved_1[0x40]; 6417 }; 6418 6419 struct mlx5_ifc_rmp_bitmask_bits { 6420 u8 reserved[0x20]; 6421 6422 u8 reserved1[0x1f]; 6423 u8 lwm[0x1]; 6424 }; 6425 6426 struct mlx5_ifc_modify_rmp_in_bits { 6427 u8 opcode[0x10]; 6428 u8 uid[0x10]; 6429 6430 u8 reserved_1[0x10]; 6431 u8 op_mod[0x10]; 6432 6433 u8 rmp_state[0x4]; 6434 u8 reserved_2[0x4]; 6435 u8 rmpn[0x18]; 6436 6437 u8 reserved_3[0x20]; 6438 6439 struct mlx5_ifc_rmp_bitmask_bits bitmask; 6440 6441 u8 reserved_4[0x40]; 6442 6443 struct mlx5_ifc_rmpc_bits ctx; 6444 }; 6445 6446 struct mlx5_ifc_modify_nic_vport_context_out_bits { 6447 u8 status[0x8]; 6448 u8 reserved_0[0x18]; 6449 6450 u8 syndrome[0x20]; 6451 6452 u8 reserved_1[0x40]; 6453 }; 6454 6455 struct mlx5_ifc_modify_nic_vport_field_select_bits { 6456 u8 reserved_0[0x14]; 6457 u8 disable_uc_local_lb[0x1]; 6458 u8 disable_mc_local_lb[0x1]; 6459 u8 node_guid[0x1]; 6460 u8 port_guid[0x1]; 6461 u8 min_wqe_inline_mode[0x1]; 6462 u8 mtu[0x1]; 6463 u8 change_event[0x1]; 6464 u8 promisc[0x1]; 6465 u8 permanent_address[0x1]; 6466 u8 addresses_list[0x1]; 6467 u8 roce_en[0x1]; 6468 u8 reserved_1[0x1]; 6469 }; 6470 6471 struct mlx5_ifc_modify_nic_vport_context_in_bits { 6472 u8 opcode[0x10]; 6473 u8 reserved_0[0x10]; 6474 6475 u8 reserved_1[0x10]; 6476 u8 op_mod[0x10]; 6477 6478 u8 other_vport[0x1]; 6479 u8 reserved_2[0xf]; 6480 u8 vport_number[0x10]; 6481 6482 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 6483 6484 u8 reserved_3[0x780]; 6485 6486 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 6487 }; 6488 6489 struct mlx5_ifc_modify_hca_vport_context_out_bits { 6490 u8 status[0x8]; 6491 u8 reserved_0[0x18]; 6492 6493 u8 syndrome[0x20]; 6494 6495 u8 reserved_1[0x40]; 6496 }; 6497 6498 struct mlx5_ifc_grh_bits { 6499 u8 ip_version[4]; 6500 u8 traffic_class[8]; 6501 u8 flow_label[20]; 6502 u8 payload_length[16]; 6503 u8 next_header[8]; 6504 u8 hop_limit[8]; 6505 u8 sgid[128]; 6506 u8 dgid[128]; 6507 }; 6508 6509 struct mlx5_ifc_bth_bits { 6510 u8 opcode[8]; 6511 u8 se[1]; 6512 u8 migreq[1]; 6513 u8 pad_count[2]; 6514 u8 tver[4]; 6515 u8 p_key[16]; 6516 u8 reserved8[8]; 6517 u8 dest_qp[24]; 6518 u8 ack_req[1]; 6519 u8 reserved7[7]; 6520 u8 psn[24]; 6521 }; 6522 6523 struct mlx5_ifc_aeth_bits { 6524 u8 syndrome[8]; 6525 u8 msn[24]; 6526 }; 6527 6528 struct mlx5_ifc_dceth_bits { 6529 u8 reserved0[8]; 6530 u8 session_id[24]; 6531 u8 reserved1[8]; 6532 u8 dci_dct[24]; 6533 }; 6534 6535 struct mlx5_ifc_modify_hca_vport_context_in_bits { 6536 u8 opcode[0x10]; 6537 u8 reserved_0[0x10]; 6538 6539 u8 reserved_1[0x10]; 6540 u8 op_mod[0x10]; 6541 6542 u8 other_vport[0x1]; 6543 u8 reserved_2[0xb]; 6544 u8 port_num[0x4]; 6545 u8 vport_number[0x10]; 6546 6547 u8 reserved_3[0x20]; 6548 6549 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 6550 }; 6551 6552 enum { 6553 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 6554 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 6555 }; 6556 6557 struct mlx5_ifc_modify_flow_table_out_bits { 6558 u8 status[0x8]; 6559 u8 reserved_at_8[0x18]; 6560 6561 u8 syndrome[0x20]; 6562 6563 u8 reserved_at_40[0x40]; 6564 }; 6565 6566 enum { 6567 MLX5_MODIFY_FLOW_TABLE_SELECT_MISS_ACTION_AND_ID = 0x1, 6568 MLX5_MODIFY_FLOW_TABLE_SELECT_LAG_MASTER_NEXT_TABLE_ID = 0x8000, 6569 }; 6570 6571 struct mlx5_ifc_modify_flow_table_in_bits { 6572 u8 opcode[0x10]; 6573 u8 reserved_at_10[0x10]; 6574 6575 u8 reserved_at_20[0x10]; 6576 u8 op_mod[0x10]; 6577 6578 u8 other_vport[0x1]; 6579 u8 reserved_at_41[0xf]; 6580 u8 vport_number[0x10]; 6581 6582 u8 reserved_at_60[0x10]; 6583 u8 modify_field_select[0x10]; 6584 6585 u8 table_type[0x8]; 6586 u8 reserved_at_88[0x18]; 6587 6588 u8 reserved_at_a0[0x8]; 6589 u8 table_id[0x18]; 6590 6591 struct mlx5_ifc_flow_table_context_bits flow_table_context; 6592 }; 6593 6594 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6595 u8 status[0x8]; 6596 u8 reserved_0[0x18]; 6597 6598 u8 syndrome[0x20]; 6599 6600 u8 reserved_1[0x40]; 6601 }; 6602 6603 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6604 u8 reserved[0x1c]; 6605 u8 vport_cvlan_insert[0x1]; 6606 u8 vport_svlan_insert[0x1]; 6607 u8 vport_cvlan_strip[0x1]; 6608 u8 vport_svlan_strip[0x1]; 6609 }; 6610 6611 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6612 u8 opcode[0x10]; 6613 u8 reserved_0[0x10]; 6614 6615 u8 reserved_1[0x10]; 6616 u8 op_mod[0x10]; 6617 6618 u8 other_vport[0x1]; 6619 u8 reserved_2[0xf]; 6620 u8 vport_number[0x10]; 6621 6622 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6623 6624 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6625 }; 6626 6627 struct mlx5_ifc_modify_cq_out_bits { 6628 u8 status[0x8]; 6629 u8 reserved_0[0x18]; 6630 6631 u8 syndrome[0x20]; 6632 6633 u8 reserved_1[0x40]; 6634 }; 6635 6636 enum { 6637 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 6638 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 6639 }; 6640 6641 struct mlx5_ifc_modify_cq_in_bits { 6642 u8 opcode[0x10]; 6643 u8 uid[0x10]; 6644 6645 u8 reserved_1[0x10]; 6646 u8 op_mod[0x10]; 6647 6648 u8 reserved_2[0x8]; 6649 u8 cqn[0x18]; 6650 6651 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 6652 6653 struct mlx5_ifc_cqc_bits cq_context; 6654 6655 u8 reserved_at_280[0x60]; 6656 6657 u8 cq_umem_valid[0x1]; 6658 u8 reserved_at_2e1[0x1f]; 6659 6660 u8 reserved_at_300[0x580]; 6661 6662 u8 pas[0][0x40]; 6663 }; 6664 6665 struct mlx5_ifc_modify_cong_status_out_bits { 6666 u8 status[0x8]; 6667 u8 reserved_0[0x18]; 6668 6669 u8 syndrome[0x20]; 6670 6671 u8 reserved_1[0x40]; 6672 }; 6673 6674 struct mlx5_ifc_modify_cong_status_in_bits { 6675 u8 opcode[0x10]; 6676 u8 reserved_0[0x10]; 6677 6678 u8 reserved_1[0x10]; 6679 u8 op_mod[0x10]; 6680 6681 u8 reserved_2[0x18]; 6682 u8 priority[0x4]; 6683 u8 cong_protocol[0x4]; 6684 6685 u8 enable[0x1]; 6686 u8 tag_enable[0x1]; 6687 u8 reserved_3[0x1e]; 6688 }; 6689 6690 struct mlx5_ifc_modify_cong_params_out_bits { 6691 u8 status[0x8]; 6692 u8 reserved_0[0x18]; 6693 6694 u8 syndrome[0x20]; 6695 6696 u8 reserved_1[0x40]; 6697 }; 6698 6699 struct mlx5_ifc_modify_cong_params_in_bits { 6700 u8 opcode[0x10]; 6701 u8 reserved_0[0x10]; 6702 6703 u8 reserved_1[0x10]; 6704 u8 op_mod[0x10]; 6705 6706 u8 reserved_2[0x1c]; 6707 u8 cong_protocol[0x4]; 6708 6709 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 6710 6711 u8 reserved_3[0x80]; 6712 6713 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6714 }; 6715 6716 struct mlx5_ifc_manage_pages_out_bits { 6717 u8 status[0x8]; 6718 u8 reserved_0[0x18]; 6719 6720 u8 syndrome[0x20]; 6721 6722 u8 output_num_entries[0x20]; 6723 6724 u8 reserved_1[0x20]; 6725 6726 u8 pas[0][0x40]; 6727 }; 6728 6729 enum { 6730 MLX5_PAGES_CANT_GIVE = 0x0, 6731 MLX5_PAGES_GIVE = 0x1, 6732 MLX5_PAGES_TAKE = 0x2, 6733 }; 6734 6735 struct mlx5_ifc_manage_pages_in_bits { 6736 u8 opcode[0x10]; 6737 u8 reserved_0[0x10]; 6738 6739 u8 reserved_1[0x10]; 6740 u8 op_mod[0x10]; 6741 6742 u8 reserved_2[0x10]; 6743 u8 function_id[0x10]; 6744 6745 u8 input_num_entries[0x20]; 6746 6747 u8 pas[0][0x40]; 6748 }; 6749 6750 struct mlx5_ifc_mad_ifc_out_bits { 6751 u8 status[0x8]; 6752 u8 reserved_0[0x18]; 6753 6754 u8 syndrome[0x20]; 6755 6756 u8 reserved_1[0x40]; 6757 6758 u8 response_mad_packet[256][0x8]; 6759 }; 6760 6761 struct mlx5_ifc_mad_ifc_in_bits { 6762 u8 opcode[0x10]; 6763 u8 reserved_0[0x10]; 6764 6765 u8 reserved_1[0x10]; 6766 u8 op_mod[0x10]; 6767 6768 u8 remote_lid[0x10]; 6769 u8 reserved_2[0x8]; 6770 u8 port[0x8]; 6771 6772 u8 reserved_3[0x20]; 6773 6774 u8 mad[256][0x8]; 6775 }; 6776 6777 struct mlx5_ifc_init_hca_out_bits { 6778 u8 status[0x8]; 6779 u8 reserved_0[0x18]; 6780 6781 u8 syndrome[0x20]; 6782 6783 u8 reserved_1[0x40]; 6784 }; 6785 6786 enum { 6787 MLX5_INIT_HCA_IN_OP_MOD_INIT = 0x0, 6788 MLX5_INIT_HCA_IN_OP_MOD_PRE_INIT = 0x1, 6789 }; 6790 6791 struct mlx5_ifc_init_hca_in_bits { 6792 u8 opcode[0x10]; 6793 u8 reserved_0[0x10]; 6794 6795 u8 reserved_1[0x10]; 6796 u8 op_mod[0x10]; 6797 6798 u8 reserved_2[0x40]; 6799 }; 6800 6801 struct mlx5_ifc_init2rtr_qp_out_bits { 6802 u8 status[0x8]; 6803 u8 reserved_0[0x18]; 6804 6805 u8 syndrome[0x20]; 6806 6807 u8 reserved_1[0x40]; 6808 }; 6809 6810 struct mlx5_ifc_init2rtr_qp_in_bits { 6811 u8 opcode[0x10]; 6812 u8 uid[0x10]; 6813 6814 u8 reserved_1[0x10]; 6815 u8 op_mod[0x10]; 6816 6817 u8 reserved_2[0x8]; 6818 u8 qpn[0x18]; 6819 6820 u8 reserved_3[0x20]; 6821 6822 u8 opt_param_mask[0x20]; 6823 6824 u8 reserved_4[0x20]; 6825 6826 struct mlx5_ifc_qpc_bits qpc; 6827 6828 u8 reserved_5[0x80]; 6829 }; 6830 6831 struct mlx5_ifc_init2init_qp_out_bits { 6832 u8 status[0x8]; 6833 u8 reserved_0[0x18]; 6834 6835 u8 syndrome[0x20]; 6836 6837 u8 reserved_1[0x40]; 6838 }; 6839 6840 struct mlx5_ifc_init2init_qp_in_bits { 6841 u8 opcode[0x10]; 6842 u8 uid[0x10]; 6843 6844 u8 reserved_1[0x10]; 6845 u8 op_mod[0x10]; 6846 6847 u8 reserved_2[0x8]; 6848 u8 qpn[0x18]; 6849 6850 u8 reserved_3[0x20]; 6851 6852 u8 opt_param_mask[0x20]; 6853 6854 u8 reserved_4[0x20]; 6855 6856 struct mlx5_ifc_qpc_bits qpc; 6857 6858 u8 reserved_5[0x80]; 6859 }; 6860 6861 struct mlx5_ifc_get_dropped_packet_log_out_bits { 6862 u8 status[0x8]; 6863 u8 reserved_0[0x18]; 6864 6865 u8 syndrome[0x20]; 6866 6867 u8 reserved_1[0x40]; 6868 6869 u8 packet_headers_log[128][0x8]; 6870 6871 u8 packet_syndrome[64][0x8]; 6872 }; 6873 6874 struct mlx5_ifc_get_dropped_packet_log_in_bits { 6875 u8 opcode[0x10]; 6876 u8 reserved_0[0x10]; 6877 6878 u8 reserved_1[0x10]; 6879 u8 op_mod[0x10]; 6880 6881 u8 reserved_2[0x40]; 6882 }; 6883 6884 struct mlx5_ifc_encryption_key_obj_bits { 6885 u8 modify_field_select[0x40]; 6886 6887 u8 reserved_at_40[0x14]; 6888 u8 key_size[0x4]; 6889 u8 reserved_at_58[0x4]; 6890 u8 key_type[0x4]; 6891 6892 u8 reserved_at_60[0x8]; 6893 u8 pd[0x18]; 6894 6895 u8 reserved_at_80[0x180]; 6896 6897 u8 key[8][0x20]; 6898 6899 u8 reserved_at_300[0x500]; 6900 }; 6901 6902 struct mlx5_ifc_gen_eqe_in_bits { 6903 u8 opcode[0x10]; 6904 u8 reserved_0[0x10]; 6905 6906 u8 reserved_1[0x10]; 6907 u8 op_mod[0x10]; 6908 6909 u8 reserved_2[0x18]; 6910 u8 eq_number[0x8]; 6911 6912 u8 reserved_3[0x20]; 6913 6914 u8 eqe[64][0x8]; 6915 }; 6916 6917 struct mlx5_ifc_gen_eq_out_bits { 6918 u8 status[0x8]; 6919 u8 reserved_0[0x18]; 6920 6921 u8 syndrome[0x20]; 6922 6923 u8 reserved_1[0x40]; 6924 }; 6925 6926 struct mlx5_ifc_enable_hca_out_bits { 6927 u8 status[0x8]; 6928 u8 reserved_0[0x18]; 6929 6930 u8 syndrome[0x20]; 6931 6932 u8 reserved_1[0x20]; 6933 }; 6934 6935 struct mlx5_ifc_enable_hca_in_bits { 6936 u8 opcode[0x10]; 6937 u8 reserved_0[0x10]; 6938 6939 u8 reserved_1[0x10]; 6940 u8 op_mod[0x10]; 6941 6942 u8 reserved_2[0x10]; 6943 u8 function_id[0x10]; 6944 6945 u8 reserved_3[0x20]; 6946 }; 6947 6948 struct mlx5_ifc_drain_dct_out_bits { 6949 u8 status[0x8]; 6950 u8 reserved_0[0x18]; 6951 6952 u8 syndrome[0x20]; 6953 6954 u8 reserved_1[0x40]; 6955 }; 6956 6957 struct mlx5_ifc_drain_dct_in_bits { 6958 u8 opcode[0x10]; 6959 u8 uid[0x10]; 6960 6961 u8 reserved_1[0x10]; 6962 u8 op_mod[0x10]; 6963 6964 u8 reserved_2[0x8]; 6965 u8 dctn[0x18]; 6966 6967 u8 reserved_3[0x20]; 6968 }; 6969 6970 struct mlx5_ifc_disable_hca_out_bits { 6971 u8 status[0x8]; 6972 u8 reserved_0[0x18]; 6973 6974 u8 syndrome[0x20]; 6975 6976 u8 reserved_1[0x20]; 6977 }; 6978 6979 struct mlx5_ifc_disable_hca_in_bits { 6980 u8 opcode[0x10]; 6981 u8 reserved_0[0x10]; 6982 6983 u8 reserved_1[0x10]; 6984 u8 op_mod[0x10]; 6985 6986 u8 reserved_2[0x10]; 6987 u8 function_id[0x10]; 6988 6989 u8 reserved_3[0x20]; 6990 }; 6991 6992 struct mlx5_ifc_detach_from_mcg_out_bits { 6993 u8 status[0x8]; 6994 u8 reserved_0[0x18]; 6995 6996 u8 syndrome[0x20]; 6997 6998 u8 reserved_1[0x40]; 6999 }; 7000 7001 struct mlx5_ifc_detach_from_mcg_in_bits { 7002 u8 opcode[0x10]; 7003 u8 uid[0x10]; 7004 7005 u8 reserved_1[0x10]; 7006 u8 op_mod[0x10]; 7007 7008 u8 reserved_2[0x8]; 7009 u8 qpn[0x18]; 7010 7011 u8 reserved_3[0x20]; 7012 7013 u8 multicast_gid[16][0x8]; 7014 }; 7015 7016 struct mlx5_ifc_destroy_xrc_srq_out_bits { 7017 u8 status[0x8]; 7018 u8 reserved_0[0x18]; 7019 7020 u8 syndrome[0x20]; 7021 7022 u8 reserved_1[0x40]; 7023 }; 7024 7025 struct mlx5_ifc_destroy_xrc_srq_in_bits { 7026 u8 opcode[0x10]; 7027 u8 uid[0x10]; 7028 7029 u8 reserved_1[0x10]; 7030 u8 op_mod[0x10]; 7031 7032 u8 reserved_2[0x8]; 7033 u8 xrc_srqn[0x18]; 7034 7035 u8 reserved_3[0x20]; 7036 }; 7037 7038 struct mlx5_ifc_destroy_tis_out_bits { 7039 u8 status[0x8]; 7040 u8 reserved_0[0x18]; 7041 7042 u8 syndrome[0x20]; 7043 7044 u8 reserved_1[0x40]; 7045 }; 7046 7047 struct mlx5_ifc_destroy_tis_in_bits { 7048 u8 opcode[0x10]; 7049 u8 uid[0x10]; 7050 7051 u8 reserved_1[0x10]; 7052 u8 op_mod[0x10]; 7053 7054 u8 reserved_2[0x8]; 7055 u8 tisn[0x18]; 7056 7057 u8 reserved_3[0x20]; 7058 }; 7059 7060 struct mlx5_ifc_destroy_tir_out_bits { 7061 u8 status[0x8]; 7062 u8 reserved_0[0x18]; 7063 7064 u8 syndrome[0x20]; 7065 7066 u8 reserved_1[0x40]; 7067 }; 7068 7069 struct mlx5_ifc_destroy_tir_in_bits { 7070 u8 opcode[0x10]; 7071 u8 uid[0x10]; 7072 7073 u8 reserved_1[0x10]; 7074 u8 op_mod[0x10]; 7075 7076 u8 reserved_2[0x8]; 7077 u8 tirn[0x18]; 7078 7079 u8 reserved_3[0x20]; 7080 }; 7081 7082 struct mlx5_ifc_destroy_srq_out_bits { 7083 u8 status[0x8]; 7084 u8 reserved_0[0x18]; 7085 7086 u8 syndrome[0x20]; 7087 7088 u8 reserved_1[0x40]; 7089 }; 7090 7091 struct mlx5_ifc_destroy_srq_in_bits { 7092 u8 opcode[0x10]; 7093 u8 uid[0x10]; 7094 7095 u8 reserved_1[0x10]; 7096 u8 op_mod[0x10]; 7097 7098 u8 reserved_2[0x8]; 7099 u8 srqn[0x18]; 7100 7101 u8 reserved_3[0x20]; 7102 }; 7103 7104 struct mlx5_ifc_destroy_sq_out_bits { 7105 u8 status[0x8]; 7106 u8 reserved_0[0x18]; 7107 7108 u8 syndrome[0x20]; 7109 7110 u8 reserved_1[0x40]; 7111 }; 7112 7113 struct mlx5_ifc_destroy_sq_in_bits { 7114 u8 opcode[0x10]; 7115 u8 uid[0x10]; 7116 7117 u8 reserved_1[0x10]; 7118 u8 op_mod[0x10]; 7119 7120 u8 reserved_2[0x8]; 7121 u8 sqn[0x18]; 7122 7123 u8 reserved_3[0x20]; 7124 }; 7125 7126 struct mlx5_ifc_destroy_scheduling_element_out_bits { 7127 u8 status[0x8]; 7128 u8 reserved_at_8[0x18]; 7129 7130 u8 syndrome[0x20]; 7131 7132 u8 reserved_at_40[0x1c0]; 7133 }; 7134 7135 enum { 7136 MLX5_DESTROY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 7137 }; 7138 7139 struct mlx5_ifc_destroy_scheduling_element_in_bits { 7140 u8 opcode[0x10]; 7141 u8 reserved_at_10[0x10]; 7142 7143 u8 reserved_at_20[0x10]; 7144 u8 op_mod[0x10]; 7145 7146 u8 scheduling_hierarchy[0x8]; 7147 u8 reserved_at_48[0x18]; 7148 7149 u8 scheduling_element_id[0x20]; 7150 7151 u8 reserved_at_80[0x180]; 7152 }; 7153 7154 struct mlx5_ifc_destroy_rqt_out_bits { 7155 u8 status[0x8]; 7156 u8 reserved_0[0x18]; 7157 7158 u8 syndrome[0x20]; 7159 7160 u8 reserved_1[0x40]; 7161 }; 7162 7163 struct mlx5_ifc_destroy_rqt_in_bits { 7164 u8 opcode[0x10]; 7165 u8 uid[0x10]; 7166 7167 u8 reserved_1[0x10]; 7168 u8 op_mod[0x10]; 7169 7170 u8 reserved_2[0x8]; 7171 u8 rqtn[0x18]; 7172 7173 u8 reserved_3[0x20]; 7174 }; 7175 7176 struct mlx5_ifc_destroy_rq_out_bits { 7177 u8 status[0x8]; 7178 u8 reserved_0[0x18]; 7179 7180 u8 syndrome[0x20]; 7181 7182 u8 reserved_1[0x40]; 7183 }; 7184 7185 struct mlx5_ifc_destroy_rq_in_bits { 7186 u8 opcode[0x10]; 7187 u8 uid[0x10]; 7188 7189 u8 reserved_1[0x10]; 7190 u8 op_mod[0x10]; 7191 7192 u8 reserved_2[0x8]; 7193 u8 rqn[0x18]; 7194 7195 u8 reserved_3[0x20]; 7196 }; 7197 7198 struct mlx5_ifc_destroy_rmp_out_bits { 7199 u8 status[0x8]; 7200 u8 reserved_0[0x18]; 7201 7202 u8 syndrome[0x20]; 7203 7204 u8 reserved_1[0x40]; 7205 }; 7206 7207 struct mlx5_ifc_destroy_rmp_in_bits { 7208 u8 opcode[0x10]; 7209 u8 reserved_0[0x10]; 7210 7211 u8 reserved_1[0x10]; 7212 u8 op_mod[0x10]; 7213 7214 u8 reserved_2[0x8]; 7215 u8 rmpn[0x18]; 7216 7217 u8 reserved_3[0x20]; 7218 }; 7219 7220 struct mlx5_ifc_destroy_qp_out_bits { 7221 u8 status[0x8]; 7222 u8 reserved_0[0x18]; 7223 7224 u8 syndrome[0x20]; 7225 7226 u8 reserved_1[0x40]; 7227 }; 7228 7229 struct mlx5_ifc_destroy_qp_in_bits { 7230 u8 opcode[0x10]; 7231 u8 uid[0x10]; 7232 7233 u8 reserved_1[0x10]; 7234 u8 op_mod[0x10]; 7235 7236 u8 reserved_2[0x8]; 7237 u8 qpn[0x18]; 7238 7239 u8 reserved_3[0x20]; 7240 }; 7241 7242 struct mlx5_ifc_destroy_qos_para_vport_out_bits { 7243 u8 status[0x8]; 7244 u8 reserved_at_8[0x18]; 7245 7246 u8 syndrome[0x20]; 7247 7248 u8 reserved_at_40[0x1c0]; 7249 }; 7250 7251 struct mlx5_ifc_destroy_qos_para_vport_in_bits { 7252 u8 opcode[0x10]; 7253 u8 reserved_at_10[0x10]; 7254 7255 u8 reserved_at_20[0x10]; 7256 u8 op_mod[0x10]; 7257 7258 u8 reserved_at_40[0x20]; 7259 7260 u8 reserved_at_60[0x10]; 7261 u8 qos_para_vport_number[0x10]; 7262 7263 u8 reserved_at_80[0x180]; 7264 }; 7265 7266 struct mlx5_ifc_destroy_psv_out_bits { 7267 u8 status[0x8]; 7268 u8 reserved_0[0x18]; 7269 7270 u8 syndrome[0x20]; 7271 7272 u8 reserved_1[0x40]; 7273 }; 7274 7275 struct mlx5_ifc_destroy_psv_in_bits { 7276 u8 opcode[0x10]; 7277 u8 reserved_0[0x10]; 7278 7279 u8 reserved_1[0x10]; 7280 u8 op_mod[0x10]; 7281 7282 u8 reserved_2[0x8]; 7283 u8 psvn[0x18]; 7284 7285 u8 reserved_3[0x20]; 7286 }; 7287 7288 struct mlx5_ifc_destroy_mkey_out_bits { 7289 u8 status[0x8]; 7290 u8 reserved_0[0x18]; 7291 7292 u8 syndrome[0x20]; 7293 7294 u8 reserved_1[0x40]; 7295 }; 7296 7297 struct mlx5_ifc_destroy_mkey_in_bits { 7298 u8 opcode[0x10]; 7299 u8 reserved_0[0x10]; 7300 7301 u8 reserved_1[0x10]; 7302 u8 op_mod[0x10]; 7303 7304 u8 reserved_2[0x8]; 7305 u8 mkey_index[0x18]; 7306 7307 u8 reserved_3[0x20]; 7308 }; 7309 7310 struct mlx5_ifc_destroy_flow_table_out_bits { 7311 u8 status[0x8]; 7312 u8 reserved_0[0x18]; 7313 7314 u8 syndrome[0x20]; 7315 7316 u8 reserved_1[0x40]; 7317 }; 7318 7319 struct mlx5_ifc_destroy_flow_table_in_bits { 7320 u8 opcode[0x10]; 7321 u8 reserved_0[0x10]; 7322 7323 u8 reserved_1[0x10]; 7324 u8 op_mod[0x10]; 7325 7326 u8 other_vport[0x1]; 7327 u8 reserved_2[0xf]; 7328 u8 vport_number[0x10]; 7329 7330 u8 reserved_3[0x20]; 7331 7332 u8 table_type[0x8]; 7333 u8 reserved_4[0x18]; 7334 7335 u8 reserved_5[0x8]; 7336 u8 table_id[0x18]; 7337 7338 u8 reserved_6[0x140]; 7339 }; 7340 7341 struct mlx5_ifc_destroy_flow_group_out_bits { 7342 u8 status[0x8]; 7343 u8 reserved_0[0x18]; 7344 7345 u8 syndrome[0x20]; 7346 7347 u8 reserved_1[0x40]; 7348 }; 7349 7350 struct mlx5_ifc_destroy_flow_group_in_bits { 7351 u8 opcode[0x10]; 7352 u8 reserved_0[0x10]; 7353 7354 u8 reserved_1[0x10]; 7355 u8 op_mod[0x10]; 7356 7357 u8 other_vport[0x1]; 7358 u8 reserved_2[0xf]; 7359 u8 vport_number[0x10]; 7360 7361 u8 reserved_3[0x20]; 7362 7363 u8 table_type[0x8]; 7364 u8 reserved_4[0x18]; 7365 7366 u8 reserved_5[0x8]; 7367 u8 table_id[0x18]; 7368 7369 u8 group_id[0x20]; 7370 7371 u8 reserved_6[0x120]; 7372 }; 7373 7374 struct mlx5_ifc_destroy_encryption_key_out_bits { 7375 u8 status[0x8]; 7376 u8 reserved_at_8[0x18]; 7377 7378 u8 syndrome[0x20]; 7379 7380 u8 reserved_at_40[0x40]; 7381 }; 7382 7383 struct mlx5_ifc_destroy_encryption_key_in_bits { 7384 u8 opcode[0x10]; 7385 u8 reserved_at_10[0x10]; 7386 7387 u8 reserved_at_20[0x10]; 7388 u8 obj_type[0x10]; 7389 7390 u8 obj_id[0x20]; 7391 7392 u8 reserved_at_60[0x20]; 7393 }; 7394 7395 struct mlx5_ifc_destroy_eq_out_bits { 7396 u8 status[0x8]; 7397 u8 reserved_0[0x18]; 7398 7399 u8 syndrome[0x20]; 7400 7401 u8 reserved_1[0x40]; 7402 }; 7403 7404 struct mlx5_ifc_destroy_eq_in_bits { 7405 u8 opcode[0x10]; 7406 u8 reserved_0[0x10]; 7407 7408 u8 reserved_1[0x10]; 7409 u8 op_mod[0x10]; 7410 7411 u8 reserved_2[0x18]; 7412 u8 eq_number[0x8]; 7413 7414 u8 reserved_3[0x20]; 7415 }; 7416 7417 struct mlx5_ifc_destroy_dct_out_bits { 7418 u8 status[0x8]; 7419 u8 reserved_0[0x18]; 7420 7421 u8 syndrome[0x20]; 7422 7423 u8 reserved_1[0x40]; 7424 }; 7425 7426 struct mlx5_ifc_destroy_dct_in_bits { 7427 u8 opcode[0x10]; 7428 u8 uid[0x10]; 7429 7430 u8 reserved_1[0x10]; 7431 u8 op_mod[0x10]; 7432 7433 u8 reserved_2[0x8]; 7434 u8 dctn[0x18]; 7435 7436 u8 reserved_3[0x20]; 7437 }; 7438 7439 struct mlx5_ifc_destroy_cq_out_bits { 7440 u8 status[0x8]; 7441 u8 reserved_0[0x18]; 7442 7443 u8 syndrome[0x20]; 7444 7445 u8 reserved_1[0x40]; 7446 }; 7447 7448 struct mlx5_ifc_destroy_cq_in_bits { 7449 u8 opcode[0x10]; 7450 u8 uid[0x10]; 7451 7452 u8 reserved_1[0x10]; 7453 u8 op_mod[0x10]; 7454 7455 u8 reserved_2[0x8]; 7456 u8 cqn[0x18]; 7457 7458 u8 reserved_3[0x20]; 7459 }; 7460 7461 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 7462 u8 status[0x8]; 7463 u8 reserved_0[0x18]; 7464 7465 u8 syndrome[0x20]; 7466 7467 u8 reserved_1[0x40]; 7468 }; 7469 7470 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 7471 u8 opcode[0x10]; 7472 u8 reserved_0[0x10]; 7473 7474 u8 reserved_1[0x10]; 7475 u8 op_mod[0x10]; 7476 7477 u8 reserved_2[0x20]; 7478 7479 u8 reserved_3[0x10]; 7480 u8 vxlan_udp_port[0x10]; 7481 }; 7482 7483 struct mlx5_ifc_delete_l2_table_entry_out_bits { 7484 u8 status[0x8]; 7485 u8 reserved_0[0x18]; 7486 7487 u8 syndrome[0x20]; 7488 7489 u8 reserved_1[0x40]; 7490 }; 7491 7492 struct mlx5_ifc_delete_l2_table_entry_in_bits { 7493 u8 opcode[0x10]; 7494 u8 reserved_0[0x10]; 7495 7496 u8 reserved_1[0x10]; 7497 u8 op_mod[0x10]; 7498 7499 u8 reserved_2[0x60]; 7500 7501 u8 reserved_3[0x8]; 7502 u8 table_index[0x18]; 7503 7504 u8 reserved_4[0x140]; 7505 }; 7506 7507 struct mlx5_ifc_delete_fte_out_bits { 7508 u8 status[0x8]; 7509 u8 reserved_0[0x18]; 7510 7511 u8 syndrome[0x20]; 7512 7513 u8 reserved_1[0x40]; 7514 }; 7515 7516 struct mlx5_ifc_delete_fte_in_bits { 7517 u8 opcode[0x10]; 7518 u8 reserved_0[0x10]; 7519 7520 u8 reserved_1[0x10]; 7521 u8 op_mod[0x10]; 7522 7523 u8 other_vport[0x1]; 7524 u8 reserved_2[0xf]; 7525 u8 vport_number[0x10]; 7526 7527 u8 reserved_3[0x20]; 7528 7529 u8 table_type[0x8]; 7530 u8 reserved_4[0x18]; 7531 7532 u8 reserved_5[0x8]; 7533 u8 table_id[0x18]; 7534 7535 u8 reserved_6[0x40]; 7536 7537 u8 flow_index[0x20]; 7538 7539 u8 reserved_7[0xe0]; 7540 }; 7541 7542 struct mlx5_ifc_dealloc_xrcd_out_bits { 7543 u8 status[0x8]; 7544 u8 reserved_0[0x18]; 7545 7546 u8 syndrome[0x20]; 7547 7548 u8 reserved_1[0x40]; 7549 }; 7550 7551 struct mlx5_ifc_dealloc_xrcd_in_bits { 7552 u8 opcode[0x10]; 7553 u8 uid[0x10]; 7554 7555 u8 reserved_1[0x10]; 7556 u8 op_mod[0x10]; 7557 7558 u8 reserved_2[0x8]; 7559 u8 xrcd[0x18]; 7560 7561 u8 reserved_3[0x20]; 7562 }; 7563 7564 struct mlx5_ifc_dealloc_uar_out_bits { 7565 u8 status[0x8]; 7566 u8 reserved_0[0x18]; 7567 7568 u8 syndrome[0x20]; 7569 7570 u8 reserved_1[0x40]; 7571 }; 7572 7573 struct mlx5_ifc_dealloc_uar_in_bits { 7574 u8 opcode[0x10]; 7575 u8 reserved_0[0x10]; 7576 7577 u8 reserved_1[0x10]; 7578 u8 op_mod[0x10]; 7579 7580 u8 reserved_2[0x8]; 7581 u8 uar[0x18]; 7582 7583 u8 reserved_3[0x20]; 7584 }; 7585 7586 struct mlx5_ifc_dealloc_transport_domain_out_bits { 7587 u8 status[0x8]; 7588 u8 reserved_0[0x18]; 7589 7590 u8 syndrome[0x20]; 7591 7592 u8 reserved_1[0x40]; 7593 }; 7594 7595 struct mlx5_ifc_dealloc_transport_domain_in_bits { 7596 u8 opcode[0x10]; 7597 u8 uid[0x10]; 7598 7599 u8 reserved_1[0x10]; 7600 u8 op_mod[0x10]; 7601 7602 u8 reserved_2[0x8]; 7603 u8 transport_domain[0x18]; 7604 7605 u8 reserved_3[0x20]; 7606 }; 7607 7608 struct mlx5_ifc_dealloc_q_counter_out_bits { 7609 u8 status[0x8]; 7610 u8 reserved_0[0x18]; 7611 7612 u8 syndrome[0x20]; 7613 7614 u8 reserved_1[0x40]; 7615 }; 7616 7617 struct mlx5_ifc_counter_id_bits { 7618 u8 reserved[0x10]; 7619 u8 counter_id[0x10]; 7620 }; 7621 7622 struct mlx5_ifc_diagnostic_params_context_bits { 7623 u8 num_of_counters[0x10]; 7624 u8 reserved_2[0x8]; 7625 u8 log_num_of_samples[0x8]; 7626 7627 u8 single[0x1]; 7628 u8 repetitive[0x1]; 7629 u8 sync[0x1]; 7630 u8 clear[0x1]; 7631 u8 on_demand[0x1]; 7632 u8 enable[0x1]; 7633 u8 reserved_3[0x12]; 7634 u8 log_sample_period[0x8]; 7635 7636 u8 reserved_4[0x80]; 7637 7638 struct mlx5_ifc_counter_id_bits counter_id[0]; 7639 }; 7640 7641 struct mlx5_ifc_query_diagnostic_params_in_bits { 7642 u8 opcode[0x10]; 7643 u8 reserved_at_10[0x10]; 7644 7645 u8 reserved_at_20[0x10]; 7646 u8 op_mod[0x10]; 7647 7648 u8 reserved_at_40[0x40]; 7649 }; 7650 7651 struct mlx5_ifc_query_diagnostic_params_out_bits { 7652 u8 status[0x8]; 7653 u8 reserved_at_8[0x18]; 7654 7655 u8 syndrome[0x20]; 7656 7657 struct mlx5_ifc_diagnostic_params_context_bits diagnostic_params_ctx; 7658 }; 7659 7660 struct mlx5_ifc_set_diagnostic_params_in_bits { 7661 u8 opcode[0x10]; 7662 u8 reserved_0[0x10]; 7663 7664 u8 reserved_1[0x10]; 7665 u8 op_mod[0x10]; 7666 7667 struct mlx5_ifc_diagnostic_params_context_bits diagnostic_params_ctx; 7668 }; 7669 7670 struct mlx5_ifc_set_diagnostic_params_out_bits { 7671 u8 status[0x8]; 7672 u8 reserved_0[0x18]; 7673 7674 u8 syndrome[0x20]; 7675 7676 u8 reserved_1[0x40]; 7677 }; 7678 7679 struct mlx5_ifc_query_diagnostic_counters_in_bits { 7680 u8 opcode[0x10]; 7681 u8 reserved_0[0x10]; 7682 7683 u8 reserved_1[0x10]; 7684 u8 op_mod[0x10]; 7685 7686 u8 num_of_samples[0x10]; 7687 u8 sample_index[0x10]; 7688 7689 u8 reserved_2[0x20]; 7690 }; 7691 7692 struct mlx5_ifc_diagnostic_counter_bits { 7693 u8 counter_id[0x10]; 7694 u8 sample_id[0x10]; 7695 7696 u8 time_stamp_31_0[0x20]; 7697 7698 u8 counter_value_h[0x20]; 7699 7700 u8 counter_value_l[0x20]; 7701 }; 7702 7703 struct mlx5_ifc_query_diagnostic_counters_out_bits { 7704 u8 status[0x8]; 7705 u8 reserved_0[0x18]; 7706 7707 u8 syndrome[0x20]; 7708 7709 u8 reserved_1[0x40]; 7710 7711 struct mlx5_ifc_diagnostic_counter_bits diag_counter[0]; 7712 }; 7713 7714 struct mlx5_ifc_dealloc_q_counter_in_bits { 7715 u8 opcode[0x10]; 7716 u8 reserved_0[0x10]; 7717 7718 u8 reserved_1[0x10]; 7719 u8 op_mod[0x10]; 7720 7721 u8 reserved_2[0x18]; 7722 u8 counter_set_id[0x8]; 7723 7724 u8 reserved_3[0x20]; 7725 }; 7726 7727 struct mlx5_ifc_dealloc_pd_out_bits { 7728 u8 status[0x8]; 7729 u8 reserved_0[0x18]; 7730 7731 u8 syndrome[0x20]; 7732 7733 u8 reserved_1[0x40]; 7734 }; 7735 7736 struct mlx5_ifc_dealloc_pd_in_bits { 7737 u8 opcode[0x10]; 7738 u8 uid[0x10]; 7739 7740 u8 reserved_1[0x10]; 7741 u8 op_mod[0x10]; 7742 7743 u8 reserved_2[0x8]; 7744 u8 pd[0x18]; 7745 7746 u8 reserved_3[0x20]; 7747 }; 7748 7749 struct mlx5_ifc_dealloc_flow_counter_out_bits { 7750 u8 status[0x8]; 7751 u8 reserved_0[0x18]; 7752 7753 u8 syndrome[0x20]; 7754 7755 u8 reserved_1[0x40]; 7756 }; 7757 7758 struct mlx5_ifc_dealloc_flow_counter_in_bits { 7759 u8 opcode[0x10]; 7760 u8 reserved_0[0x10]; 7761 7762 u8 reserved_1[0x10]; 7763 u8 op_mod[0x10]; 7764 7765 u8 flow_counter_id[0x20]; 7766 7767 u8 reserved_3[0x20]; 7768 }; 7769 7770 struct mlx5_ifc_create_xrq_out_bits { 7771 u8 status[0x8]; 7772 u8 reserved_at_8[0x18]; 7773 7774 u8 syndrome[0x20]; 7775 7776 u8 reserved_at_40[0x8]; 7777 u8 xrqn[0x18]; 7778 7779 u8 reserved_at_60[0x20]; 7780 }; 7781 7782 struct mlx5_ifc_create_xrq_in_bits { 7783 u8 opcode[0x10]; 7784 u8 uid[0x10]; 7785 7786 u8 reserved_at_20[0x10]; 7787 u8 op_mod[0x10]; 7788 7789 u8 reserved_at_40[0x40]; 7790 7791 struct mlx5_ifc_xrqc_bits xrq_context; 7792 }; 7793 7794 struct mlx5_ifc_deactivate_tracer_out_bits { 7795 u8 status[0x8]; 7796 u8 reserved_0[0x18]; 7797 7798 u8 syndrome[0x20]; 7799 7800 u8 reserved_1[0x40]; 7801 }; 7802 7803 struct mlx5_ifc_deactivate_tracer_in_bits { 7804 u8 opcode[0x10]; 7805 u8 reserved_0[0x10]; 7806 7807 u8 reserved_1[0x10]; 7808 u8 op_mod[0x10]; 7809 7810 u8 mkey[0x20]; 7811 7812 u8 reserved_2[0x20]; 7813 }; 7814 7815 struct mlx5_ifc_create_xrc_srq_out_bits { 7816 u8 status[0x8]; 7817 u8 reserved_0[0x18]; 7818 7819 u8 syndrome[0x20]; 7820 7821 u8 reserved_1[0x8]; 7822 u8 xrc_srqn[0x18]; 7823 7824 u8 reserved_2[0x20]; 7825 }; 7826 7827 struct mlx5_ifc_create_xrc_srq_in_bits { 7828 u8 opcode[0x10]; 7829 u8 uid[0x10]; 7830 7831 u8 reserved_1[0x10]; 7832 u8 op_mod[0x10]; 7833 7834 u8 reserved_2[0x40]; 7835 7836 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 7837 7838 u8 reserved_at_280[0x60]; 7839 7840 u8 xrc_srq_umem_valid[0x1]; 7841 u8 reserved_at_2e1[0x1f]; 7842 7843 u8 reserved_at_300[0x580]; 7844 7845 u8 pas[0][0x40]; 7846 }; 7847 7848 struct mlx5_ifc_create_tis_out_bits { 7849 u8 status[0x8]; 7850 u8 reserved_0[0x18]; 7851 7852 u8 syndrome[0x20]; 7853 7854 u8 reserved_1[0x8]; 7855 u8 tisn[0x18]; 7856 7857 u8 reserved_2[0x20]; 7858 }; 7859 7860 struct mlx5_ifc_create_tis_in_bits { 7861 u8 opcode[0x10]; 7862 u8 uid[0x10]; 7863 7864 u8 reserved_1[0x10]; 7865 u8 op_mod[0x10]; 7866 7867 u8 reserved_2[0xc0]; 7868 7869 struct mlx5_ifc_tisc_bits ctx; 7870 }; 7871 7872 struct mlx5_ifc_create_tir_out_bits { 7873 u8 status[0x8]; 7874 u8 reserved_0[0x18]; 7875 7876 u8 syndrome[0x20]; 7877 7878 u8 reserved_1[0x8]; 7879 u8 tirn[0x18]; 7880 7881 u8 reserved_2[0x20]; 7882 }; 7883 7884 struct mlx5_ifc_create_tir_in_bits { 7885 u8 opcode[0x10]; 7886 u8 uid[0x10]; 7887 7888 u8 reserved_1[0x10]; 7889 u8 op_mod[0x10]; 7890 7891 u8 reserved_2[0xc0]; 7892 7893 struct mlx5_ifc_tirc_bits tir_context; 7894 }; 7895 7896 struct mlx5_ifc_create_srq_out_bits { 7897 u8 status[0x8]; 7898 u8 reserved_0[0x18]; 7899 7900 u8 syndrome[0x20]; 7901 7902 u8 reserved_1[0x8]; 7903 u8 srqn[0x18]; 7904 7905 u8 reserved_2[0x20]; 7906 }; 7907 7908 struct mlx5_ifc_create_srq_in_bits { 7909 u8 opcode[0x10]; 7910 u8 uid[0x10]; 7911 7912 u8 reserved_1[0x10]; 7913 u8 op_mod[0x10]; 7914 7915 u8 reserved_2[0x40]; 7916 7917 struct mlx5_ifc_srqc_bits srq_context_entry; 7918 7919 u8 reserved_3[0x600]; 7920 7921 u8 pas[0][0x40]; 7922 }; 7923 7924 struct mlx5_ifc_create_sq_out_bits { 7925 u8 status[0x8]; 7926 u8 reserved_0[0x18]; 7927 7928 u8 syndrome[0x20]; 7929 7930 u8 reserved_1[0x8]; 7931 u8 sqn[0x18]; 7932 7933 u8 reserved_2[0x20]; 7934 }; 7935 7936 struct mlx5_ifc_create_sq_in_bits { 7937 u8 opcode[0x10]; 7938 u8 uid[0x10]; 7939 7940 u8 reserved_1[0x10]; 7941 u8 op_mod[0x10]; 7942 7943 u8 reserved_2[0xc0]; 7944 7945 struct mlx5_ifc_sqc_bits ctx; 7946 }; 7947 7948 struct mlx5_ifc_create_scheduling_element_out_bits { 7949 u8 status[0x8]; 7950 u8 reserved_at_8[0x18]; 7951 7952 u8 syndrome[0x20]; 7953 7954 u8 reserved_at_40[0x40]; 7955 7956 u8 scheduling_element_id[0x20]; 7957 7958 u8 reserved_at_a0[0x160]; 7959 }; 7960 7961 enum { 7962 MLX5_CREATE_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 7963 }; 7964 7965 struct mlx5_ifc_create_scheduling_element_in_bits { 7966 u8 opcode[0x10]; 7967 u8 reserved_at_10[0x10]; 7968 7969 u8 reserved_at_20[0x10]; 7970 u8 op_mod[0x10]; 7971 7972 u8 scheduling_hierarchy[0x8]; 7973 u8 reserved_at_48[0x18]; 7974 7975 u8 reserved_at_60[0xa0]; 7976 7977 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7978 7979 u8 reserved_at_300[0x100]; 7980 }; 7981 7982 struct mlx5_ifc_create_rqt_out_bits { 7983 u8 status[0x8]; 7984 u8 reserved_0[0x18]; 7985 7986 u8 syndrome[0x20]; 7987 7988 u8 reserved_1[0x8]; 7989 u8 rqtn[0x18]; 7990 7991 u8 reserved_2[0x20]; 7992 }; 7993 7994 struct mlx5_ifc_create_rqt_in_bits { 7995 u8 opcode[0x10]; 7996 u8 uid[0x10]; 7997 7998 u8 reserved_1[0x10]; 7999 u8 op_mod[0x10]; 8000 8001 u8 reserved_2[0xc0]; 8002 8003 struct mlx5_ifc_rqtc_bits rqt_context; 8004 }; 8005 8006 struct mlx5_ifc_create_rq_out_bits { 8007 u8 status[0x8]; 8008 u8 reserved_0[0x18]; 8009 8010 u8 syndrome[0x20]; 8011 8012 u8 reserved_1[0x8]; 8013 u8 rqn[0x18]; 8014 8015 u8 reserved_2[0x20]; 8016 }; 8017 8018 struct mlx5_ifc_create_rq_in_bits { 8019 u8 opcode[0x10]; 8020 u8 uid[0x10]; 8021 8022 u8 reserved_1[0x10]; 8023 u8 op_mod[0x10]; 8024 8025 u8 reserved_2[0xc0]; 8026 8027 struct mlx5_ifc_rqc_bits ctx; 8028 }; 8029 8030 struct mlx5_ifc_create_rmp_out_bits { 8031 u8 status[0x8]; 8032 u8 reserved_0[0x18]; 8033 8034 u8 syndrome[0x20]; 8035 8036 u8 reserved_1[0x8]; 8037 u8 rmpn[0x18]; 8038 8039 u8 reserved_2[0x20]; 8040 }; 8041 8042 struct mlx5_ifc_create_rmp_in_bits { 8043 u8 opcode[0x10]; 8044 u8 uid[0x10]; 8045 8046 u8 reserved_1[0x10]; 8047 u8 op_mod[0x10]; 8048 8049 u8 reserved_2[0xc0]; 8050 8051 struct mlx5_ifc_rmpc_bits ctx; 8052 }; 8053 8054 struct mlx5_ifc_create_qp_out_bits { 8055 u8 status[0x8]; 8056 u8 reserved_0[0x18]; 8057 8058 u8 syndrome[0x20]; 8059 8060 u8 reserved_1[0x8]; 8061 u8 qpn[0x18]; 8062 8063 u8 reserved_2[0x20]; 8064 }; 8065 8066 struct mlx5_ifc_create_qp_in_bits { 8067 u8 opcode[0x10]; 8068 u8 uid[0x10]; 8069 8070 u8 reserved_1[0x10]; 8071 u8 op_mod[0x10]; 8072 8073 u8 reserved_2[0x8]; 8074 u8 input_qpn[0x18]; 8075 8076 u8 reserved_3[0x20]; 8077 8078 u8 opt_param_mask[0x20]; 8079 8080 u8 reserved_4[0x20]; 8081 8082 struct mlx5_ifc_qpc_bits qpc; 8083 8084 u8 reserved_at_800[0x60]; 8085 8086 u8 wq_umem_valid[0x1]; 8087 u8 reserved_at_861[0x1f]; 8088 8089 u8 pas[0][0x40]; 8090 }; 8091 8092 struct mlx5_ifc_create_qos_para_vport_out_bits { 8093 u8 status[0x8]; 8094 u8 reserved_at_8[0x18]; 8095 8096 u8 syndrome[0x20]; 8097 8098 u8 reserved_at_40[0x20]; 8099 8100 u8 reserved_at_60[0x10]; 8101 u8 qos_para_vport_number[0x10]; 8102 8103 u8 reserved_at_80[0x180]; 8104 }; 8105 8106 struct mlx5_ifc_create_qos_para_vport_in_bits { 8107 u8 opcode[0x10]; 8108 u8 reserved_at_10[0x10]; 8109 8110 u8 reserved_at_20[0x10]; 8111 u8 op_mod[0x10]; 8112 8113 u8 reserved_at_40[0x1c0]; 8114 }; 8115 8116 struct mlx5_ifc_create_psv_out_bits { 8117 u8 status[0x8]; 8118 u8 reserved_0[0x18]; 8119 8120 u8 syndrome[0x20]; 8121 8122 u8 reserved_1[0x40]; 8123 8124 u8 reserved_2[0x8]; 8125 u8 psv0_index[0x18]; 8126 8127 u8 reserved_3[0x8]; 8128 u8 psv1_index[0x18]; 8129 8130 u8 reserved_4[0x8]; 8131 u8 psv2_index[0x18]; 8132 8133 u8 reserved_5[0x8]; 8134 u8 psv3_index[0x18]; 8135 }; 8136 8137 struct mlx5_ifc_create_psv_in_bits { 8138 u8 opcode[0x10]; 8139 u8 reserved_0[0x10]; 8140 8141 u8 reserved_1[0x10]; 8142 u8 op_mod[0x10]; 8143 8144 u8 num_psv[0x4]; 8145 u8 reserved_2[0x4]; 8146 u8 pd[0x18]; 8147 8148 u8 reserved_3[0x20]; 8149 }; 8150 8151 struct mlx5_ifc_create_mkey_out_bits { 8152 u8 status[0x8]; 8153 u8 reserved_0[0x18]; 8154 8155 u8 syndrome[0x20]; 8156 8157 u8 reserved_1[0x8]; 8158 u8 mkey_index[0x18]; 8159 8160 u8 reserved_2[0x20]; 8161 }; 8162 8163 struct mlx5_ifc_create_mkey_in_bits { 8164 u8 opcode[0x10]; 8165 u8 reserved_0[0x10]; 8166 8167 u8 reserved_1[0x10]; 8168 u8 op_mod[0x10]; 8169 8170 u8 reserved_2[0x20]; 8171 8172 u8 pg_access[0x1]; 8173 u8 mkey_umem_valid[0x1]; 8174 u8 reserved_at_62[0x1e]; 8175 8176 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 8177 8178 u8 reserved_4[0x80]; 8179 8180 u8 translations_octword_actual_size[0x20]; 8181 8182 u8 reserved_5[0x560]; 8183 8184 u8 klm_pas_mtt[0][0x20]; 8185 }; 8186 8187 struct mlx5_ifc_create_flow_table_out_bits { 8188 u8 status[0x8]; 8189 u8 reserved_0[0x18]; 8190 8191 u8 syndrome[0x20]; 8192 8193 u8 reserved_1[0x8]; 8194 u8 table_id[0x18]; 8195 8196 u8 reserved_2[0x20]; 8197 }; 8198 8199 struct mlx5_ifc_create_flow_table_in_bits { 8200 u8 opcode[0x10]; 8201 u8 uid[0x10]; 8202 8203 u8 reserved_at_20[0x10]; 8204 u8 op_mod[0x10]; 8205 8206 u8 other_vport[0x1]; 8207 u8 reserved_at_41[0xf]; 8208 u8 vport_number[0x10]; 8209 8210 u8 reserved_at_60[0x20]; 8211 8212 u8 table_type[0x8]; 8213 u8 reserved_at_88[0x18]; 8214 8215 u8 reserved_at_a0[0x20]; 8216 8217 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8218 }; 8219 8220 struct mlx5_ifc_create_flow_group_out_bits { 8221 u8 status[0x8]; 8222 u8 reserved_0[0x18]; 8223 8224 u8 syndrome[0x20]; 8225 8226 u8 reserved_1[0x8]; 8227 u8 group_id[0x18]; 8228 8229 u8 reserved_2[0x20]; 8230 }; 8231 8232 enum { 8233 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 8234 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 8235 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 8236 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 8237 }; 8238 8239 struct mlx5_ifc_create_flow_group_in_bits { 8240 u8 opcode[0x10]; 8241 u8 reserved_at_10[0x10]; 8242 8243 u8 reserved_at_20[0x10]; 8244 u8 op_mod[0x10]; 8245 8246 u8 other_vport[0x1]; 8247 u8 reserved_at_41[0xf]; 8248 u8 vport_number[0x10]; 8249 8250 u8 reserved_at_60[0x20]; 8251 8252 u8 table_type[0x8]; 8253 u8 reserved_at_88[0x4]; 8254 u8 group_type[0x4]; 8255 u8 reserved_at_90[0x10]; 8256 8257 u8 reserved_at_a0[0x8]; 8258 u8 table_id[0x18]; 8259 8260 u8 source_eswitch_owner_vhca_id_valid[0x1]; 8261 8262 u8 reserved_at_c1[0x1f]; 8263 8264 u8 start_flow_index[0x20]; 8265 8266 u8 reserved_at_100[0x20]; 8267 8268 u8 end_flow_index[0x20]; 8269 8270 u8 reserved_at_140[0x10]; 8271 u8 match_definer_id[0x10]; 8272 8273 u8 reserved_at_160[0x80]; 8274 8275 u8 reserved_at_1e0[0x18]; 8276 u8 match_criteria_enable[0x8]; 8277 8278 struct mlx5_ifc_fte_match_param_bits match_criteria; 8279 8280 u8 reserved_at_1200[0xe00]; 8281 }; 8282 8283 struct mlx5_ifc_create_encryption_key_out_bits { 8284 u8 status[0x8]; 8285 u8 reserved_at_8[0x18]; 8286 8287 u8 syndrome[0x20]; 8288 8289 u8 obj_id[0x20]; 8290 8291 u8 reserved_at_60[0x20]; 8292 }; 8293 8294 struct mlx5_ifc_create_encryption_key_in_bits { 8295 u8 opcode[0x10]; 8296 u8 reserved_at_10[0x10]; 8297 8298 u8 reserved_at_20[0x10]; 8299 u8 obj_type[0x10]; 8300 8301 u8 reserved_at_40[0x40]; 8302 8303 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 8304 }; 8305 8306 struct mlx5_ifc_create_eq_out_bits { 8307 u8 status[0x8]; 8308 u8 reserved_0[0x18]; 8309 8310 u8 syndrome[0x20]; 8311 8312 u8 reserved_1[0x18]; 8313 u8 eq_number[0x8]; 8314 8315 u8 reserved_2[0x20]; 8316 }; 8317 8318 struct mlx5_ifc_create_eq_in_bits { 8319 u8 opcode[0x10]; 8320 u8 reserved_0[0x10]; 8321 8322 u8 reserved_1[0x10]; 8323 u8 op_mod[0x10]; 8324 8325 u8 reserved_2[0x40]; 8326 8327 struct mlx5_ifc_eqc_bits eq_context_entry; 8328 8329 u8 reserved_3[0x40]; 8330 8331 u8 event_bitmask[0x40]; 8332 8333 u8 reserved_4[0x580]; 8334 8335 u8 pas[0][0x40]; 8336 }; 8337 8338 struct mlx5_ifc_create_dct_out_bits { 8339 u8 status[0x8]; 8340 u8 reserved_0[0x18]; 8341 8342 u8 syndrome[0x20]; 8343 8344 u8 reserved_1[0x8]; 8345 u8 dctn[0x18]; 8346 8347 u8 reserved_2[0x20]; 8348 }; 8349 8350 struct mlx5_ifc_create_dct_in_bits { 8351 u8 opcode[0x10]; 8352 u8 uid[0x10]; 8353 8354 u8 reserved_1[0x10]; 8355 u8 op_mod[0x10]; 8356 8357 u8 reserved_2[0x40]; 8358 8359 struct mlx5_ifc_dctc_bits dct_context_entry; 8360 8361 u8 reserved_3[0x180]; 8362 }; 8363 8364 struct mlx5_ifc_create_cq_out_bits { 8365 u8 status[0x8]; 8366 u8 reserved_0[0x18]; 8367 8368 u8 syndrome[0x20]; 8369 8370 u8 reserved_1[0x8]; 8371 u8 cqn[0x18]; 8372 8373 u8 reserved_2[0x20]; 8374 }; 8375 8376 struct mlx5_ifc_create_cq_in_bits { 8377 u8 opcode[0x10]; 8378 u8 uid[0x10]; 8379 8380 u8 reserved_1[0x10]; 8381 u8 op_mod[0x10]; 8382 8383 u8 reserved_2[0x40]; 8384 8385 struct mlx5_ifc_cqc_bits cq_context; 8386 8387 u8 reserved_at_280[0x60]; 8388 8389 u8 cq_umem_valid[0x1]; 8390 u8 reserved_at_2e1[0x59f]; 8391 8392 u8 pas[0][0x40]; 8393 }; 8394 8395 struct mlx5_ifc_config_int_moderation_out_bits { 8396 u8 status[0x8]; 8397 u8 reserved_0[0x18]; 8398 8399 u8 syndrome[0x20]; 8400 8401 u8 reserved_1[0x4]; 8402 u8 min_delay[0xc]; 8403 u8 int_vector[0x10]; 8404 8405 u8 reserved_2[0x20]; 8406 }; 8407 8408 enum { 8409 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 8410 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 8411 }; 8412 8413 struct mlx5_ifc_config_int_moderation_in_bits { 8414 u8 opcode[0x10]; 8415 u8 reserved_0[0x10]; 8416 8417 u8 reserved_1[0x10]; 8418 u8 op_mod[0x10]; 8419 8420 u8 reserved_2[0x4]; 8421 u8 min_delay[0xc]; 8422 u8 int_vector[0x10]; 8423 8424 u8 reserved_3[0x20]; 8425 }; 8426 8427 struct mlx5_ifc_attach_to_mcg_out_bits { 8428 u8 status[0x8]; 8429 u8 reserved_0[0x18]; 8430 8431 u8 syndrome[0x20]; 8432 8433 u8 reserved_1[0x40]; 8434 }; 8435 8436 struct mlx5_ifc_attach_to_mcg_in_bits { 8437 u8 opcode[0x10]; 8438 u8 uid[0x10]; 8439 8440 u8 reserved_1[0x10]; 8441 u8 op_mod[0x10]; 8442 8443 u8 reserved_2[0x8]; 8444 u8 qpn[0x18]; 8445 8446 u8 reserved_3[0x20]; 8447 8448 u8 multicast_gid[16][0x8]; 8449 }; 8450 8451 struct mlx5_ifc_arm_xrq_out_bits { 8452 u8 status[0x8]; 8453 u8 reserved_at_8[0x18]; 8454 8455 u8 syndrome[0x20]; 8456 8457 u8 reserved_at_40[0x40]; 8458 }; 8459 8460 struct mlx5_ifc_arm_xrq_in_bits { 8461 u8 opcode[0x10]; 8462 u8 reserved_at_10[0x10]; 8463 8464 u8 reserved_at_20[0x10]; 8465 u8 op_mod[0x10]; 8466 8467 u8 reserved_at_40[0x8]; 8468 u8 xrqn[0x18]; 8469 8470 u8 reserved_at_60[0x10]; 8471 u8 lwm[0x10]; 8472 }; 8473 8474 struct mlx5_ifc_arm_xrc_srq_out_bits { 8475 u8 status[0x8]; 8476 u8 reserved_0[0x18]; 8477 8478 u8 syndrome[0x20]; 8479 8480 u8 reserved_1[0x40]; 8481 }; 8482 8483 enum { 8484 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 8485 }; 8486 8487 struct mlx5_ifc_arm_xrc_srq_in_bits { 8488 u8 opcode[0x10]; 8489 u8 uid[0x10]; 8490 8491 u8 reserved_1[0x10]; 8492 u8 op_mod[0x10]; 8493 8494 u8 reserved_2[0x8]; 8495 u8 xrc_srqn[0x18]; 8496 8497 u8 reserved_3[0x10]; 8498 u8 lwm[0x10]; 8499 }; 8500 8501 struct mlx5_ifc_arm_rq_out_bits { 8502 u8 status[0x8]; 8503 u8 reserved_0[0x18]; 8504 8505 u8 syndrome[0x20]; 8506 8507 u8 reserved_1[0x40]; 8508 }; 8509 8510 enum { 8511 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 8512 }; 8513 8514 struct mlx5_ifc_arm_rq_in_bits { 8515 u8 opcode[0x10]; 8516 u8 uid[0x10]; 8517 8518 u8 reserved_1[0x10]; 8519 u8 op_mod[0x10]; 8520 8521 u8 reserved_2[0x8]; 8522 u8 srq_number[0x18]; 8523 8524 u8 reserved_3[0x10]; 8525 u8 lwm[0x10]; 8526 }; 8527 8528 struct mlx5_ifc_arm_dct_out_bits { 8529 u8 status[0x8]; 8530 u8 reserved_0[0x18]; 8531 8532 u8 syndrome[0x20]; 8533 8534 u8 reserved_1[0x40]; 8535 }; 8536 8537 struct mlx5_ifc_arm_dct_in_bits { 8538 u8 opcode[0x10]; 8539 u8 reserved_0[0x10]; 8540 8541 u8 reserved_1[0x10]; 8542 u8 op_mod[0x10]; 8543 8544 u8 reserved_2[0x8]; 8545 u8 dctn[0x18]; 8546 8547 u8 reserved_3[0x20]; 8548 }; 8549 8550 struct mlx5_ifc_alloc_xrcd_out_bits { 8551 u8 status[0x8]; 8552 u8 reserved_0[0x18]; 8553 8554 u8 syndrome[0x20]; 8555 8556 u8 reserved_1[0x8]; 8557 u8 xrcd[0x18]; 8558 8559 u8 reserved_2[0x20]; 8560 }; 8561 8562 struct mlx5_ifc_alloc_xrcd_in_bits { 8563 u8 opcode[0x10]; 8564 u8 uid[0x10]; 8565 8566 u8 reserved_1[0x10]; 8567 u8 op_mod[0x10]; 8568 8569 u8 reserved_2[0x40]; 8570 }; 8571 8572 struct mlx5_ifc_alloc_uar_out_bits { 8573 u8 status[0x8]; 8574 u8 reserved_0[0x18]; 8575 8576 u8 syndrome[0x20]; 8577 8578 u8 reserved_1[0x8]; 8579 u8 uar[0x18]; 8580 8581 u8 reserved_2[0x20]; 8582 }; 8583 8584 struct mlx5_ifc_alloc_uar_in_bits { 8585 u8 opcode[0x10]; 8586 u8 reserved_0[0x10]; 8587 8588 u8 reserved_1[0x10]; 8589 u8 op_mod[0x10]; 8590 8591 u8 reserved_2[0x40]; 8592 }; 8593 8594 struct mlx5_ifc_alloc_transport_domain_out_bits { 8595 u8 status[0x8]; 8596 u8 reserved_0[0x18]; 8597 8598 u8 syndrome[0x20]; 8599 8600 u8 reserved_1[0x8]; 8601 u8 transport_domain[0x18]; 8602 8603 u8 reserved_2[0x20]; 8604 }; 8605 8606 struct mlx5_ifc_alloc_transport_domain_in_bits { 8607 u8 opcode[0x10]; 8608 u8 uid[0x10]; 8609 8610 u8 reserved_1[0x10]; 8611 u8 op_mod[0x10]; 8612 8613 u8 reserved_2[0x40]; 8614 }; 8615 8616 struct mlx5_ifc_alloc_q_counter_out_bits { 8617 u8 status[0x8]; 8618 u8 reserved_0[0x18]; 8619 8620 u8 syndrome[0x20]; 8621 8622 u8 reserved_1[0x18]; 8623 u8 counter_set_id[0x8]; 8624 8625 u8 reserved_2[0x20]; 8626 }; 8627 8628 struct mlx5_ifc_alloc_q_counter_in_bits { 8629 u8 opcode[0x10]; 8630 u8 uid[0x10]; 8631 8632 u8 reserved_1[0x10]; 8633 u8 op_mod[0x10]; 8634 8635 u8 reserved_2[0x40]; 8636 }; 8637 8638 struct mlx5_ifc_alloc_pd_out_bits { 8639 u8 status[0x8]; 8640 u8 reserved_0[0x18]; 8641 8642 u8 syndrome[0x20]; 8643 8644 u8 reserved_1[0x8]; 8645 u8 pd[0x18]; 8646 8647 u8 reserved_2[0x20]; 8648 }; 8649 8650 struct mlx5_ifc_alloc_pd_in_bits { 8651 u8 opcode[0x10]; 8652 u8 uid[0x10]; 8653 8654 u8 reserved_1[0x10]; 8655 u8 op_mod[0x10]; 8656 8657 u8 reserved_2[0x40]; 8658 }; 8659 8660 struct mlx5_ifc_alloc_flow_counter_out_bits { 8661 u8 status[0x8]; 8662 u8 reserved_at_8[0x18]; 8663 8664 u8 syndrome[0x20]; 8665 8666 u8 flow_counter_id[0x20]; 8667 8668 u8 reserved_at_60[0x20]; 8669 }; 8670 8671 struct mlx5_ifc_alloc_flow_counter_in_bits { 8672 u8 opcode[0x10]; 8673 u8 reserved_at_10[0x10]; 8674 8675 u8 reserved_at_20[0x10]; 8676 u8 op_mod[0x10]; 8677 8678 u8 reserved_at_40[0x38]; 8679 u8 flow_counter_bulk[0x8]; 8680 }; 8681 8682 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 8683 u8 status[0x8]; 8684 u8 reserved_0[0x18]; 8685 8686 u8 syndrome[0x20]; 8687 8688 u8 reserved_1[0x40]; 8689 }; 8690 8691 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 8692 u8 opcode[0x10]; 8693 u8 reserved_0[0x10]; 8694 8695 u8 reserved_1[0x10]; 8696 u8 op_mod[0x10]; 8697 8698 u8 reserved_2[0x20]; 8699 8700 u8 reserved_3[0x10]; 8701 u8 vxlan_udp_port[0x10]; 8702 }; 8703 8704 struct mlx5_ifc_activate_tracer_out_bits { 8705 u8 status[0x8]; 8706 u8 reserved_0[0x18]; 8707 8708 u8 syndrome[0x20]; 8709 8710 u8 reserved_1[0x40]; 8711 }; 8712 8713 struct mlx5_ifc_activate_tracer_in_bits { 8714 u8 opcode[0x10]; 8715 u8 reserved_0[0x10]; 8716 8717 u8 reserved_1[0x10]; 8718 u8 op_mod[0x10]; 8719 8720 u8 mkey[0x20]; 8721 8722 u8 reserved_2[0x20]; 8723 }; 8724 8725 struct mlx5_ifc_set_rate_limit_out_bits { 8726 u8 status[0x8]; 8727 u8 reserved_at_8[0x18]; 8728 8729 u8 syndrome[0x20]; 8730 8731 u8 reserved_at_40[0x40]; 8732 }; 8733 8734 struct mlx5_ifc_set_rate_limit_in_bits { 8735 u8 opcode[0x10]; 8736 u8 uid[0x10]; 8737 8738 u8 reserved_at_20[0x10]; 8739 u8 op_mod[0x10]; 8740 8741 u8 reserved_at_40[0x10]; 8742 u8 rate_limit_index[0x10]; 8743 8744 u8 reserved_at_60[0x20]; 8745 8746 u8 rate_limit[0x20]; 8747 8748 u8 burst_upper_bound[0x20]; 8749 8750 u8 reserved_at_c0[0x10]; 8751 u8 typical_packet_size[0x10]; 8752 8753 u8 reserved_at_e0[0x120]; 8754 }; 8755 8756 struct mlx5_ifc_access_register_out_bits { 8757 u8 status[0x8]; 8758 u8 reserved_0[0x18]; 8759 8760 u8 syndrome[0x20]; 8761 8762 u8 reserved_1[0x40]; 8763 8764 u8 register_data[0][0x20]; 8765 }; 8766 8767 enum { 8768 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 8769 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 8770 }; 8771 8772 struct mlx5_ifc_access_register_in_bits { 8773 u8 opcode[0x10]; 8774 u8 reserved_0[0x10]; 8775 8776 u8 reserved_1[0x10]; 8777 u8 op_mod[0x10]; 8778 8779 u8 reserved_2[0x10]; 8780 u8 register_id[0x10]; 8781 8782 u8 argument[0x20]; 8783 8784 u8 register_data[0][0x20]; 8785 }; 8786 8787 struct mlx5_ifc_sltp_reg_bits { 8788 u8 status[0x4]; 8789 u8 version[0x4]; 8790 u8 local_port[0x8]; 8791 u8 pnat[0x2]; 8792 u8 reserved_0[0x2]; 8793 u8 lane[0x4]; 8794 u8 reserved_1[0x8]; 8795 8796 u8 reserved_2[0x20]; 8797 8798 u8 reserved_3[0x7]; 8799 u8 polarity[0x1]; 8800 u8 ob_tap0[0x8]; 8801 u8 ob_tap1[0x8]; 8802 u8 ob_tap2[0x8]; 8803 8804 u8 reserved_4[0xc]; 8805 u8 ob_preemp_mode[0x4]; 8806 u8 ob_reg[0x8]; 8807 u8 ob_bias[0x8]; 8808 8809 u8 reserved_5[0x20]; 8810 }; 8811 8812 struct mlx5_ifc_slrp_reg_bits { 8813 u8 status[0x4]; 8814 u8 version[0x4]; 8815 u8 local_port[0x8]; 8816 u8 pnat[0x2]; 8817 u8 reserved_0[0x2]; 8818 u8 lane[0x4]; 8819 u8 reserved_1[0x8]; 8820 8821 u8 ib_sel[0x2]; 8822 u8 reserved_2[0x11]; 8823 u8 dp_sel[0x1]; 8824 u8 dp90sel[0x4]; 8825 u8 mix90phase[0x8]; 8826 8827 u8 ffe_tap0[0x8]; 8828 u8 ffe_tap1[0x8]; 8829 u8 ffe_tap2[0x8]; 8830 u8 ffe_tap3[0x8]; 8831 8832 u8 ffe_tap4[0x8]; 8833 u8 ffe_tap5[0x8]; 8834 u8 ffe_tap6[0x8]; 8835 u8 ffe_tap7[0x8]; 8836 8837 u8 ffe_tap8[0x8]; 8838 u8 mixerbias_tap_amp[0x8]; 8839 u8 reserved_3[0x7]; 8840 u8 ffe_tap_en[0x9]; 8841 8842 u8 ffe_tap_offset0[0x8]; 8843 u8 ffe_tap_offset1[0x8]; 8844 u8 slicer_offset0[0x10]; 8845 8846 u8 mixer_offset0[0x10]; 8847 u8 mixer_offset1[0x10]; 8848 8849 u8 mixerbgn_inp[0x8]; 8850 u8 mixerbgn_inn[0x8]; 8851 u8 mixerbgn_refp[0x8]; 8852 u8 mixerbgn_refn[0x8]; 8853 8854 u8 sel_slicer_lctrl_h[0x1]; 8855 u8 sel_slicer_lctrl_l[0x1]; 8856 u8 reserved_4[0x1]; 8857 u8 ref_mixer_vreg[0x5]; 8858 u8 slicer_gctrl[0x8]; 8859 u8 lctrl_input[0x8]; 8860 u8 mixer_offset_cm1[0x8]; 8861 8862 u8 common_mode[0x6]; 8863 u8 reserved_5[0x1]; 8864 u8 mixer_offset_cm0[0x9]; 8865 u8 reserved_6[0x7]; 8866 u8 slicer_offset_cm[0x9]; 8867 }; 8868 8869 struct mlx5_ifc_slrg_reg_bits { 8870 u8 status[0x4]; 8871 u8 version[0x4]; 8872 u8 local_port[0x8]; 8873 u8 pnat[0x2]; 8874 u8 reserved_0[0x2]; 8875 u8 lane[0x4]; 8876 u8 reserved_1[0x8]; 8877 8878 u8 time_to_link_up[0x10]; 8879 u8 reserved_2[0xc]; 8880 u8 grade_lane_speed[0x4]; 8881 8882 u8 grade_version[0x8]; 8883 u8 grade[0x18]; 8884 8885 u8 reserved_3[0x4]; 8886 u8 height_grade_type[0x4]; 8887 u8 height_grade[0x18]; 8888 8889 u8 height_dz[0x10]; 8890 u8 height_dv[0x10]; 8891 8892 u8 reserved_4[0x10]; 8893 u8 height_sigma[0x10]; 8894 8895 u8 reserved_5[0x20]; 8896 8897 u8 reserved_6[0x4]; 8898 u8 phase_grade_type[0x4]; 8899 u8 phase_grade[0x18]; 8900 8901 u8 reserved_7[0x8]; 8902 u8 phase_eo_pos[0x8]; 8903 u8 reserved_8[0x8]; 8904 u8 phase_eo_neg[0x8]; 8905 8906 u8 ffe_set_tested[0x10]; 8907 u8 test_errors_per_lane[0x10]; 8908 }; 8909 8910 struct mlx5_ifc_pvlc_reg_bits { 8911 u8 reserved_0[0x8]; 8912 u8 local_port[0x8]; 8913 u8 reserved_1[0x10]; 8914 8915 u8 reserved_2[0x1c]; 8916 u8 vl_hw_cap[0x4]; 8917 8918 u8 reserved_3[0x1c]; 8919 u8 vl_admin[0x4]; 8920 8921 u8 reserved_4[0x1c]; 8922 u8 vl_operational[0x4]; 8923 }; 8924 8925 struct mlx5_ifc_pude_reg_bits { 8926 u8 swid[0x8]; 8927 u8 local_port[0x8]; 8928 u8 reserved_0[0x4]; 8929 u8 admin_status[0x4]; 8930 u8 reserved_1[0x4]; 8931 u8 oper_status[0x4]; 8932 8933 u8 reserved_2[0x60]; 8934 }; 8935 8936 enum { 8937 MLX5_PTYS_REG_PROTO_MASK_INFINIBAND = 0x1, 8938 MLX5_PTYS_REG_PROTO_MASK_ETHERNET = 0x4, 8939 }; 8940 8941 struct mlx5_ifc_ptys_reg_bits { 8942 u8 reserved_0[0x1]; 8943 u8 an_disable_admin[0x1]; 8944 u8 an_disable_cap[0x1]; 8945 u8 reserved_1[0x4]; 8946 u8 force_tx_aba_param[0x1]; 8947 u8 local_port[0x8]; 8948 u8 reserved_2[0xd]; 8949 u8 proto_mask[0x3]; 8950 8951 u8 an_status[0x4]; 8952 u8 reserved_3[0xc]; 8953 u8 data_rate_oper[0x10]; 8954 8955 u8 ext_eth_proto_capability[0x20]; 8956 8957 u8 eth_proto_capability[0x20]; 8958 8959 u8 ib_link_width_capability[0x10]; 8960 u8 ib_proto_capability[0x10]; 8961 8962 u8 ext_eth_proto_admin[0x20]; 8963 8964 u8 eth_proto_admin[0x20]; 8965 8966 u8 ib_link_width_admin[0x10]; 8967 u8 ib_proto_admin[0x10]; 8968 8969 u8 ext_eth_proto_oper[0x20]; 8970 8971 u8 eth_proto_oper[0x20]; 8972 8973 u8 ib_link_width_oper[0x10]; 8974 u8 ib_proto_oper[0x10]; 8975 8976 u8 reserved_4[0x1c]; 8977 u8 connector_type[0x4]; 8978 8979 u8 eth_proto_lp_advertise[0x20]; 8980 8981 u8 reserved_5[0x60]; 8982 }; 8983 8984 struct mlx5_ifc_ptas_reg_bits { 8985 u8 reserved_0[0x20]; 8986 8987 u8 algorithm_options[0x10]; 8988 u8 reserved_1[0x4]; 8989 u8 repetitions_mode[0x4]; 8990 u8 num_of_repetitions[0x8]; 8991 8992 u8 grade_version[0x8]; 8993 u8 height_grade_type[0x4]; 8994 u8 phase_grade_type[0x4]; 8995 u8 height_grade_weight[0x8]; 8996 u8 phase_grade_weight[0x8]; 8997 8998 u8 gisim_measure_bits[0x10]; 8999 u8 adaptive_tap_measure_bits[0x10]; 9000 9001 u8 ber_bath_high_error_threshold[0x10]; 9002 u8 ber_bath_mid_error_threshold[0x10]; 9003 9004 u8 ber_bath_low_error_threshold[0x10]; 9005 u8 one_ratio_high_threshold[0x10]; 9006 9007 u8 one_ratio_high_mid_threshold[0x10]; 9008 u8 one_ratio_low_mid_threshold[0x10]; 9009 9010 u8 one_ratio_low_threshold[0x10]; 9011 u8 ndeo_error_threshold[0x10]; 9012 9013 u8 mixer_offset_step_size[0x10]; 9014 u8 reserved_2[0x8]; 9015 u8 mix90_phase_for_voltage_bath[0x8]; 9016 9017 u8 mixer_offset_start[0x10]; 9018 u8 mixer_offset_end[0x10]; 9019 9020 u8 reserved_3[0x15]; 9021 u8 ber_test_time[0xb]; 9022 }; 9023 9024 struct mlx5_ifc_pspa_reg_bits { 9025 u8 swid[0x8]; 9026 u8 local_port[0x8]; 9027 u8 sub_port[0x8]; 9028 u8 reserved_0[0x8]; 9029 9030 u8 reserved_1[0x20]; 9031 }; 9032 9033 struct mlx5_ifc_ppsc_reg_bits { 9034 u8 reserved_0[0x8]; 9035 u8 local_port[0x8]; 9036 u8 reserved_1[0x10]; 9037 9038 u8 reserved_2[0x60]; 9039 9040 u8 reserved_3[0x1c]; 9041 u8 wrps_admin[0x4]; 9042 9043 u8 reserved_4[0x1c]; 9044 u8 wrps_status[0x4]; 9045 9046 u8 up_th_vld[0x1]; 9047 u8 down_th_vld[0x1]; 9048 u8 reserved_5[0x6]; 9049 u8 up_threshold[0x8]; 9050 u8 reserved_6[0x8]; 9051 u8 down_threshold[0x8]; 9052 9053 u8 reserved_7[0x20]; 9054 9055 u8 reserved_8[0x1c]; 9056 u8 srps_admin[0x4]; 9057 9058 u8 reserved_9[0x60]; 9059 }; 9060 9061 struct mlx5_ifc_pplr_reg_bits { 9062 u8 reserved_0[0x8]; 9063 u8 local_port[0x8]; 9064 u8 reserved_1[0x10]; 9065 9066 u8 reserved_2[0x8]; 9067 u8 lb_cap[0x8]; 9068 u8 reserved_3[0x8]; 9069 u8 lb_en[0x8]; 9070 }; 9071 9072 struct mlx5_ifc_pplm_reg_bits { 9073 u8 reserved_at_0[0x8]; 9074 u8 local_port[0x8]; 9075 u8 reserved_at_10[0x10]; 9076 9077 u8 reserved_at_20[0x20]; 9078 9079 u8 port_profile_mode[0x8]; 9080 u8 static_port_profile[0x8]; 9081 u8 active_port_profile[0x8]; 9082 u8 reserved_at_58[0x8]; 9083 9084 u8 retransmission_active[0x8]; 9085 u8 fec_mode_active[0x18]; 9086 9087 u8 rs_fec_correction_bypass_cap[0x4]; 9088 u8 reserved_at_84[0x8]; 9089 u8 fec_override_cap_56g[0x4]; 9090 u8 fec_override_cap_100g[0x4]; 9091 u8 fec_override_cap_50g[0x4]; 9092 u8 fec_override_cap_25g[0x4]; 9093 u8 fec_override_cap_10g_40g[0x4]; 9094 9095 u8 rs_fec_correction_bypass_admin[0x4]; 9096 u8 reserved_at_a4[0x8]; 9097 u8 fec_override_admin_56g[0x4]; 9098 u8 fec_override_admin_100g[0x4]; 9099 u8 fec_override_admin_50g[0x4]; 9100 u8 fec_override_admin_25g[0x4]; 9101 u8 fec_override_admin_10g_40g[0x4]; 9102 9103 u8 fec_override_cap_400g_8x[0x10]; 9104 u8 fec_override_cap_200g_4x[0x10]; 9105 u8 fec_override_cap_100g_2x[0x10]; 9106 u8 fec_override_cap_50g_1x[0x10]; 9107 9108 u8 fec_override_admin_400g_8x[0x10]; 9109 u8 fec_override_admin_200g_4x[0x10]; 9110 u8 fec_override_admin_100g_2x[0x10]; 9111 u8 fec_override_admin_50g_1x[0x10]; 9112 9113 u8 reserved_at_140[0x140]; 9114 }; 9115 9116 struct mlx5_ifc_ppll_reg_bits { 9117 u8 num_pll_groups[0x8]; 9118 u8 pll_group[0x8]; 9119 u8 reserved_0[0x4]; 9120 u8 num_plls[0x4]; 9121 u8 reserved_1[0x8]; 9122 9123 u8 reserved_2[0x1f]; 9124 u8 ae[0x1]; 9125 9126 u8 pll_status[4][0x40]; 9127 }; 9128 9129 struct mlx5_ifc_ppad_reg_bits { 9130 u8 reserved_0[0x3]; 9131 u8 single_mac[0x1]; 9132 u8 reserved_1[0x4]; 9133 u8 local_port[0x8]; 9134 u8 mac_47_32[0x10]; 9135 9136 u8 mac_31_0[0x20]; 9137 9138 u8 reserved_2[0x40]; 9139 }; 9140 9141 struct mlx5_ifc_pmtu_reg_bits { 9142 u8 reserved_0[0x8]; 9143 u8 local_port[0x8]; 9144 u8 reserved_1[0x10]; 9145 9146 u8 max_mtu[0x10]; 9147 u8 reserved_2[0x10]; 9148 9149 u8 admin_mtu[0x10]; 9150 u8 reserved_3[0x10]; 9151 9152 u8 oper_mtu[0x10]; 9153 u8 reserved_4[0x10]; 9154 }; 9155 9156 struct mlx5_ifc_pmpr_reg_bits { 9157 u8 reserved_0[0x8]; 9158 u8 module[0x8]; 9159 u8 reserved_1[0x10]; 9160 9161 u8 reserved_2[0x18]; 9162 u8 attenuation_5g[0x8]; 9163 9164 u8 reserved_3[0x18]; 9165 u8 attenuation_7g[0x8]; 9166 9167 u8 reserved_4[0x18]; 9168 u8 attenuation_12g[0x8]; 9169 }; 9170 9171 struct mlx5_ifc_pmpe_reg_bits { 9172 u8 reserved_0[0x8]; 9173 u8 module[0x8]; 9174 u8 reserved_1[0xc]; 9175 u8 module_status[0x4]; 9176 9177 u8 reserved_2[0x14]; 9178 u8 error_type[0x4]; 9179 u8 reserved_3[0x8]; 9180 9181 u8 reserved_4[0x40]; 9182 }; 9183 9184 struct mlx5_ifc_pmpc_reg_bits { 9185 u8 module_state_updated[32][0x8]; 9186 }; 9187 9188 struct mlx5_ifc_pmlpn_reg_bits { 9189 u8 reserved_0[0x4]; 9190 u8 mlpn_status[0x4]; 9191 u8 local_port[0x8]; 9192 u8 reserved_1[0x10]; 9193 9194 u8 e[0x1]; 9195 u8 reserved_2[0x1f]; 9196 }; 9197 9198 struct mlx5_ifc_pmlp_reg_bits { 9199 u8 rxtx[0x1]; 9200 u8 reserved_0[0x7]; 9201 u8 local_port[0x8]; 9202 u8 reserved_1[0x8]; 9203 u8 width[0x8]; 9204 9205 u8 lane0_module_mapping[0x20]; 9206 9207 u8 lane1_module_mapping[0x20]; 9208 9209 u8 lane2_module_mapping[0x20]; 9210 9211 u8 lane3_module_mapping[0x20]; 9212 9213 u8 reserved_2[0x160]; 9214 }; 9215 9216 struct mlx5_ifc_pmaos_reg_bits { 9217 u8 reserved_0[0x8]; 9218 u8 module[0x8]; 9219 u8 reserved_1[0x4]; 9220 u8 admin_status[0x4]; 9221 u8 reserved_2[0x4]; 9222 u8 oper_status[0x4]; 9223 9224 u8 ase[0x1]; 9225 u8 ee[0x1]; 9226 u8 reserved_3[0x12]; 9227 u8 error_type[0x4]; 9228 u8 reserved_4[0x6]; 9229 u8 e[0x2]; 9230 9231 u8 reserved_5[0x40]; 9232 }; 9233 9234 struct mlx5_ifc_plpc_reg_bits { 9235 u8 reserved_0[0x4]; 9236 u8 profile_id[0xc]; 9237 u8 reserved_1[0x4]; 9238 u8 proto_mask[0x4]; 9239 u8 reserved_2[0x8]; 9240 9241 u8 reserved_3[0x10]; 9242 u8 lane_speed[0x10]; 9243 9244 u8 reserved_4[0x17]; 9245 u8 lpbf[0x1]; 9246 u8 fec_mode_policy[0x8]; 9247 9248 u8 retransmission_capability[0x8]; 9249 u8 fec_mode_capability[0x18]; 9250 9251 u8 retransmission_support_admin[0x8]; 9252 u8 fec_mode_support_admin[0x18]; 9253 9254 u8 retransmission_request_admin[0x8]; 9255 u8 fec_mode_request_admin[0x18]; 9256 9257 u8 reserved_5[0x80]; 9258 }; 9259 9260 struct mlx5_ifc_pll_status_data_bits { 9261 u8 reserved_0[0x1]; 9262 u8 lock_cal[0x1]; 9263 u8 lock_status[0x2]; 9264 u8 reserved_1[0x2]; 9265 u8 algo_f_ctrl[0xa]; 9266 u8 analog_algo_num_var[0x6]; 9267 u8 f_ctrl_measure[0xa]; 9268 9269 u8 reserved_2[0x2]; 9270 u8 analog_var[0x6]; 9271 u8 reserved_3[0x2]; 9272 u8 high_var[0x6]; 9273 u8 reserved_4[0x2]; 9274 u8 low_var[0x6]; 9275 u8 reserved_5[0x2]; 9276 u8 mid_val[0x6]; 9277 }; 9278 9279 struct mlx5_ifc_plib_reg_bits { 9280 u8 reserved_0[0x8]; 9281 u8 local_port[0x8]; 9282 u8 reserved_1[0x8]; 9283 u8 ib_port[0x8]; 9284 9285 u8 reserved_2[0x60]; 9286 }; 9287 9288 struct mlx5_ifc_plbf_reg_bits { 9289 u8 reserved_0[0x8]; 9290 u8 local_port[0x8]; 9291 u8 reserved_1[0xd]; 9292 u8 lbf_mode[0x3]; 9293 9294 u8 reserved_2[0x20]; 9295 }; 9296 9297 struct mlx5_ifc_pipg_reg_bits { 9298 u8 reserved_0[0x8]; 9299 u8 local_port[0x8]; 9300 u8 reserved_1[0x10]; 9301 9302 u8 dic[0x1]; 9303 u8 reserved_2[0x19]; 9304 u8 ipg[0x4]; 9305 u8 reserved_3[0x2]; 9306 }; 9307 9308 struct mlx5_ifc_pifr_reg_bits { 9309 u8 reserved_0[0x8]; 9310 u8 local_port[0x8]; 9311 u8 reserved_1[0x10]; 9312 9313 u8 reserved_2[0xe0]; 9314 9315 u8 port_filter[8][0x20]; 9316 9317 u8 port_filter_update_en[8][0x20]; 9318 }; 9319 9320 struct mlx5_ifc_phys_layer_cntrs_bits { 9321 u8 time_since_last_clear_high[0x20]; 9322 9323 u8 time_since_last_clear_low[0x20]; 9324 9325 u8 symbol_errors_high[0x20]; 9326 9327 u8 symbol_errors_low[0x20]; 9328 9329 u8 sync_headers_errors_high[0x20]; 9330 9331 u8 sync_headers_errors_low[0x20]; 9332 9333 u8 edpl_bip_errors_lane0_high[0x20]; 9334 9335 u8 edpl_bip_errors_lane0_low[0x20]; 9336 9337 u8 edpl_bip_errors_lane1_high[0x20]; 9338 9339 u8 edpl_bip_errors_lane1_low[0x20]; 9340 9341 u8 edpl_bip_errors_lane2_high[0x20]; 9342 9343 u8 edpl_bip_errors_lane2_low[0x20]; 9344 9345 u8 edpl_bip_errors_lane3_high[0x20]; 9346 9347 u8 edpl_bip_errors_lane3_low[0x20]; 9348 9349 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 9350 9351 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 9352 9353 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 9354 9355 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 9356 9357 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 9358 9359 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 9360 9361 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 9362 9363 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 9364 9365 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 9366 9367 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 9368 9369 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 9370 9371 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 9372 9373 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 9374 9375 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 9376 9377 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 9378 9379 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 9380 9381 u8 rs_fec_corrected_blocks_high[0x20]; 9382 9383 u8 rs_fec_corrected_blocks_low[0x20]; 9384 9385 u8 rs_fec_uncorrectable_blocks_high[0x20]; 9386 9387 u8 rs_fec_uncorrectable_blocks_low[0x20]; 9388 9389 u8 rs_fec_no_errors_blocks_high[0x20]; 9390 9391 u8 rs_fec_no_errors_blocks_low[0x20]; 9392 9393 u8 rs_fec_single_error_blocks_high[0x20]; 9394 9395 u8 rs_fec_single_error_blocks_low[0x20]; 9396 9397 u8 rs_fec_corrected_symbols_total_high[0x20]; 9398 9399 u8 rs_fec_corrected_symbols_total_low[0x20]; 9400 9401 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 9402 9403 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 9404 9405 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 9406 9407 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 9408 9409 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 9410 9411 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 9412 9413 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 9414 9415 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 9416 9417 u8 link_down_events[0x20]; 9418 9419 u8 successful_recovery_events[0x20]; 9420 9421 u8 reserved_0[0x180]; 9422 }; 9423 9424 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 9425 u8 symbol_error_counter[0x10]; 9426 9427 u8 link_error_recovery_counter[0x8]; 9428 9429 u8 link_downed_counter[0x8]; 9430 9431 u8 port_rcv_errors[0x10]; 9432 9433 u8 port_rcv_remote_physical_errors[0x10]; 9434 9435 u8 port_rcv_switch_relay_errors[0x10]; 9436 9437 u8 port_xmit_discards[0x10]; 9438 9439 u8 port_xmit_constraint_errors[0x8]; 9440 9441 u8 port_rcv_constraint_errors[0x8]; 9442 9443 u8 reserved_at_70[0x8]; 9444 9445 u8 link_overrun_errors[0x8]; 9446 9447 u8 reserved_at_80[0x10]; 9448 9449 u8 vl_15_dropped[0x10]; 9450 9451 u8 reserved_at_a0[0xa0]; 9452 }; 9453 9454 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 9455 u8 time_since_last_clear_high[0x20]; 9456 9457 u8 time_since_last_clear_low[0x20]; 9458 9459 u8 phy_received_bits_high[0x20]; 9460 9461 u8 phy_received_bits_low[0x20]; 9462 9463 u8 phy_symbol_errors_high[0x20]; 9464 9465 u8 phy_symbol_errors_low[0x20]; 9466 9467 u8 phy_corrected_bits_high[0x20]; 9468 9469 u8 phy_corrected_bits_low[0x20]; 9470 9471 u8 phy_corrected_bits_lane0_high[0x20]; 9472 9473 u8 phy_corrected_bits_lane0_low[0x20]; 9474 9475 u8 phy_corrected_bits_lane1_high[0x20]; 9476 9477 u8 phy_corrected_bits_lane1_low[0x20]; 9478 9479 u8 phy_corrected_bits_lane2_high[0x20]; 9480 9481 u8 phy_corrected_bits_lane2_low[0x20]; 9482 9483 u8 phy_corrected_bits_lane3_high[0x20]; 9484 9485 u8 phy_corrected_bits_lane3_low[0x20]; 9486 9487 u8 reserved_at_200[0x5c0]; 9488 }; 9489 9490 struct mlx5_ifc_infiniband_port_cntrs_bits { 9491 u8 symbol_error_counter[0x10]; 9492 u8 link_error_recovery_counter[0x8]; 9493 u8 link_downed_counter[0x8]; 9494 9495 u8 port_rcv_errors[0x10]; 9496 u8 port_rcv_remote_physical_errors[0x10]; 9497 9498 u8 port_rcv_switch_relay_errors[0x10]; 9499 u8 port_xmit_discards[0x10]; 9500 9501 u8 port_xmit_constraint_errors[0x8]; 9502 u8 port_rcv_constraint_errors[0x8]; 9503 u8 reserved_0[0x8]; 9504 u8 local_link_integrity_errors[0x4]; 9505 u8 excessive_buffer_overrun_errors[0x4]; 9506 9507 u8 reserved_1[0x10]; 9508 u8 vl_15_dropped[0x10]; 9509 9510 u8 port_xmit_data[0x20]; 9511 9512 u8 port_rcv_data[0x20]; 9513 9514 u8 port_xmit_pkts[0x20]; 9515 9516 u8 port_rcv_pkts[0x20]; 9517 9518 u8 port_xmit_wait[0x20]; 9519 9520 u8 reserved_2[0x680]; 9521 }; 9522 9523 struct mlx5_ifc_phrr_reg_bits { 9524 u8 clr[0x1]; 9525 u8 reserved_0[0x7]; 9526 u8 local_port[0x8]; 9527 u8 reserved_1[0x10]; 9528 9529 u8 hist_group[0x8]; 9530 u8 reserved_2[0x10]; 9531 u8 hist_id[0x8]; 9532 9533 u8 reserved_3[0x40]; 9534 9535 u8 time_since_last_clear_high[0x20]; 9536 9537 u8 time_since_last_clear_low[0x20]; 9538 9539 u8 bin[10][0x20]; 9540 }; 9541 9542 struct mlx5_ifc_phbr_for_prio_reg_bits { 9543 u8 reserved_0[0x18]; 9544 u8 prio[0x8]; 9545 }; 9546 9547 struct mlx5_ifc_phbr_for_port_tclass_reg_bits { 9548 u8 reserved_0[0x18]; 9549 u8 tclass[0x8]; 9550 }; 9551 9552 struct mlx5_ifc_phbr_binding_reg_bits { 9553 u8 opcode[0x4]; 9554 u8 reserved_0[0x4]; 9555 u8 local_port[0x8]; 9556 u8 pnat[0x2]; 9557 u8 reserved_1[0xe]; 9558 9559 u8 hist_group[0x8]; 9560 u8 reserved_2[0x10]; 9561 u8 hist_id[0x8]; 9562 9563 u8 reserved_3[0x10]; 9564 u8 hist_type[0x10]; 9565 9566 u8 hist_parameters[0x20]; 9567 9568 u8 hist_min_value[0x20]; 9569 9570 u8 hist_max_value[0x20]; 9571 9572 u8 sample_time[0x20]; 9573 }; 9574 9575 enum { 9576 MLX5_PFCC_REG_PPAN_DISABLED = 0x0, 9577 MLX5_PFCC_REG_PPAN_ENABLED = 0x1, 9578 }; 9579 9580 struct mlx5_ifc_pfcc_reg_bits { 9581 u8 dcbx_operation_type[0x2]; 9582 u8 cap_local_admin[0x1]; 9583 u8 cap_remote_admin[0x1]; 9584 u8 reserved_0[0x4]; 9585 u8 local_port[0x8]; 9586 u8 pnat[0x2]; 9587 u8 reserved_1[0xc]; 9588 u8 shl_cap[0x1]; 9589 u8 shl_opr[0x1]; 9590 9591 u8 ppan[0x4]; 9592 u8 reserved_2[0x4]; 9593 u8 prio_mask_tx[0x8]; 9594 u8 reserved_3[0x8]; 9595 u8 prio_mask_rx[0x8]; 9596 9597 u8 pptx[0x1]; 9598 u8 aptx[0x1]; 9599 u8 reserved_4[0x6]; 9600 u8 pfctx[0x8]; 9601 u8 reserved_5[0x8]; 9602 u8 cbftx[0x8]; 9603 9604 u8 pprx[0x1]; 9605 u8 aprx[0x1]; 9606 u8 reserved_6[0x6]; 9607 u8 pfcrx[0x8]; 9608 u8 reserved_7[0x8]; 9609 u8 cbfrx[0x8]; 9610 9611 u8 device_stall_minor_watermark[0x10]; 9612 u8 device_stall_critical_watermark[0x10]; 9613 9614 u8 reserved_8[0x60]; 9615 }; 9616 9617 struct mlx5_ifc_pelc_reg_bits { 9618 u8 op[0x4]; 9619 u8 reserved_0[0x4]; 9620 u8 local_port[0x8]; 9621 u8 reserved_1[0x10]; 9622 9623 u8 op_admin[0x8]; 9624 u8 op_capability[0x8]; 9625 u8 op_request[0x8]; 9626 u8 op_active[0x8]; 9627 9628 u8 admin[0x40]; 9629 9630 u8 capability[0x40]; 9631 9632 u8 request[0x40]; 9633 9634 u8 active[0x40]; 9635 9636 u8 reserved_2[0x80]; 9637 }; 9638 9639 struct mlx5_ifc_peir_reg_bits { 9640 u8 reserved_0[0x8]; 9641 u8 local_port[0x8]; 9642 u8 reserved_1[0x10]; 9643 9644 u8 reserved_2[0xc]; 9645 u8 error_count[0x4]; 9646 u8 reserved_3[0x10]; 9647 9648 u8 reserved_4[0xc]; 9649 u8 lane[0x4]; 9650 u8 reserved_5[0x8]; 9651 u8 error_type[0x8]; 9652 }; 9653 9654 struct mlx5_ifc_qcam_access_reg_cap_mask { 9655 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 9656 u8 qpdpm[0x1]; 9657 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 9658 u8 qdpm[0x1]; 9659 u8 qpts[0x1]; 9660 u8 qcap[0x1]; 9661 u8 qcam_access_reg_cap_mask_0[0x1]; 9662 }; 9663 9664 struct mlx5_ifc_qcam_qos_feature_cap_mask { 9665 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 9666 u8 qpts_trust_both[0x1]; 9667 }; 9668 9669 struct mlx5_ifc_qcam_reg_bits { 9670 u8 reserved_at_0[0x8]; 9671 u8 feature_group[0x8]; 9672 u8 reserved_at_10[0x8]; 9673 u8 access_reg_group[0x8]; 9674 u8 reserved_at_20[0x20]; 9675 9676 union { 9677 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 9678 u8 reserved_at_0[0x80]; 9679 } qos_access_reg_cap_mask; 9680 9681 u8 reserved_at_c0[0x80]; 9682 9683 union { 9684 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 9685 u8 reserved_at_0[0x80]; 9686 } qos_feature_cap_mask; 9687 9688 u8 reserved_at_1c0[0x80]; 9689 }; 9690 9691 struct mlx5_ifc_pcam_enhanced_features_bits { 9692 u8 reserved_at_0[0x6d]; 9693 u8 rx_icrc_encapsulated_counter[0x1]; 9694 u8 reserved_at_6e[0x4]; 9695 u8 ptys_extended_ethernet[0x1]; 9696 u8 reserved_at_73[0x3]; 9697 u8 pfcc_mask[0x1]; 9698 u8 reserved_at_77[0x3]; 9699 u8 per_lane_error_counters[0x1]; 9700 u8 rx_buffer_fullness_counters[0x1]; 9701 u8 ptys_connector_type[0x1]; 9702 u8 reserved_at_7d[0x1]; 9703 u8 ppcnt_discard_group[0x1]; 9704 u8 ppcnt_statistical_group[0x1]; 9705 }; 9706 9707 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 9708 u8 port_access_reg_cap_mask_127_to_96[0x20]; 9709 u8 port_access_reg_cap_mask_95_to_64[0x20]; 9710 9711 u8 reserved_at_40[0xe]; 9712 u8 pddr[0x1]; 9713 u8 reserved_at_4f[0xd]; 9714 9715 u8 pplm[0x1]; 9716 u8 port_access_reg_cap_mask_34_to_32[0x3]; 9717 9718 u8 port_access_reg_cap_mask_31_to_13[0x13]; 9719 u8 pbmc[0x1]; 9720 u8 pptb[0x1]; 9721 u8 port_access_reg_cap_mask_10_to_09[0x2]; 9722 u8 ppcnt[0x1]; 9723 u8 port_access_reg_cap_mask_07_to_00[0x8]; 9724 }; 9725 9726 struct mlx5_ifc_pcam_reg_bits { 9727 u8 reserved_at_0[0x8]; 9728 u8 feature_group[0x8]; 9729 u8 reserved_at_10[0x8]; 9730 u8 access_reg_group[0x8]; 9731 9732 u8 reserved_at_20[0x20]; 9733 9734 union { 9735 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 9736 u8 reserved_at_0[0x80]; 9737 } port_access_reg_cap_mask; 9738 9739 u8 reserved_at_c0[0x80]; 9740 9741 union { 9742 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 9743 u8 reserved_at_0[0x80]; 9744 } feature_cap_mask; 9745 9746 u8 reserved_at_1c0[0xc0]; 9747 }; 9748 9749 struct mlx5_ifc_mcam_enhanced_features_bits { 9750 u8 reserved_at_0[0x6e]; 9751 u8 pcie_status_and_power[0x1]; 9752 u8 reserved_at_111[0x10]; 9753 u8 pcie_performance_group[0x1]; 9754 }; 9755 9756 struct mlx5_ifc_mcam_access_reg_bits { 9757 u8 reserved_at_0[0x1c]; 9758 u8 mcda[0x1]; 9759 u8 mcc[0x1]; 9760 u8 mcqi[0x1]; 9761 u8 reserved_at_1f[0x1]; 9762 9763 u8 regs_95_to_64[0x20]; 9764 u8 regs_63_to_32[0x20]; 9765 u8 regs_31_to_0[0x20]; 9766 }; 9767 9768 struct mlx5_ifc_mcam_reg_bits { 9769 u8 reserved_at_0[0x8]; 9770 u8 feature_group[0x8]; 9771 u8 reserved_at_10[0x8]; 9772 u8 access_reg_group[0x8]; 9773 9774 u8 reserved_at_20[0x20]; 9775 9776 union { 9777 struct mlx5_ifc_mcam_access_reg_bits access_regs; 9778 u8 reserved_at_0[0x80]; 9779 } mng_access_reg_cap_mask; 9780 9781 u8 reserved_at_c0[0x80]; 9782 9783 union { 9784 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 9785 u8 reserved_at_0[0x80]; 9786 } mng_feature_cap_mask; 9787 9788 u8 reserved_at_1c0[0x80]; 9789 }; 9790 9791 struct mlx5_ifc_pcap_reg_bits { 9792 u8 reserved_0[0x8]; 9793 u8 local_port[0x8]; 9794 u8 reserved_1[0x10]; 9795 9796 u8 port_capability_mask[4][0x20]; 9797 }; 9798 9799 struct mlx5_ifc_pbmc_reg_bits { 9800 u8 reserved_at_0[0x8]; 9801 u8 local_port[0x8]; 9802 u8 reserved_at_10[0x10]; 9803 9804 u8 xoff_timer_value[0x10]; 9805 u8 xoff_refresh[0x10]; 9806 9807 u8 reserved_at_40[0x9]; 9808 u8 fullness_threshold[0x7]; 9809 u8 port_buffer_size[0x10]; 9810 9811 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 9812 9813 u8 reserved_at_2e0[0x80]; 9814 }; 9815 9816 struct mlx5_ifc_paos_reg_bits { 9817 u8 swid[0x8]; 9818 u8 local_port[0x8]; 9819 u8 reserved_0[0x4]; 9820 u8 admin_status[0x4]; 9821 u8 reserved_1[0x4]; 9822 u8 oper_status[0x4]; 9823 9824 u8 ase[0x1]; 9825 u8 ee[0x1]; 9826 u8 reserved_2[0x1c]; 9827 u8 e[0x2]; 9828 9829 u8 reserved_3[0x40]; 9830 }; 9831 9832 struct mlx5_ifc_pamp_reg_bits { 9833 u8 reserved_0[0x8]; 9834 u8 opamp_group[0x8]; 9835 u8 reserved_1[0xc]; 9836 u8 opamp_group_type[0x4]; 9837 9838 u8 start_index[0x10]; 9839 u8 reserved_2[0x4]; 9840 u8 num_of_indices[0xc]; 9841 9842 u8 index_data[18][0x10]; 9843 }; 9844 9845 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits { 9846 u8 llr_rx_cells_high[0x20]; 9847 9848 u8 llr_rx_cells_low[0x20]; 9849 9850 u8 llr_rx_error_high[0x20]; 9851 9852 u8 llr_rx_error_low[0x20]; 9853 9854 u8 llr_rx_crc_error_high[0x20]; 9855 9856 u8 llr_rx_crc_error_low[0x20]; 9857 9858 u8 llr_tx_cells_high[0x20]; 9859 9860 u8 llr_tx_cells_low[0x20]; 9861 9862 u8 llr_tx_ret_cells_high[0x20]; 9863 9864 u8 llr_tx_ret_cells_low[0x20]; 9865 9866 u8 llr_tx_ret_events_high[0x20]; 9867 9868 u8 llr_tx_ret_events_low[0x20]; 9869 9870 u8 reserved_0[0x640]; 9871 }; 9872 9873 struct mlx5_ifc_mtmp_reg_bits { 9874 u8 i[0x1]; 9875 u8 reserved_at_1[0x18]; 9876 u8 sensor_index[0x7]; 9877 9878 u8 reserved_at_20[0x10]; 9879 u8 temperature[0x10]; 9880 9881 u8 mte[0x1]; 9882 u8 mtr[0x1]; 9883 u8 reserved_at_42[0x0e]; 9884 u8 max_temperature[0x10]; 9885 9886 u8 tee[0x2]; 9887 u8 reserved_at_62[0x0e]; 9888 u8 temperature_threshold_hi[0x10]; 9889 9890 u8 reserved_at_80[0x10]; 9891 u8 temperature_threshold_lo[0x10]; 9892 9893 u8 reserved_at_100[0x20]; 9894 9895 u8 sensor_name[0x40]; 9896 }; 9897 9898 struct mlx5_ifc_lane_2_module_mapping_bits { 9899 u8 reserved_0[0x6]; 9900 u8 rx_lane[0x2]; 9901 u8 reserved_1[0x6]; 9902 u8 tx_lane[0x2]; 9903 u8 reserved_2[0x8]; 9904 u8 module[0x8]; 9905 }; 9906 9907 struct mlx5_ifc_eth_per_traffic_class_layout_bits { 9908 u8 transmit_queue_high[0x20]; 9909 9910 u8 transmit_queue_low[0x20]; 9911 9912 u8 reserved_0[0x780]; 9913 }; 9914 9915 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits { 9916 u8 no_buffer_discard_uc_high[0x20]; 9917 9918 u8 no_buffer_discard_uc_low[0x20]; 9919 9920 u8 wred_discard_high[0x20]; 9921 9922 u8 wred_discard_low[0x20]; 9923 9924 u8 reserved_0[0x740]; 9925 }; 9926 9927 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 9928 u8 rx_octets_high[0x20]; 9929 9930 u8 rx_octets_low[0x20]; 9931 9932 u8 reserved_0[0xc0]; 9933 9934 u8 rx_frames_high[0x20]; 9935 9936 u8 rx_frames_low[0x20]; 9937 9938 u8 tx_octets_high[0x20]; 9939 9940 u8 tx_octets_low[0x20]; 9941 9942 u8 reserved_1[0xc0]; 9943 9944 u8 tx_frames_high[0x20]; 9945 9946 u8 tx_frames_low[0x20]; 9947 9948 u8 rx_pause_high[0x20]; 9949 9950 u8 rx_pause_low[0x20]; 9951 9952 u8 rx_pause_duration_high[0x20]; 9953 9954 u8 rx_pause_duration_low[0x20]; 9955 9956 u8 tx_pause_high[0x20]; 9957 9958 u8 tx_pause_low[0x20]; 9959 9960 u8 tx_pause_duration_high[0x20]; 9961 9962 u8 tx_pause_duration_low[0x20]; 9963 9964 u8 rx_pause_transition_high[0x20]; 9965 9966 u8 rx_pause_transition_low[0x20]; 9967 9968 u8 rx_discards_high[0x20]; 9969 9970 u8 rx_discards_low[0x20]; 9971 9972 u8 device_stall_minor_watermark_cnt_high[0x20]; 9973 9974 u8 device_stall_minor_watermark_cnt_low[0x20]; 9975 9976 u8 device_stall_critical_watermark_cnt_high[0x20]; 9977 9978 u8 device_stall_critical_watermark_cnt_low[0x20]; 9979 9980 u8 reserved_2[0x340]; 9981 }; 9982 9983 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 9984 u8 port_transmit_wait_high[0x20]; 9985 9986 u8 port_transmit_wait_low[0x20]; 9987 9988 u8 ecn_marked_high[0x20]; 9989 9990 u8 ecn_marked_low[0x20]; 9991 9992 u8 no_buffer_discard_mc_high[0x20]; 9993 9994 u8 no_buffer_discard_mc_low[0x20]; 9995 9996 u8 rx_ebp_high[0x20]; 9997 9998 u8 rx_ebp_low[0x20]; 9999 10000 u8 tx_ebp_high[0x20]; 10001 10002 u8 tx_ebp_low[0x20]; 10003 10004 u8 rx_buffer_almost_full_high[0x20]; 10005 10006 u8 rx_buffer_almost_full_low[0x20]; 10007 10008 u8 rx_buffer_full_high[0x20]; 10009 10010 u8 rx_buffer_full_low[0x20]; 10011 10012 u8 rx_icrc_encapsulated_high[0x20]; 10013 10014 u8 rx_icrc_encapsulated_low[0x20]; 10015 10016 u8 reserved_0[0x80]; 10017 10018 u8 tx_stats_pkts64octets_high[0x20]; 10019 10020 u8 tx_stats_pkts64octets_low[0x20]; 10021 10022 u8 tx_stats_pkts65to127octets_high[0x20]; 10023 10024 u8 tx_stats_pkts65to127octets_low[0x20]; 10025 10026 u8 tx_stats_pkts128to255octets_high[0x20]; 10027 10028 u8 tx_stats_pkts128to255octets_low[0x20]; 10029 10030 u8 tx_stats_pkts256to511octets_high[0x20]; 10031 10032 u8 tx_stats_pkts256to511octets_low[0x20]; 10033 10034 u8 tx_stats_pkts512to1023octets_high[0x20]; 10035 10036 u8 tx_stats_pkts512to1023octets_low[0x20]; 10037 10038 u8 tx_stats_pkts1024to1518octets_high[0x20]; 10039 10040 u8 tx_stats_pkts1024to1518octets_low[0x20]; 10041 10042 u8 tx_stats_pkts1519to2047octets_high[0x20]; 10043 10044 u8 tx_stats_pkts1519to2047octets_low[0x20]; 10045 10046 u8 tx_stats_pkts2048to4095octets_high[0x20]; 10047 10048 u8 tx_stats_pkts2048to4095octets_low[0x20]; 10049 10050 u8 tx_stats_pkts4096to8191octets_high[0x20]; 10051 10052 u8 tx_stats_pkts4096to8191octets_low[0x20]; 10053 10054 u8 tx_stats_pkts8192to10239octets_high[0x20]; 10055 10056 u8 tx_stats_pkts8192to10239octets_low[0x20]; 10057 10058 u8 reserved_1[0x2C0]; 10059 }; 10060 10061 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 10062 u8 a_frames_transmitted_ok_high[0x20]; 10063 10064 u8 a_frames_transmitted_ok_low[0x20]; 10065 10066 u8 a_frames_received_ok_high[0x20]; 10067 10068 u8 a_frames_received_ok_low[0x20]; 10069 10070 u8 a_frame_check_sequence_errors_high[0x20]; 10071 10072 u8 a_frame_check_sequence_errors_low[0x20]; 10073 10074 u8 a_alignment_errors_high[0x20]; 10075 10076 u8 a_alignment_errors_low[0x20]; 10077 10078 u8 a_octets_transmitted_ok_high[0x20]; 10079 10080 u8 a_octets_transmitted_ok_low[0x20]; 10081 10082 u8 a_octets_received_ok_high[0x20]; 10083 10084 u8 a_octets_received_ok_low[0x20]; 10085 10086 u8 a_multicast_frames_xmitted_ok_high[0x20]; 10087 10088 u8 a_multicast_frames_xmitted_ok_low[0x20]; 10089 10090 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 10091 10092 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 10093 10094 u8 a_multicast_frames_received_ok_high[0x20]; 10095 10096 u8 a_multicast_frames_received_ok_low[0x20]; 10097 10098 u8 a_broadcast_frames_recieved_ok_high[0x20]; 10099 10100 u8 a_broadcast_frames_recieved_ok_low[0x20]; 10101 10102 u8 a_in_range_length_errors_high[0x20]; 10103 10104 u8 a_in_range_length_errors_low[0x20]; 10105 10106 u8 a_out_of_range_length_field_high[0x20]; 10107 10108 u8 a_out_of_range_length_field_low[0x20]; 10109 10110 u8 a_frame_too_long_errors_high[0x20]; 10111 10112 u8 a_frame_too_long_errors_low[0x20]; 10113 10114 u8 a_symbol_error_during_carrier_high[0x20]; 10115 10116 u8 a_symbol_error_during_carrier_low[0x20]; 10117 10118 u8 a_mac_control_frames_transmitted_high[0x20]; 10119 10120 u8 a_mac_control_frames_transmitted_low[0x20]; 10121 10122 u8 a_mac_control_frames_received_high[0x20]; 10123 10124 u8 a_mac_control_frames_received_low[0x20]; 10125 10126 u8 a_unsupported_opcodes_received_high[0x20]; 10127 10128 u8 a_unsupported_opcodes_received_low[0x20]; 10129 10130 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 10131 10132 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 10133 10134 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 10135 10136 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 10137 10138 u8 reserved_0[0x300]; 10139 }; 10140 10141 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 10142 u8 dot3stats_alignment_errors_high[0x20]; 10143 10144 u8 dot3stats_alignment_errors_low[0x20]; 10145 10146 u8 dot3stats_fcs_errors_high[0x20]; 10147 10148 u8 dot3stats_fcs_errors_low[0x20]; 10149 10150 u8 dot3stats_single_collision_frames_high[0x20]; 10151 10152 u8 dot3stats_single_collision_frames_low[0x20]; 10153 10154 u8 dot3stats_multiple_collision_frames_high[0x20]; 10155 10156 u8 dot3stats_multiple_collision_frames_low[0x20]; 10157 10158 u8 dot3stats_sqe_test_errors_high[0x20]; 10159 10160 u8 dot3stats_sqe_test_errors_low[0x20]; 10161 10162 u8 dot3stats_deferred_transmissions_high[0x20]; 10163 10164 u8 dot3stats_deferred_transmissions_low[0x20]; 10165 10166 u8 dot3stats_late_collisions_high[0x20]; 10167 10168 u8 dot3stats_late_collisions_low[0x20]; 10169 10170 u8 dot3stats_excessive_collisions_high[0x20]; 10171 10172 u8 dot3stats_excessive_collisions_low[0x20]; 10173 10174 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 10175 10176 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 10177 10178 u8 dot3stats_carrier_sense_errors_high[0x20]; 10179 10180 u8 dot3stats_carrier_sense_errors_low[0x20]; 10181 10182 u8 dot3stats_frame_too_longs_high[0x20]; 10183 10184 u8 dot3stats_frame_too_longs_low[0x20]; 10185 10186 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 10187 10188 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 10189 10190 u8 dot3stats_symbol_errors_high[0x20]; 10191 10192 u8 dot3stats_symbol_errors_low[0x20]; 10193 10194 u8 dot3control_in_unknown_opcodes_high[0x20]; 10195 10196 u8 dot3control_in_unknown_opcodes_low[0x20]; 10197 10198 u8 dot3in_pause_frames_high[0x20]; 10199 10200 u8 dot3in_pause_frames_low[0x20]; 10201 10202 u8 dot3out_pause_frames_high[0x20]; 10203 10204 u8 dot3out_pause_frames_low[0x20]; 10205 10206 u8 reserved_0[0x3c0]; 10207 }; 10208 10209 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 10210 u8 if_in_octets_high[0x20]; 10211 10212 u8 if_in_octets_low[0x20]; 10213 10214 u8 if_in_ucast_pkts_high[0x20]; 10215 10216 u8 if_in_ucast_pkts_low[0x20]; 10217 10218 u8 if_in_discards_high[0x20]; 10219 10220 u8 if_in_discards_low[0x20]; 10221 10222 u8 if_in_errors_high[0x20]; 10223 10224 u8 if_in_errors_low[0x20]; 10225 10226 u8 if_in_unknown_protos_high[0x20]; 10227 10228 u8 if_in_unknown_protos_low[0x20]; 10229 10230 u8 if_out_octets_high[0x20]; 10231 10232 u8 if_out_octets_low[0x20]; 10233 10234 u8 if_out_ucast_pkts_high[0x20]; 10235 10236 u8 if_out_ucast_pkts_low[0x20]; 10237 10238 u8 if_out_discards_high[0x20]; 10239 10240 u8 if_out_discards_low[0x20]; 10241 10242 u8 if_out_errors_high[0x20]; 10243 10244 u8 if_out_errors_low[0x20]; 10245 10246 u8 if_in_multicast_pkts_high[0x20]; 10247 10248 u8 if_in_multicast_pkts_low[0x20]; 10249 10250 u8 if_in_broadcast_pkts_high[0x20]; 10251 10252 u8 if_in_broadcast_pkts_low[0x20]; 10253 10254 u8 if_out_multicast_pkts_high[0x20]; 10255 10256 u8 if_out_multicast_pkts_low[0x20]; 10257 10258 u8 if_out_broadcast_pkts_high[0x20]; 10259 10260 u8 if_out_broadcast_pkts_low[0x20]; 10261 10262 u8 reserved_0[0x480]; 10263 }; 10264 10265 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 10266 u8 ether_stats_drop_events_high[0x20]; 10267 10268 u8 ether_stats_drop_events_low[0x20]; 10269 10270 u8 ether_stats_octets_high[0x20]; 10271 10272 u8 ether_stats_octets_low[0x20]; 10273 10274 u8 ether_stats_pkts_high[0x20]; 10275 10276 u8 ether_stats_pkts_low[0x20]; 10277 10278 u8 ether_stats_broadcast_pkts_high[0x20]; 10279 10280 u8 ether_stats_broadcast_pkts_low[0x20]; 10281 10282 u8 ether_stats_multicast_pkts_high[0x20]; 10283 10284 u8 ether_stats_multicast_pkts_low[0x20]; 10285 10286 u8 ether_stats_crc_align_errors_high[0x20]; 10287 10288 u8 ether_stats_crc_align_errors_low[0x20]; 10289 10290 u8 ether_stats_undersize_pkts_high[0x20]; 10291 10292 u8 ether_stats_undersize_pkts_low[0x20]; 10293 10294 u8 ether_stats_oversize_pkts_high[0x20]; 10295 10296 u8 ether_stats_oversize_pkts_low[0x20]; 10297 10298 u8 ether_stats_fragments_high[0x20]; 10299 10300 u8 ether_stats_fragments_low[0x20]; 10301 10302 u8 ether_stats_jabbers_high[0x20]; 10303 10304 u8 ether_stats_jabbers_low[0x20]; 10305 10306 u8 ether_stats_collisions_high[0x20]; 10307 10308 u8 ether_stats_collisions_low[0x20]; 10309 10310 u8 ether_stats_pkts64octets_high[0x20]; 10311 10312 u8 ether_stats_pkts64octets_low[0x20]; 10313 10314 u8 ether_stats_pkts65to127octets_high[0x20]; 10315 10316 u8 ether_stats_pkts65to127octets_low[0x20]; 10317 10318 u8 ether_stats_pkts128to255octets_high[0x20]; 10319 10320 u8 ether_stats_pkts128to255octets_low[0x20]; 10321 10322 u8 ether_stats_pkts256to511octets_high[0x20]; 10323 10324 u8 ether_stats_pkts256to511octets_low[0x20]; 10325 10326 u8 ether_stats_pkts512to1023octets_high[0x20]; 10327 10328 u8 ether_stats_pkts512to1023octets_low[0x20]; 10329 10330 u8 ether_stats_pkts1024to1518octets_high[0x20]; 10331 10332 u8 ether_stats_pkts1024to1518octets_low[0x20]; 10333 10334 u8 ether_stats_pkts1519to2047octets_high[0x20]; 10335 10336 u8 ether_stats_pkts1519to2047octets_low[0x20]; 10337 10338 u8 ether_stats_pkts2048to4095octets_high[0x20]; 10339 10340 u8 ether_stats_pkts2048to4095octets_low[0x20]; 10341 10342 u8 ether_stats_pkts4096to8191octets_high[0x20]; 10343 10344 u8 ether_stats_pkts4096to8191octets_low[0x20]; 10345 10346 u8 ether_stats_pkts8192to10239octets_high[0x20]; 10347 10348 u8 ether_stats_pkts8192to10239octets_low[0x20]; 10349 10350 u8 reserved_0[0x280]; 10351 }; 10352 10353 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits { 10354 u8 symbol_error_counter[0x10]; 10355 u8 link_error_recovery_counter[0x8]; 10356 u8 link_downed_counter[0x8]; 10357 10358 u8 port_rcv_errors[0x10]; 10359 u8 port_rcv_remote_physical_errors[0x10]; 10360 10361 u8 port_rcv_switch_relay_errors[0x10]; 10362 u8 port_xmit_discards[0x10]; 10363 10364 u8 port_xmit_constraint_errors[0x8]; 10365 u8 port_rcv_constraint_errors[0x8]; 10366 u8 reserved_0[0x8]; 10367 u8 local_link_integrity_errors[0x4]; 10368 u8 excessive_buffer_overrun_errors[0x4]; 10369 10370 u8 reserved_1[0x10]; 10371 u8 vl_15_dropped[0x10]; 10372 10373 u8 port_xmit_data[0x20]; 10374 10375 u8 port_rcv_data[0x20]; 10376 10377 u8 port_xmit_pkts[0x20]; 10378 10379 u8 port_rcv_pkts[0x20]; 10380 10381 u8 port_xmit_wait[0x20]; 10382 10383 u8 reserved_2[0x680]; 10384 }; 10385 10386 struct mlx5_ifc_trc_tlb_reg_bits { 10387 u8 reserved_0[0x80]; 10388 10389 u8 tlb_addr[0][0x40]; 10390 }; 10391 10392 struct mlx5_ifc_trc_read_fifo_reg_bits { 10393 u8 reserved_0[0x10]; 10394 u8 requested_event_num[0x10]; 10395 10396 u8 reserved_1[0x20]; 10397 10398 u8 reserved_2[0x10]; 10399 u8 acual_event_num[0x10]; 10400 10401 u8 reserved_3[0x20]; 10402 10403 u8 event[0][0x40]; 10404 }; 10405 10406 struct mlx5_ifc_trc_lock_reg_bits { 10407 u8 reserved_0[0x1f]; 10408 u8 lock[0x1]; 10409 10410 u8 reserved_1[0x60]; 10411 }; 10412 10413 struct mlx5_ifc_trc_filter_reg_bits { 10414 u8 status[0x1]; 10415 u8 reserved_0[0xf]; 10416 u8 filter_index[0x10]; 10417 10418 u8 reserved_1[0x20]; 10419 10420 u8 filter_val[0x20]; 10421 10422 u8 reserved_2[0x1a0]; 10423 }; 10424 10425 struct mlx5_ifc_trc_event_reg_bits { 10426 u8 status[0x1]; 10427 u8 reserved_0[0xf]; 10428 u8 event_index[0x10]; 10429 10430 u8 reserved_1[0x20]; 10431 10432 u8 event_id[0x20]; 10433 10434 u8 event_selector_val[0x10]; 10435 u8 event_selector_size[0x10]; 10436 10437 u8 reserved_2[0x180]; 10438 }; 10439 10440 struct mlx5_ifc_trc_conf_reg_bits { 10441 u8 limit_en[0x1]; 10442 u8 reserved_0[0x3]; 10443 u8 dump_mode[0x4]; 10444 u8 reserved_1[0x15]; 10445 u8 state[0x3]; 10446 10447 u8 reserved_2[0x20]; 10448 10449 u8 limit_event_index[0x20]; 10450 10451 u8 mkey[0x20]; 10452 10453 u8 fifo_ready_ev_num[0x20]; 10454 10455 u8 reserved_3[0x160]; 10456 }; 10457 10458 struct mlx5_ifc_trc_cap_reg_bits { 10459 u8 reserved_0[0x18]; 10460 u8 dump_mode[0x8]; 10461 10462 u8 reserved_1[0x20]; 10463 10464 u8 num_of_events[0x10]; 10465 u8 num_of_filters[0x10]; 10466 10467 u8 fifo_size[0x20]; 10468 10469 u8 tlb_size[0x10]; 10470 u8 event_size[0x10]; 10471 10472 u8 reserved_2[0x160]; 10473 }; 10474 10475 struct mlx5_ifc_set_node_in_bits { 10476 u8 node_description[64][0x8]; 10477 }; 10478 10479 struct mlx5_ifc_register_power_settings_bits { 10480 u8 reserved_0[0x18]; 10481 u8 power_settings_level[0x8]; 10482 10483 u8 reserved_1[0x60]; 10484 }; 10485 10486 struct mlx5_ifc_register_host_endianess_bits { 10487 u8 he[0x1]; 10488 u8 reserved_0[0x1f]; 10489 10490 u8 reserved_1[0x60]; 10491 }; 10492 10493 struct mlx5_ifc_register_diag_buffer_ctrl_bits { 10494 u8 physical_address[0x40]; 10495 }; 10496 10497 struct mlx5_ifc_qtct_reg_bits { 10498 u8 operation_type[0x2]; 10499 u8 cap_local_admin[0x1]; 10500 u8 cap_remote_admin[0x1]; 10501 u8 reserved_0[0x4]; 10502 u8 port_number[0x8]; 10503 u8 reserved_1[0xd]; 10504 u8 prio[0x3]; 10505 10506 u8 reserved_2[0x1d]; 10507 u8 tclass[0x3]; 10508 }; 10509 10510 struct mlx5_ifc_qpdp_reg_bits { 10511 u8 reserved_0[0x8]; 10512 u8 port_number[0x8]; 10513 u8 reserved_1[0x10]; 10514 10515 u8 reserved_2[0x1d]; 10516 u8 pprio[0x3]; 10517 }; 10518 10519 struct mlx5_ifc_port_info_ro_fields_param_bits { 10520 u8 reserved_0[0x8]; 10521 u8 port[0x8]; 10522 u8 max_gid[0x10]; 10523 10524 u8 reserved_1[0x20]; 10525 10526 u8 port_guid[0x40]; 10527 }; 10528 10529 struct mlx5_ifc_nvqc_reg_bits { 10530 u8 type[0x20]; 10531 10532 u8 reserved_0[0x18]; 10533 u8 version[0x4]; 10534 u8 reserved_1[0x2]; 10535 u8 support_wr[0x1]; 10536 u8 support_rd[0x1]; 10537 }; 10538 10539 struct mlx5_ifc_nvia_reg_bits { 10540 u8 reserved_0[0x1d]; 10541 u8 target[0x3]; 10542 10543 u8 reserved_1[0x20]; 10544 }; 10545 10546 struct mlx5_ifc_nvdi_reg_bits { 10547 struct mlx5_ifc_config_item_bits configuration_item_header; 10548 }; 10549 10550 struct mlx5_ifc_nvda_reg_bits { 10551 struct mlx5_ifc_config_item_bits configuration_item_header; 10552 10553 u8 configuration_item_data[0x20]; 10554 }; 10555 10556 struct mlx5_ifc_node_info_ro_fields_param_bits { 10557 u8 system_image_guid[0x40]; 10558 10559 u8 reserved_0[0x40]; 10560 10561 u8 node_guid[0x40]; 10562 10563 u8 reserved_1[0x10]; 10564 u8 max_pkey[0x10]; 10565 10566 u8 reserved_2[0x20]; 10567 }; 10568 10569 struct mlx5_ifc_ets_tcn_config_reg_bits { 10570 u8 g[0x1]; 10571 u8 b[0x1]; 10572 u8 r[0x1]; 10573 u8 reserved_0[0x9]; 10574 u8 group[0x4]; 10575 u8 reserved_1[0x9]; 10576 u8 bw_allocation[0x7]; 10577 10578 u8 reserved_2[0xc]; 10579 u8 max_bw_units[0x4]; 10580 u8 reserved_3[0x8]; 10581 u8 max_bw_value[0x8]; 10582 }; 10583 10584 struct mlx5_ifc_ets_global_config_reg_bits { 10585 u8 reserved_0[0x2]; 10586 u8 r[0x1]; 10587 u8 reserved_1[0x1d]; 10588 10589 u8 reserved_2[0xc]; 10590 u8 max_bw_units[0x4]; 10591 u8 reserved_3[0x8]; 10592 u8 max_bw_value[0x8]; 10593 }; 10594 10595 struct mlx5_ifc_qetc_reg_bits { 10596 u8 reserved_at_0[0x8]; 10597 u8 port_number[0x8]; 10598 u8 reserved_at_10[0x30]; 10599 10600 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 10601 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 10602 }; 10603 10604 struct mlx5_ifc_nodnic_mac_filters_bits { 10605 struct mlx5_ifc_mac_address_layout_bits mac_filter0; 10606 10607 struct mlx5_ifc_mac_address_layout_bits mac_filter1; 10608 10609 struct mlx5_ifc_mac_address_layout_bits mac_filter2; 10610 10611 struct mlx5_ifc_mac_address_layout_bits mac_filter3; 10612 10613 struct mlx5_ifc_mac_address_layout_bits mac_filter4; 10614 10615 u8 reserved_0[0xc0]; 10616 }; 10617 10618 struct mlx5_ifc_nodnic_gid_filters_bits { 10619 u8 mgid_filter0[16][0x8]; 10620 10621 u8 mgid_filter1[16][0x8]; 10622 10623 u8 mgid_filter2[16][0x8]; 10624 10625 u8 mgid_filter3[16][0x8]; 10626 }; 10627 10628 enum { 10629 MLX5_NODNIC_CONFIG_REG_NUM_PORTS_SINGLE_PORT = 0x0, 10630 MLX5_NODNIC_CONFIG_REG_NUM_PORTS_DUAL_PORT = 0x1, 10631 }; 10632 10633 enum { 10634 MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_LEGACY_CQE = 0x0, 10635 MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_NEW_CQE = 0x1, 10636 }; 10637 10638 struct mlx5_ifc_nodnic_config_reg_bits { 10639 u8 no_dram_nic_revision[0x8]; 10640 u8 hardware_format[0x8]; 10641 u8 support_receive_filter[0x1]; 10642 u8 support_promisc_filter[0x1]; 10643 u8 support_promisc_multicast_filter[0x1]; 10644 u8 reserved_0[0x2]; 10645 u8 log_working_buffer_size[0x3]; 10646 u8 log_pkey_table_size[0x4]; 10647 u8 reserved_1[0x3]; 10648 u8 num_ports[0x1]; 10649 10650 u8 reserved_2[0x2]; 10651 u8 log_max_ring_size[0x6]; 10652 u8 reserved_3[0x18]; 10653 10654 u8 lkey[0x20]; 10655 10656 u8 cqe_format[0x4]; 10657 u8 reserved_4[0x1c]; 10658 10659 u8 node_guid[0x40]; 10660 10661 u8 reserved_5[0x740]; 10662 10663 struct mlx5_ifc_nodnic_port_config_reg_bits port1_settings; 10664 10665 struct mlx5_ifc_nodnic_port_config_reg_bits port2_settings; 10666 }; 10667 10668 struct mlx5_ifc_vlan_layout_bits { 10669 u8 reserved_0[0x14]; 10670 u8 vlan[0xc]; 10671 10672 u8 reserved_1[0x20]; 10673 }; 10674 10675 struct mlx5_ifc_umr_pointer_desc_argument_bits { 10676 u8 reserved_0[0x20]; 10677 10678 u8 mkey[0x20]; 10679 10680 u8 addressh_63_32[0x20]; 10681 10682 u8 addressl_31_0[0x20]; 10683 }; 10684 10685 struct mlx5_ifc_ud_adrs_vector_bits { 10686 u8 dc_key[0x40]; 10687 10688 u8 ext[0x1]; 10689 u8 reserved_0[0x7]; 10690 u8 destination_qp_dct[0x18]; 10691 10692 u8 static_rate[0x4]; 10693 u8 sl_eth_prio[0x4]; 10694 u8 fl[0x1]; 10695 u8 mlid[0x7]; 10696 u8 rlid_udp_sport[0x10]; 10697 10698 u8 reserved_1[0x20]; 10699 10700 u8 rmac_47_16[0x20]; 10701 10702 u8 rmac_15_0[0x10]; 10703 u8 tclass[0x8]; 10704 u8 hop_limit[0x8]; 10705 10706 u8 reserved_2[0x1]; 10707 u8 grh[0x1]; 10708 u8 reserved_3[0x2]; 10709 u8 src_addr_index[0x8]; 10710 u8 flow_label[0x14]; 10711 10712 u8 rgid_rip[16][0x8]; 10713 }; 10714 10715 struct mlx5_ifc_port_module_event_bits { 10716 u8 reserved_0[0x8]; 10717 u8 module[0x8]; 10718 u8 reserved_1[0xc]; 10719 u8 module_status[0x4]; 10720 10721 u8 reserved_2[0x14]; 10722 u8 error_type[0x4]; 10723 u8 reserved_3[0x8]; 10724 10725 u8 reserved_4[0xa0]; 10726 }; 10727 10728 struct mlx5_ifc_icmd_control_bits { 10729 u8 opcode[0x10]; 10730 u8 status[0x8]; 10731 u8 reserved_0[0x7]; 10732 u8 busy[0x1]; 10733 }; 10734 10735 struct mlx5_ifc_eqe_bits { 10736 u8 reserved_0[0x8]; 10737 u8 event_type[0x8]; 10738 u8 reserved_1[0x8]; 10739 u8 event_sub_type[0x8]; 10740 10741 u8 reserved_2[0xe0]; 10742 10743 union mlx5_ifc_event_auto_bits event_data; 10744 10745 u8 reserved_3[0x10]; 10746 u8 signature[0x8]; 10747 u8 reserved_4[0x7]; 10748 u8 owner[0x1]; 10749 }; 10750 10751 enum { 10752 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10753 }; 10754 10755 struct mlx5_ifc_cmd_queue_entry_bits { 10756 u8 type[0x8]; 10757 u8 reserved_0[0x18]; 10758 10759 u8 input_length[0x20]; 10760 10761 u8 input_mailbox_pointer_63_32[0x20]; 10762 10763 u8 input_mailbox_pointer_31_9[0x17]; 10764 u8 reserved_1[0x9]; 10765 10766 u8 command_input_inline_data[16][0x8]; 10767 10768 u8 command_output_inline_data[16][0x8]; 10769 10770 u8 output_mailbox_pointer_63_32[0x20]; 10771 10772 u8 output_mailbox_pointer_31_9[0x17]; 10773 u8 reserved_2[0x9]; 10774 10775 u8 output_length[0x20]; 10776 10777 u8 token[0x8]; 10778 u8 signature[0x8]; 10779 u8 reserved_3[0x8]; 10780 u8 status[0x7]; 10781 u8 ownership[0x1]; 10782 }; 10783 10784 struct mlx5_ifc_cmd_out_bits { 10785 u8 status[0x8]; 10786 u8 reserved_0[0x18]; 10787 10788 u8 syndrome[0x20]; 10789 10790 u8 command_output[0x20]; 10791 }; 10792 10793 struct mlx5_ifc_cmd_in_bits { 10794 u8 opcode[0x10]; 10795 u8 reserved_0[0x10]; 10796 10797 u8 reserved_1[0x10]; 10798 u8 op_mod[0x10]; 10799 10800 u8 command[0][0x20]; 10801 }; 10802 10803 struct mlx5_ifc_cmd_if_box_bits { 10804 u8 mailbox_data[512][0x8]; 10805 10806 u8 reserved_0[0x180]; 10807 10808 u8 next_pointer_63_32[0x20]; 10809 10810 u8 next_pointer_31_10[0x16]; 10811 u8 reserved_1[0xa]; 10812 10813 u8 block_number[0x20]; 10814 10815 u8 reserved_2[0x8]; 10816 u8 token[0x8]; 10817 u8 ctrl_signature[0x8]; 10818 u8 signature[0x8]; 10819 }; 10820 10821 struct mlx5_ifc_mtt_bits { 10822 u8 ptag_63_32[0x20]; 10823 10824 u8 ptag_31_8[0x18]; 10825 u8 reserved_0[0x6]; 10826 u8 wr_en[0x1]; 10827 u8 rd_en[0x1]; 10828 }; 10829 10830 struct mlx5_ifc_tls_progress_params_bits { 10831 u8 valid[0x1]; 10832 u8 reserved_at_1[0x7]; 10833 u8 pd[0x18]; 10834 10835 u8 next_record_tcp_sn[0x20]; 10836 10837 u8 hw_resync_tcp_sn[0x20]; 10838 10839 u8 record_tracker_state[0x2]; 10840 u8 auth_state[0x2]; 10841 u8 reserved_at_64[0x4]; 10842 u8 hw_offset_record_number[0x18]; 10843 }; 10844 10845 struct mlx5_ifc_tls_static_params_bits { 10846 u8 const_2[0x2]; 10847 u8 tls_version[0x4]; 10848 u8 const_1[0x2]; 10849 u8 reserved_at_8[0x14]; 10850 u8 encryption_standard[0x4]; 10851 10852 u8 reserved_at_20[0x20]; 10853 10854 u8 initial_record_number[0x40]; 10855 10856 u8 resync_tcp_sn[0x20]; 10857 10858 u8 gcm_iv[0x20]; 10859 10860 u8 implicit_iv[0x40]; 10861 10862 u8 reserved_at_100[0x8]; 10863 u8 dek_index[0x18]; 10864 10865 u8 reserved_at_120[0xe0]; 10866 }; 10867 10868 /* Vendor Specific Capabilities, VSC */ 10869 enum { 10870 MLX5_VSC_DOMAIN_ICMD = 0x1, 10871 MLX5_VSC_DOMAIN_PROTECTED_CRSPACE = 0x6, 10872 MLX5_VSC_DOMAIN_SCAN_CRSPACE = 0x7, 10873 MLX5_VSC_DOMAIN_SEMAPHORES = 0xA, 10874 }; 10875 10876 struct mlx5_ifc_vendor_specific_cap_bits { 10877 u8 type[0x8]; 10878 u8 length[0x8]; 10879 u8 next_pointer[0x8]; 10880 u8 capability_id[0x8]; 10881 10882 u8 status[0x3]; 10883 u8 reserved_0[0xd]; 10884 u8 space[0x10]; 10885 10886 u8 counter[0x20]; 10887 10888 u8 semaphore[0x20]; 10889 10890 u8 flag[0x1]; 10891 u8 reserved_1[0x1]; 10892 u8 address[0x1e]; 10893 10894 u8 data[0x20]; 10895 }; 10896 10897 struct mlx5_ifc_vsc_space_bits { 10898 u8 status[0x3]; 10899 u8 reserved0[0xd]; 10900 u8 space[0x10]; 10901 }; 10902 10903 struct mlx5_ifc_vsc_addr_bits { 10904 u8 flag[0x1]; 10905 u8 reserved0[0x1]; 10906 u8 address[0x1e]; 10907 }; 10908 10909 enum { 10910 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10911 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10912 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10913 }; 10914 10915 enum { 10916 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10917 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10918 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10919 }; 10920 10921 enum { 10922 MLX5_HEALTH_SYNDR_FW_ERR = 0x1, 10923 MLX5_HEALTH_SYNDR_IRISC_ERR = 0x7, 10924 MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR = 0x8, 10925 MLX5_HEALTH_SYNDR_CRC_ERR = 0x9, 10926 MLX5_HEALTH_SYNDR_FETCH_PCI_ERR = 0xa, 10927 MLX5_HEALTH_SYNDR_HW_FTL_ERR = 0xb, 10928 MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR = 0xc, 10929 MLX5_HEALTH_SYNDR_EQ_ERR = 0xd, 10930 MLX5_HEALTH_SYNDR_EQ_INV = 0xe, 10931 MLX5_HEALTH_SYNDR_FFSER_ERR = 0xf, 10932 MLX5_HEALTH_SYNDR_HIGH_TEMP = 0x10, 10933 }; 10934 10935 struct mlx5_ifc_initial_seg_bits { 10936 u8 fw_rev_minor[0x10]; 10937 u8 fw_rev_major[0x10]; 10938 10939 u8 cmd_interface_rev[0x10]; 10940 u8 fw_rev_subminor[0x10]; 10941 10942 u8 reserved_0[0x40]; 10943 10944 u8 cmdq_phy_addr_63_32[0x20]; 10945 10946 u8 cmdq_phy_addr_31_12[0x14]; 10947 u8 reserved_1[0x2]; 10948 u8 nic_interface[0x2]; 10949 u8 log_cmdq_size[0x4]; 10950 u8 log_cmdq_stride[0x4]; 10951 10952 u8 command_doorbell_vector[0x20]; 10953 10954 u8 reserved_2[0xf00]; 10955 10956 u8 initializing[0x1]; 10957 u8 reserved_3[0x4]; 10958 u8 nic_interface_supported[0x3]; 10959 u8 reserved_4[0x18]; 10960 10961 struct mlx5_ifc_health_buffer_bits health_buffer; 10962 10963 u8 no_dram_nic_offset[0x20]; 10964 10965 u8 reserved_5[0x6de0]; 10966 10967 u8 internal_timer_h[0x20]; 10968 10969 u8 internal_timer_l[0x20]; 10970 10971 u8 reserved_6[0x20]; 10972 10973 u8 reserved_7[0x1f]; 10974 u8 clear_int[0x1]; 10975 10976 u8 health_syndrome[0x8]; 10977 u8 health_counter[0x18]; 10978 10979 u8 reserved_8[0x17fc0]; 10980 }; 10981 10982 union mlx5_ifc_icmd_interface_document_bits { 10983 struct mlx5_ifc_fw_version_bits fw_version; 10984 struct mlx5_ifc_icmd_access_reg_in_bits icmd_access_reg_in; 10985 struct mlx5_ifc_icmd_access_reg_out_bits icmd_access_reg_out; 10986 struct mlx5_ifc_icmd_init_ocsd_in_bits icmd_init_ocsd_in; 10987 struct mlx5_ifc_icmd_ocbb_init_in_bits icmd_ocbb_init_in; 10988 struct mlx5_ifc_icmd_ocbb_query_etoc_stats_out_bits icmd_ocbb_query_etoc_stats_out; 10989 struct mlx5_ifc_icmd_ocbb_query_header_stats_out_bits icmd_ocbb_query_header_stats_out; 10990 struct mlx5_ifc_icmd_query_cap_general_bits icmd_query_cap_general; 10991 struct mlx5_ifc_icmd_query_cap_in_bits icmd_query_cap_in; 10992 struct mlx5_ifc_icmd_query_fw_info_out_bits icmd_query_fw_info_out; 10993 struct mlx5_ifc_icmd_query_virtual_mac_out_bits icmd_query_virtual_mac_out; 10994 struct mlx5_ifc_icmd_set_virtual_mac_in_bits icmd_set_virtual_mac_in; 10995 struct mlx5_ifc_icmd_set_wol_rol_in_bits icmd_set_wol_rol_in; 10996 struct mlx5_ifc_icmd_set_wol_rol_out_bits icmd_set_wol_rol_out; 10997 u8 reserved_0[0x42c0]; 10998 }; 10999 11000 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 11001 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 11002 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 11003 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 11004 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 11005 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 11006 struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp; 11007 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 11008 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 11009 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 11010 struct mlx5_ifc_infiniband_port_cntrs_bits infiniband_port_cntrs; 11011 u8 reserved_0[0x7c0]; 11012 }; 11013 11014 struct mlx5_ifc_ppcnt_reg_bits { 11015 u8 swid[0x8]; 11016 u8 local_port[0x8]; 11017 u8 pnat[0x2]; 11018 u8 reserved_0[0x8]; 11019 u8 grp[0x6]; 11020 11021 u8 clr[0x1]; 11022 u8 reserved_1[0x1c]; 11023 u8 prio_tc[0x3]; 11024 11025 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 11026 }; 11027 11028 struct mlx5_ifc_pcie_lanes_counters_bits { 11029 u8 life_time_counter_high[0x20]; 11030 11031 u8 life_time_counter_low[0x20]; 11032 11033 u8 error_counter_lane0[0x20]; 11034 11035 u8 error_counter_lane1[0x20]; 11036 11037 u8 error_counter_lane2[0x20]; 11038 11039 u8 error_counter_lane3[0x20]; 11040 11041 u8 error_counter_lane4[0x20]; 11042 11043 u8 error_counter_lane5[0x20]; 11044 11045 u8 error_counter_lane6[0x20]; 11046 11047 u8 error_counter_lane7[0x20]; 11048 11049 u8 error_counter_lane8[0x20]; 11050 11051 u8 error_counter_lane9[0x20]; 11052 11053 u8 error_counter_lane10[0x20]; 11054 11055 u8 error_counter_lane11[0x20]; 11056 11057 u8 error_counter_lane12[0x20]; 11058 11059 u8 error_counter_lane13[0x20]; 11060 11061 u8 error_counter_lane14[0x20]; 11062 11063 u8 error_counter_lane15[0x20]; 11064 11065 u8 reserved_at_240[0x580]; 11066 }; 11067 11068 struct mlx5_ifc_pcie_lanes_counters_ext_bits { 11069 u8 reserved_at_0[0x40]; 11070 11071 u8 error_counter_lane0[0x20]; 11072 11073 u8 error_counter_lane1[0x20]; 11074 11075 u8 error_counter_lane2[0x20]; 11076 11077 u8 error_counter_lane3[0x20]; 11078 11079 u8 error_counter_lane4[0x20]; 11080 11081 u8 error_counter_lane5[0x20]; 11082 11083 u8 error_counter_lane6[0x20]; 11084 11085 u8 error_counter_lane7[0x20]; 11086 11087 u8 error_counter_lane8[0x20]; 11088 11089 u8 error_counter_lane9[0x20]; 11090 11091 u8 error_counter_lane10[0x20]; 11092 11093 u8 error_counter_lane11[0x20]; 11094 11095 u8 error_counter_lane12[0x20]; 11096 11097 u8 error_counter_lane13[0x20]; 11098 11099 u8 error_counter_lane14[0x20]; 11100 11101 u8 error_counter_lane15[0x20]; 11102 11103 u8 reserved_at_240[0x580]; 11104 }; 11105 11106 struct mlx5_ifc_pcie_perf_counters_bits { 11107 u8 life_time_counter_high[0x20]; 11108 11109 u8 life_time_counter_low[0x20]; 11110 11111 u8 rx_errors[0x20]; 11112 11113 u8 tx_errors[0x20]; 11114 11115 u8 l0_to_recovery_eieos[0x20]; 11116 11117 u8 l0_to_recovery_ts[0x20]; 11118 11119 u8 l0_to_recovery_framing[0x20]; 11120 11121 u8 l0_to_recovery_retrain[0x20]; 11122 11123 u8 crc_error_dllp[0x20]; 11124 11125 u8 crc_error_tlp[0x20]; 11126 11127 u8 tx_overflow_buffer_pkt[0x40]; 11128 11129 u8 outbound_stalled_reads[0x20]; 11130 11131 u8 outbound_stalled_writes[0x20]; 11132 11133 u8 outbound_stalled_reads_events[0x20]; 11134 11135 u8 outbound_stalled_writes_events[0x20]; 11136 11137 u8 tx_overflow_buffer_marked_pkt[0x40]; 11138 11139 u8 reserved_at_240[0x580]; 11140 }; 11141 11142 struct mlx5_ifc_pcie_perf_counters_ext_bits { 11143 u8 reserved_at_0[0x40]; 11144 11145 u8 rx_errors[0x20]; 11146 11147 u8 tx_errors[0x20]; 11148 11149 u8 reserved_at_80[0xc0]; 11150 11151 u8 tx_overflow_buffer_pkt[0x40]; 11152 11153 u8 outbound_stalled_reads[0x20]; 11154 11155 u8 outbound_stalled_writes[0x20]; 11156 11157 u8 outbound_stalled_reads_events[0x20]; 11158 11159 u8 outbound_stalled_writes_events[0x20]; 11160 11161 u8 tx_overflow_buffer_marked_pkt[0x40]; 11162 11163 u8 reserved_at_240[0x580]; 11164 }; 11165 11166 struct mlx5_ifc_pcie_timers_states_bits { 11167 u8 life_time_counter_high[0x20]; 11168 11169 u8 life_time_counter_low[0x20]; 11170 11171 u8 time_to_boot_image_start[0x20]; 11172 11173 u8 time_to_link_image[0x20]; 11174 11175 u8 calibration_time[0x20]; 11176 11177 u8 time_to_first_perst[0x20]; 11178 11179 u8 time_to_detect_state[0x20]; 11180 11181 u8 time_to_l0[0x20]; 11182 11183 u8 time_to_crs_en[0x20]; 11184 11185 u8 time_to_plastic_image_start[0x20]; 11186 11187 u8 time_to_iron_image_start[0x20]; 11188 11189 u8 perst_handler[0x20]; 11190 11191 u8 times_in_l1[0x20]; 11192 11193 u8 times_in_l23[0x20]; 11194 11195 u8 dl_down[0x20]; 11196 11197 u8 config_cycle1usec[0x20]; 11198 11199 u8 config_cycle2to7usec[0x20]; 11200 11201 u8 config_cycle8to15usec[0x20]; 11202 11203 u8 config_cycle16to63usec[0x20]; 11204 11205 u8 config_cycle64usec[0x20]; 11206 11207 u8 correctable_err_msg_sent[0x20]; 11208 11209 u8 non_fatal_err_msg_sent[0x20]; 11210 11211 u8 fatal_err_msg_sent[0x20]; 11212 11213 u8 reserved_at_2e0[0x4e0]; 11214 }; 11215 11216 struct mlx5_ifc_pcie_timers_states_ext_bits { 11217 u8 reserved_at_0[0x40]; 11218 11219 u8 time_to_boot_image_start[0x20]; 11220 11221 u8 time_to_link_image[0x20]; 11222 11223 u8 calibration_time[0x20]; 11224 11225 u8 time_to_first_perst[0x20]; 11226 11227 u8 time_to_detect_state[0x20]; 11228 11229 u8 time_to_l0[0x20]; 11230 11231 u8 time_to_crs_en[0x20]; 11232 11233 u8 time_to_plastic_image_start[0x20]; 11234 11235 u8 time_to_iron_image_start[0x20]; 11236 11237 u8 perst_handler[0x20]; 11238 11239 u8 times_in_l1[0x20]; 11240 11241 u8 times_in_l23[0x20]; 11242 11243 u8 dl_down[0x20]; 11244 11245 u8 config_cycle1usec[0x20]; 11246 11247 u8 config_cycle2to7usec[0x20]; 11248 11249 u8 config_cycle8to15usec[0x20]; 11250 11251 u8 config_cycle16to63usec[0x20]; 11252 11253 u8 config_cycle64usec[0x20]; 11254 11255 u8 correctable_err_msg_sent[0x20]; 11256 11257 u8 non_fatal_err_msg_sent[0x20]; 11258 11259 u8 fatal_err_msg_sent[0x20]; 11260 11261 u8 reserved_at_2e0[0x4e0]; 11262 }; 11263 11264 union mlx5_ifc_mpcnt_reg_counter_set_auto_bits { 11265 struct mlx5_ifc_pcie_perf_counters_bits pcie_perf_counters; 11266 struct mlx5_ifc_pcie_lanes_counters_bits pcie_lanes_counters; 11267 struct mlx5_ifc_pcie_timers_states_bits pcie_timers_states; 11268 u8 reserved_at_0[0x7c0]; 11269 }; 11270 11271 union mlx5_ifc_mpcnt_reg_counter_set_auto_ext_bits { 11272 struct mlx5_ifc_pcie_perf_counters_ext_bits pcie_perf_counters_ext; 11273 struct mlx5_ifc_pcie_lanes_counters_ext_bits pcie_lanes_counters_ext; 11274 struct mlx5_ifc_pcie_timers_states_ext_bits pcie_timers_states_ext; 11275 u8 reserved_at_0[0x7c0]; 11276 }; 11277 11278 struct mlx5_ifc_mpcnt_reg_bits { 11279 u8 reserved_at_0[0x2]; 11280 u8 depth[0x6]; 11281 u8 pcie_index[0x8]; 11282 u8 node[0x8]; 11283 u8 reserved_at_18[0x2]; 11284 u8 grp[0x6]; 11285 11286 u8 clr[0x1]; 11287 u8 reserved_at_21[0x1f]; 11288 11289 union mlx5_ifc_mpcnt_reg_counter_set_auto_bits counter_set; 11290 }; 11291 11292 struct mlx5_ifc_mpcnt_reg_ext_bits { 11293 u8 reserved_at_0[0x2]; 11294 u8 depth[0x6]; 11295 u8 pcie_index[0x8]; 11296 u8 node[0x8]; 11297 u8 reserved_at_18[0x2]; 11298 u8 grp[0x6]; 11299 11300 u8 clr[0x1]; 11301 u8 reserved_at_21[0x1f]; 11302 11303 union mlx5_ifc_mpcnt_reg_counter_set_auto_ext_bits counter_set; 11304 }; 11305 11306 struct mlx5_ifc_monitor_opcodes_layout_bits { 11307 u8 reserved_at_0[0x10]; 11308 u8 monitor_opcode[0x10]; 11309 }; 11310 11311 union mlx5_ifc_pddr_status_opcode_bits { 11312 struct mlx5_ifc_monitor_opcodes_layout_bits monitor_opcodes; 11313 u8 reserved_at_0[0x20]; 11314 }; 11315 11316 struct mlx5_ifc_troubleshooting_info_page_layout_bits { 11317 u8 reserved_at_0[0x10]; 11318 u8 group_opcode[0x10]; 11319 11320 union mlx5_ifc_pddr_status_opcode_bits status_opcode; 11321 11322 u8 user_feedback_data[0x10]; 11323 u8 user_feedback_index[0x10]; 11324 11325 u8 status_message[0x760]; 11326 }; 11327 11328 union mlx5_ifc_pddr_page_data_bits { 11329 struct mlx5_ifc_troubleshooting_info_page_layout_bits troubleshooting_info_page; 11330 struct mlx5_ifc_pddr_module_info_bits pddr_module_info; 11331 u8 reserved_at_0[0x7c0]; 11332 }; 11333 11334 struct mlx5_ifc_pddr_reg_bits { 11335 u8 reserved_at_0[0x8]; 11336 u8 local_port[0x8]; 11337 u8 pnat[0x2]; 11338 u8 reserved_at_12[0xe]; 11339 11340 u8 reserved_at_20[0x18]; 11341 u8 page_select[0x8]; 11342 11343 union mlx5_ifc_pddr_page_data_bits page_data; 11344 }; 11345 11346 enum { 11347 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MPEIN = 0x9050, 11348 MLX5_MPEIN_PWR_STATUS_INVALID = 0, 11349 MLX5_MPEIN_PWR_STATUS_SUFFICIENT = 1, 11350 MLX5_MPEIN_PWR_STATUS_INSUFFICIENT = 2, 11351 }; 11352 11353 struct mlx5_ifc_mpein_reg_bits { 11354 u8 reserved_at_0[0x2]; 11355 u8 depth[0x6]; 11356 u8 pcie_index[0x8]; 11357 u8 node[0x8]; 11358 u8 reserved_at_18[0x8]; 11359 11360 u8 capability_mask[0x20]; 11361 11362 u8 reserved_at_40[0x8]; 11363 u8 link_width_enabled[0x8]; 11364 u8 link_speed_enabled[0x10]; 11365 11366 u8 lane0_physical_position[0x8]; 11367 u8 link_width_active[0x8]; 11368 u8 link_speed_active[0x10]; 11369 11370 u8 num_of_pfs[0x10]; 11371 u8 num_of_vfs[0x10]; 11372 11373 u8 bdf0[0x10]; 11374 u8 reserved_at_b0[0x10]; 11375 11376 u8 max_read_request_size[0x4]; 11377 u8 max_payload_size[0x4]; 11378 u8 reserved_at_c8[0x5]; 11379 u8 pwr_status[0x3]; 11380 u8 port_type[0x4]; 11381 u8 reserved_at_d4[0xb]; 11382 u8 lane_reversal[0x1]; 11383 11384 u8 reserved_at_e0[0x14]; 11385 u8 pci_power[0xc]; 11386 11387 u8 reserved_at_100[0x20]; 11388 11389 u8 device_status[0x10]; 11390 u8 port_state[0x8]; 11391 u8 reserved_at_138[0x8]; 11392 11393 u8 reserved_at_140[0x10]; 11394 u8 receiver_detect_result[0x10]; 11395 11396 u8 reserved_at_160[0x20]; 11397 }; 11398 11399 struct mlx5_ifc_mpein_reg_ext_bits { 11400 u8 reserved_at_0[0x2]; 11401 u8 depth[0x6]; 11402 u8 pcie_index[0x8]; 11403 u8 node[0x8]; 11404 u8 reserved_at_18[0x8]; 11405 11406 u8 reserved_at_20[0x20]; 11407 11408 u8 reserved_at_40[0x8]; 11409 u8 link_width_enabled[0x8]; 11410 u8 link_speed_enabled[0x10]; 11411 11412 u8 lane0_physical_position[0x8]; 11413 u8 link_width_active[0x8]; 11414 u8 link_speed_active[0x10]; 11415 11416 u8 num_of_pfs[0x10]; 11417 u8 num_of_vfs[0x10]; 11418 11419 u8 bdf0[0x10]; 11420 u8 reserved_at_b0[0x10]; 11421 11422 u8 max_read_request_size[0x4]; 11423 u8 max_payload_size[0x4]; 11424 u8 reserved_at_c8[0x5]; 11425 u8 pwr_status[0x3]; 11426 u8 port_type[0x4]; 11427 u8 reserved_at_d4[0xb]; 11428 u8 lane_reversal[0x1]; 11429 }; 11430 11431 struct mlx5_ifc_mcqi_cap_bits { 11432 u8 supported_info_bitmask[0x20]; 11433 11434 u8 component_size[0x20]; 11435 11436 u8 max_component_size[0x20]; 11437 11438 u8 log_mcda_word_size[0x4]; 11439 u8 reserved_at_64[0xc]; 11440 u8 mcda_max_write_size[0x10]; 11441 11442 u8 rd_en[0x1]; 11443 u8 reserved_at_81[0x1]; 11444 u8 match_chip_id[0x1]; 11445 u8 match_psid[0x1]; 11446 u8 check_user_timestamp[0x1]; 11447 u8 match_base_guid_mac[0x1]; 11448 u8 reserved_at_86[0x1a]; 11449 }; 11450 11451 struct mlx5_ifc_mcqi_reg_bits { 11452 u8 read_pending_component[0x1]; 11453 u8 reserved_at_1[0xf]; 11454 u8 component_index[0x10]; 11455 11456 u8 reserved_at_20[0x20]; 11457 11458 u8 reserved_at_40[0x1b]; 11459 u8 info_type[0x5]; 11460 11461 u8 info_size[0x20]; 11462 11463 u8 offset[0x20]; 11464 11465 u8 reserved_at_a0[0x10]; 11466 u8 data_size[0x10]; 11467 11468 u8 data[0][0x20]; 11469 }; 11470 11471 struct mlx5_ifc_mcc_reg_bits { 11472 u8 reserved_at_0[0x4]; 11473 u8 time_elapsed_since_last_cmd[0xc]; 11474 u8 reserved_at_10[0x8]; 11475 u8 instruction[0x8]; 11476 11477 u8 reserved_at_20[0x10]; 11478 u8 component_index[0x10]; 11479 11480 u8 reserved_at_40[0x8]; 11481 u8 update_handle[0x18]; 11482 11483 u8 handle_owner_type[0x4]; 11484 u8 handle_owner_host_id[0x4]; 11485 u8 reserved_at_68[0x1]; 11486 u8 control_progress[0x7]; 11487 u8 error_code[0x8]; 11488 u8 reserved_at_78[0x4]; 11489 u8 control_state[0x4]; 11490 11491 u8 component_size[0x20]; 11492 11493 u8 reserved_at_a0[0x60]; 11494 }; 11495 11496 struct mlx5_ifc_mcda_reg_bits { 11497 u8 reserved_at_0[0x8]; 11498 u8 update_handle[0x18]; 11499 11500 u8 offset[0x20]; 11501 11502 u8 reserved_at_40[0x10]; 11503 u8 size[0x10]; 11504 11505 u8 reserved_at_60[0x20]; 11506 11507 u8 data[0][0x20]; 11508 }; 11509 11510 union mlx5_ifc_ports_control_registers_document_bits { 11511 struct mlx5_ifc_ib_portcntrs_attribute_grp_data_bits ib_portcntrs_attribute_grp_data; 11512 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 11513 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 11514 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 11515 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 11516 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 11517 struct mlx5_ifc_eth_discard_cntrs_grp_bits eth_discard_cntrs_grp; 11518 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 11519 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 11520 struct mlx5_ifc_eth_per_traffic_class_cong_layout_bits eth_per_traffic_class_cong_layout; 11521 struct mlx5_ifc_eth_per_traffic_class_layout_bits eth_per_traffic_class_layout; 11522 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 11523 struct mlx5_ifc_link_level_retrans_cntr_grp_date_bits link_level_retrans_cntr_grp_date; 11524 struct mlx5_ifc_pamp_reg_bits pamp_reg; 11525 struct mlx5_ifc_paos_reg_bits paos_reg; 11526 struct mlx5_ifc_pbmc_reg_bits pbmc_reg; 11527 struct mlx5_ifc_pcap_reg_bits pcap_reg; 11528 struct mlx5_ifc_peir_reg_bits peir_reg; 11529 struct mlx5_ifc_pelc_reg_bits pelc_reg; 11530 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 11531 struct mlx5_ifc_phbr_binding_reg_bits phbr_binding_reg; 11532 struct mlx5_ifc_phbr_for_port_tclass_reg_bits phbr_for_port_tclass_reg; 11533 struct mlx5_ifc_phbr_for_prio_reg_bits phbr_for_prio_reg; 11534 struct mlx5_ifc_phrr_reg_bits phrr_reg; 11535 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 11536 struct mlx5_ifc_pifr_reg_bits pifr_reg; 11537 struct mlx5_ifc_pipg_reg_bits pipg_reg; 11538 struct mlx5_ifc_plbf_reg_bits plbf_reg; 11539 struct mlx5_ifc_plib_reg_bits plib_reg; 11540 struct mlx5_ifc_pll_status_data_bits pll_status_data; 11541 struct mlx5_ifc_plpc_reg_bits plpc_reg; 11542 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 11543 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 11544 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 11545 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 11546 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 11547 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 11548 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 11549 struct mlx5_ifc_ppad_reg_bits ppad_reg; 11550 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 11551 struct mlx5_ifc_ppll_reg_bits ppll_reg; 11552 struct mlx5_ifc_pplm_reg_bits pplm_reg; 11553 struct mlx5_ifc_pplr_reg_bits pplr_reg; 11554 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 11555 struct mlx5_ifc_pspa_reg_bits pspa_reg; 11556 struct mlx5_ifc_ptas_reg_bits ptas_reg; 11557 struct mlx5_ifc_ptys_reg_bits ptys_reg; 11558 struct mlx5_ifc_pude_reg_bits pude_reg; 11559 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 11560 struct mlx5_ifc_slrg_reg_bits slrg_reg; 11561 struct mlx5_ifc_slrp_reg_bits slrp_reg; 11562 struct mlx5_ifc_sltp_reg_bits sltp_reg; 11563 u8 reserved_0[0x7880]; 11564 }; 11565 11566 union mlx5_ifc_debug_enhancements_document_bits { 11567 struct mlx5_ifc_health_buffer_bits health_buffer; 11568 u8 reserved_0[0x200]; 11569 }; 11570 11571 union mlx5_ifc_no_dram_nic_document_bits { 11572 struct mlx5_ifc_nodnic_config_reg_bits nodnic_config_reg; 11573 struct mlx5_ifc_nodnic_cq_arming_word_bits nodnic_cq_arming_word; 11574 struct mlx5_ifc_nodnic_event_word_bits nodnic_event_word; 11575 struct mlx5_ifc_nodnic_gid_filters_bits nodnic_gid_filters; 11576 struct mlx5_ifc_nodnic_mac_filters_bits nodnic_mac_filters; 11577 struct mlx5_ifc_nodnic_port_config_reg_bits nodnic_port_config_reg; 11578 struct mlx5_ifc_nodnic_ring_config_reg_bits nodnic_ring_config_reg; 11579 struct mlx5_ifc_nodnic_ring_doorbell_bits nodnic_ring_doorbell; 11580 u8 reserved_0[0x3160]; 11581 }; 11582 11583 union mlx5_ifc_uplink_pci_interface_document_bits { 11584 struct mlx5_ifc_initial_seg_bits initial_seg; 11585 struct mlx5_ifc_vendor_specific_cap_bits vendor_specific_cap; 11586 u8 reserved_0[0x20120]; 11587 }; 11588 11589 struct mlx5_ifc_qpdpm_dscp_reg_bits { 11590 u8 e[0x1]; 11591 u8 reserved_at_01[0x0b]; 11592 u8 prio[0x04]; 11593 }; 11594 11595 struct mlx5_ifc_qpdpm_reg_bits { 11596 u8 reserved_at_0[0x8]; 11597 u8 local_port[0x8]; 11598 u8 reserved_at_10[0x10]; 11599 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 11600 }; 11601 11602 struct mlx5_ifc_qpts_reg_bits { 11603 u8 reserved_at_0[0x8]; 11604 u8 local_port[0x8]; 11605 u8 reserved_at_10[0x2d]; 11606 u8 trust_state[0x3]; 11607 }; 11608 11609 struct mlx5_ifc_mfrl_reg_bits { 11610 u8 reserved_at_0[0x38]; 11611 u8 reset_level[0x8]; 11612 }; 11613 11614 enum { 11615 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTCAP = 0x9009, 11616 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTECR = 0x9109, 11617 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTMP = 0x900a, 11618 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTWE = 0x900b, 11619 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTBR = 0x900f, 11620 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTEWE = 0x910b, 11621 MLX5_MAX_TEMPERATURE = 16, 11622 }; 11623 11624 struct mlx5_ifc_mtbr_temp_record_bits { 11625 u8 max_temperature[0x10]; 11626 u8 temperature[0x10]; 11627 }; 11628 11629 struct mlx5_ifc_mtbr_reg_bits { 11630 u8 reserved_at_0[0x14]; 11631 u8 base_sensor_index[0xc]; 11632 11633 u8 reserved_at_20[0x18]; 11634 u8 num_rec[0x8]; 11635 11636 u8 reserved_at_40[0x40]; 11637 11638 struct mlx5_ifc_mtbr_temp_record_bits temperature_record[MLX5_MAX_TEMPERATURE]; 11639 }; 11640 11641 struct mlx5_ifc_mtbr_reg_ext_bits { 11642 u8 reserved_at_0[0x14]; 11643 u8 base_sensor_index[0xc]; 11644 11645 u8 reserved_at_20[0x18]; 11646 u8 num_rec[0x8]; 11647 11648 u8 reserved_at_40[0x40]; 11649 11650 struct mlx5_ifc_mtbr_temp_record_bits temperature_record[MLX5_MAX_TEMPERATURE]; 11651 }; 11652 11653 struct mlx5_ifc_mtcap_bits { 11654 u8 reserved_at_0[0x19]; 11655 u8 sensor_count[0x7]; 11656 11657 u8 reserved_at_20[0x19]; 11658 u8 internal_sensor_count[0x7]; 11659 11660 u8 sensor_map[0x40]; 11661 }; 11662 11663 struct mlx5_ifc_mtcap_ext_bits { 11664 u8 reserved_at_0[0x19]; 11665 u8 sensor_count[0x7]; 11666 11667 u8 reserved_at_20[0x20]; 11668 11669 u8 sensor_map[0x40]; 11670 }; 11671 11672 struct mlx5_ifc_mtecr_bits { 11673 u8 reserved_at_0[0x4]; 11674 u8 last_sensor[0xc]; 11675 u8 reserved_at_10[0x4]; 11676 u8 sensor_count[0xc]; 11677 11678 u8 reserved_at_20[0x19]; 11679 u8 internal_sensor_count[0x7]; 11680 11681 u8 sensor_map_0[0x20]; 11682 11683 u8 reserved_at_60[0x2a0]; 11684 }; 11685 11686 struct mlx5_ifc_mtecr_ext_bits { 11687 u8 reserved_at_0[0x4]; 11688 u8 last_sensor[0xc]; 11689 u8 reserved_at_10[0x4]; 11690 u8 sensor_count[0xc]; 11691 11692 u8 reserved_at_20[0x20]; 11693 11694 u8 sensor_map_0[0x20]; 11695 11696 u8 reserved_at_60[0x2a0]; 11697 }; 11698 11699 struct mlx5_ifc_mtewe_bits { 11700 u8 reserved_at_0[0x4]; 11701 u8 last_sensor[0xc]; 11702 u8 reserved_at_10[0x4]; 11703 u8 sensor_count[0xc]; 11704 11705 u8 sensor_warning_0[0x20]; 11706 11707 u8 reserved_at_40[0x2a0]; 11708 }; 11709 11710 struct mlx5_ifc_mtewe_ext_bits { 11711 u8 reserved_at_0[0x4]; 11712 u8 last_sensor[0xc]; 11713 u8 reserved_at_10[0x4]; 11714 u8 sensor_count[0xc]; 11715 11716 u8 sensor_warning_0[0x20]; 11717 11718 u8 reserved_at_40[0x2a0]; 11719 }; 11720 11721 struct mlx5_ifc_mtmp_bits { 11722 u8 reserved_at_0[0x14]; 11723 u8 sensor_index[0xc]; 11724 11725 u8 reserved_at_20[0x10]; 11726 u8 temperature[0x10]; 11727 11728 u8 mte[0x1]; 11729 u8 mtr[0x1]; 11730 u8 reserved_at_42[0xe]; 11731 u8 max_temperature[0x10]; 11732 11733 u8 tee[0x2]; 11734 u8 reserved_at_62[0xe]; 11735 u8 temperature_threshold_hi[0x10]; 11736 11737 u8 reserved_at_80[0x10]; 11738 u8 temperature_threshold_lo[0x10]; 11739 11740 u8 reserved_at_a0[0x20]; 11741 11742 u8 sensor_name_hi[0x20]; 11743 11744 u8 sensor_name_lo[0x20]; 11745 }; 11746 11747 struct mlx5_ifc_mtmp_ext_bits { 11748 u8 reserved_at_0[0x14]; 11749 u8 sensor_index[0xc]; 11750 11751 u8 reserved_at_20[0x10]; 11752 u8 temperature[0x10]; 11753 11754 u8 mte[0x1]; 11755 u8 mtr[0x1]; 11756 u8 reserved_at_42[0xe]; 11757 u8 max_temperature[0x10]; 11758 11759 u8 tee[0x2]; 11760 u8 reserved_at_62[0xe]; 11761 u8 temperature_threshold_hi[0x10]; 11762 11763 u8 reserved_at_80[0x10]; 11764 u8 temperature_threshold_lo[0x10]; 11765 11766 u8 reserved_at_a0[0x20]; 11767 11768 u8 sensor_name_hi[0x20]; 11769 11770 u8 sensor_name_lo[0x20]; 11771 }; 11772 11773 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 11774 u8 opcode[0x10]; 11775 u8 uid[0x10]; 11776 11777 u8 vhca_tunnel_id[0x10]; 11778 u8 obj_type[0x10]; 11779 11780 u8 obj_id[0x20]; 11781 11782 u8 reserved_at_60[0x20]; 11783 }; 11784 11785 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 11786 u8 status[0x8]; 11787 u8 reserved_at_8[0x18]; 11788 11789 u8 syndrome[0x20]; 11790 11791 u8 obj_id[0x20]; 11792 11793 u8 reserved_at_60[0x20]; 11794 }; 11795 11796 struct mlx5_ifc_umem_bits { 11797 u8 reserved_at_0[0x80]; 11798 11799 u8 reserved_at_80[0x1b]; 11800 u8 log_page_size[0x5]; 11801 11802 u8 page_offset[0x20]; 11803 11804 u8 num_of_mtt[0x40]; 11805 11806 struct mlx5_ifc_mtt_bits mtt[0]; 11807 }; 11808 11809 struct mlx5_ifc_uctx_bits { 11810 u8 cap[0x20]; 11811 11812 u8 reserved_at_20[0x160]; 11813 }; 11814 11815 struct mlx5_ifc_create_umem_in_bits { 11816 u8 opcode[0x10]; 11817 u8 uid[0x10]; 11818 11819 u8 reserved_at_20[0x10]; 11820 u8 op_mod[0x10]; 11821 11822 u8 reserved_at_40[0x40]; 11823 11824 struct mlx5_ifc_umem_bits umem; 11825 }; 11826 11827 struct mlx5_ifc_create_uctx_in_bits { 11828 u8 opcode[0x10]; 11829 u8 reserved_at_10[0x10]; 11830 11831 u8 reserved_at_20[0x10]; 11832 u8 op_mod[0x10]; 11833 11834 u8 reserved_at_40[0x40]; 11835 11836 struct mlx5_ifc_uctx_bits uctx; 11837 }; 11838 11839 struct mlx5_ifc_destroy_uctx_in_bits { 11840 u8 opcode[0x10]; 11841 u8 reserved_at_10[0x10]; 11842 11843 u8 reserved_at_20[0x10]; 11844 u8 op_mod[0x10]; 11845 11846 u8 reserved_at_40[0x10]; 11847 u8 uid[0x10]; 11848 11849 u8 reserved_at_60[0x20]; 11850 }; 11851 11852 struct mlx5_ifc_mtrc_string_db_param_bits { 11853 u8 string_db_base_address[0x20]; 11854 11855 u8 reserved_at_20[0x8]; 11856 u8 string_db_size[0x18]; 11857 }; 11858 11859 struct mlx5_ifc_mtrc_cap_bits { 11860 u8 trace_owner[0x1]; 11861 u8 trace_to_memory[0x1]; 11862 u8 reserved_at_2[0x4]; 11863 u8 trc_ver[0x2]; 11864 u8 reserved_at_8[0x14]; 11865 u8 num_string_db[0x4]; 11866 11867 u8 first_string_trace[0x8]; 11868 u8 num_string_trace[0x8]; 11869 u8 reserved_at_30[0x28]; 11870 11871 u8 log_max_trace_buffer_size[0x8]; 11872 11873 u8 reserved_at_60[0x20]; 11874 11875 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 11876 11877 u8 reserved_at_280[0x180]; 11878 }; 11879 11880 struct mlx5_ifc_mtrc_conf_bits { 11881 u8 reserved_at_0[0x1c]; 11882 u8 trace_mode[0x4]; 11883 u8 reserved_at_20[0x18]; 11884 u8 log_trace_buffer_size[0x8]; 11885 u8 trace_mkey[0x20]; 11886 u8 reserved_at_60[0x3a0]; 11887 }; 11888 11889 struct mlx5_ifc_mtrc_stdb_bits { 11890 u8 string_db_index[0x4]; 11891 u8 reserved_at_4[0x4]; 11892 u8 read_size[0x18]; 11893 u8 start_offset[0x20]; 11894 u8 string_db_data[0]; 11895 }; 11896 11897 struct mlx5_ifc_mtrc_ctrl_bits { 11898 u8 trace_status[0x2]; 11899 u8 reserved_at_2[0x2]; 11900 u8 arm_event[0x1]; 11901 u8 reserved_at_5[0xb]; 11902 u8 modify_field_select[0x10]; 11903 u8 reserved_at_20[0x2b]; 11904 u8 current_timestamp52_32[0x15]; 11905 u8 current_timestamp31_0[0x20]; 11906 u8 reserved_at_80[0x180]; 11907 }; 11908 11909 struct mlx5_ifc_affiliated_event_header_bits { 11910 u8 reserved_at_0[0x10]; 11911 u8 obj_type[0x10]; 11912 11913 u8 obj_id[0x20]; 11914 }; 11915 11916 #define MLX5_FC_BULK_SIZE_FACTOR 128 11917 11918 enum mlx5_fc_bulk_alloc_bitmask { 11919 MLX5_FC_BULK_128 = (1 << 0), 11920 MLX5_FC_BULK_256 = (1 << 1), 11921 MLX5_FC_BULK_512 = (1 << 2), 11922 MLX5_FC_BULK_1024 = (1 << 3), 11923 MLX5_FC_BULK_2048 = (1 << 4), 11924 MLX5_FC_BULK_4096 = (1 << 5), 11925 MLX5_FC_BULK_8192 = (1 << 6), 11926 MLX5_FC_BULK_16384 = (1 << 7), 11927 }; 11928 11929 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 11930 11931 struct mlx5_ifc_ipsec_cap_bits { 11932 u8 ipsec_full_offload[0x1]; 11933 u8 ipsec_crypto_offload[0x1]; 11934 u8 ipsec_esn[0x1]; 11935 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 11936 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 11937 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 11938 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 11939 u8 reserved_at_7[0x4]; 11940 u8 log_max_ipsec_offload[0x5]; 11941 u8 reserved_at_10[0x10]; 11942 11943 u8 min_log_ipsec_full_replay_window[0x8]; 11944 u8 max_log_ipsec_full_replay_window[0x8]; 11945 u8 reserved_at_30[0x7d0]; 11946 }; 11947 11948 enum { 11949 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 11950 }; 11951 11952 enum { 11953 MLX5_IPSEC_ASO_REG_C_0_1 = 0x0, 11954 MLX5_IPSEC_ASO_REG_C_2_3 = 0x1, 11955 MLX5_IPSEC_ASO_REG_C_4_5 = 0x2, 11956 MLX5_IPSEC_ASO_REG_C_6_7 = 0x3, 11957 }; 11958 11959 enum { 11960 MLX5_IPSEC_ASO_MODE = 0x0, 11961 MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1, 11962 MLX5_IPSEC_ASO_INC_SN = 0x2, 11963 }; 11964 11965 enum { 11966 MLX5_IPSEC_ASO_REPLAY_WIN_32BIT = 0x0, 11967 MLX5_IPSEC_ASO_REPLAY_WIN_64BIT = 0x1, 11968 MLX5_IPSEC_ASO_REPLAY_WIN_128BIT = 0x2, 11969 MLX5_IPSEC_ASO_REPLAY_WIN_256BIT = 0x3, 11970 }; 11971 11972 struct mlx5_ifc_ipsec_aso_bits { 11973 u8 valid[0x1]; 11974 u8 reserved_at_201[0x1]; 11975 u8 mode[0x2]; 11976 u8 window_sz[0x2]; 11977 u8 soft_lft_arm[0x1]; 11978 u8 hard_lft_arm[0x1]; 11979 u8 remove_flow_enable[0x1]; 11980 u8 esn_event_arm[0x1]; 11981 u8 reserved_at_20a[0x16]; 11982 11983 u8 remove_flow_pkt_cnt[0x20]; 11984 11985 u8 remove_flow_soft_lft[0x20]; 11986 11987 u8 reserved_at_260[0x80]; 11988 11989 u8 mode_parameter[0x20]; 11990 11991 u8 replay_protection_window[0x100]; 11992 }; 11993 11994 struct mlx5_ifc_ipsec_obj_bits { 11995 u8 modify_field_select[0x40]; 11996 u8 full_offload[0x1]; 11997 u8 reserved_at_41[0x1]; 11998 u8 esn_en[0x1]; 11999 u8 esn_overlap[0x1]; 12000 u8 reserved_at_44[0x2]; 12001 u8 icv_length[0x2]; 12002 u8 reserved_at_48[0x4]; 12003 u8 aso_return_reg[0x4]; 12004 u8 reserved_at_50[0x10]; 12005 12006 u8 esn_msb[0x20]; 12007 12008 u8 reserved_at_80[0x8]; 12009 u8 dekn[0x18]; 12010 12011 u8 salt[0x20]; 12012 12013 u8 implicit_iv[0x40]; 12014 12015 u8 reserved_at_100[0x8]; 12016 u8 ipsec_aso_access_pd[0x18]; 12017 u8 reserved_at_120[0xe0]; 12018 12019 struct mlx5_ifc_ipsec_aso_bits ipsec_aso; 12020 }; 12021 12022 struct mlx5_ifc_create_ipsec_obj_in_bits { 12023 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12024 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12025 }; 12026 12027 enum { 12028 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = 1 << 0, 12029 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = 1 << 1, 12030 }; 12031 12032 struct mlx5_ifc_query_ipsec_obj_out_bits { 12033 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 12034 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12035 }; 12036 12037 struct mlx5_ifc_modify_ipsec_obj_in_bits { 12038 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12039 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 12040 }; 12041 12042 enum { 12043 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1, 12044 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2, 12045 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4, 12046 }; 12047 #endif /* MLX5_IFC_H */ 12048