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Searched refs:latencies (Results 1 – 25 of 29) sorted by relevance

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/freebsd/sys/cam/
H A Dcam_iosched.c282 uint64_t latencies[LAT_BUCKETS]; member
977 uint64_t *latencies; in cam_iosched_sysctl_latencies() local
979 latencies = arg1; in cam_iosched_sysctl_latencies()
983 sbuf_printf(&sb, "%jd,", (intmax_t)latencies[i]); in cam_iosched_sysctl_latencies()
984 sbuf_printf(&sb, "%jd", (intmax_t)latencies[LAT_BUCKETS - 1]); in cam_iosched_sysctl_latencies()
1088 &ios->latencies, 0, in cam_iosched_iop_stats_sysctl_init()
1911 static sbintime_t latencies[LAT_BUCKETS - 1] = { variable
1980 if (sim_latency < latencies[i]) { in cam_iosched_update()
1981 iop->latencies[i]++; in cam_iosched_update()
1986 iop->latencies[i]++; /* Put all > 8192ms values into the last bucket. */ in cam_iosched_update()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DP9InstrResources.td816 // operations cannot be done at the same time and so their latencies are added.
828 // operations cannot be done at the same time and so their latencies are added.
838 // operations cannot be done at the same time and so their latencies are added.
849 // their latencies are added.
861 // operations cannot be done at the same time and so their latencies are added.
881 // Since the Load and the PM cannot be done at the same time the latencies are
1026 // latencies are not added together. Otherwise this is like having two
1038 // latencies are not added together. Otherwise this is like having two
1064 // latencies are not added together. Otherwise this is like having two
1075 // latencies are not added together. Otherwise this is like having two
[all …]
H A DPPCScheduleP9.td384 // 2 or 5 cycle latencies for the branch unit.
402 // so the latencies for their resources must be added.
/freebsd/sys/contrib/device-tree/Bindings/powerpc/opal/
H A Dpower-mgt.txt60 - ibm,cpu-idle-state-latencies-ns:
62 exit-latencies (in ns) for the idle states in
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleM4.td35 // Some definitions of latencies we apply to different instructions
H A DARMScheduleM85.td13 // but is described as if it were in EX2 to avoid having unnaturally long latencies
697 // DAG overrides to correctly set latencies.
698 // NOTE2: MVE integer MAC->MAC accumulate latencies are set as if the
H A DARMScheduleM55.td47 // For this schedule, we currently model latencies and pipelines well for each
73 // one). These use normal resources and latencies, but set SingleIssue = 0.
H A DARMSchedule.td38 // shorter latencies to certain registers as needed in the example above.
H A DARMScheduleA9.td1975 // NEON has an odd mix of latencies. Simply name the write types by latency.
2310 // latencies here. WAW latencies are sometimes longer.
2369 // has a def operand so the WriteL latencies are unused.
H A DARMFeatures.td337 // extra cycle. Take that into account when computing operand latencies.
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedA53.td59 // shift-only instruction. These latencies will be incorrect when the
98 // accounted for in the WriteST* latencies below
H A DAArch64SchedA55.td63 // These latencies are modeled without taking into account forwarding paths
64 // (the software optimisation guide lists latencies taking into account
H A DAArch64SchedThunderX.td47 // latencies.
H A DAArch64SchedA510.td22 // Most loads have a latency of 2, but some have higher latencies.
65 // These latencies are modeled without taking into account forwarding paths
66 // (the software optimisation guide lists latencies taking into account
H A DAArch64SchedA320.td54 // These latencies are modeled without taking into account forwarding paths
55 // (the software optimisation guide lists latencies taking into account
H A DAArch64SchedAmpere1.td583 // Map the target-defined scheduler read/write resources and latencies for Ampere-1.
H A DAArch64SchedAmpere1B.td539 // Map the target-defined scheduler read/write resources and latencies for Ampere-1.
H A DAArch64SchedOryon.td512 // On VXU doc, p37 -- latencies and throughput
/freebsd/contrib/libpcap/doc/
H A DREADME.dag47 filtering) for efficiency. This can introduce high latencies on quiet
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86Schedule.td732 // latencies. Since these latencies are not used for pipeline hazards,
H A DX86ScheduleBtVer2.td425 // instruction latency is set to the MAX of all the write latencies. That's why
/freebsd/crypto/openssl/crypto/
H A Dsparccpuid.S263 ! (*) result has lesser to do with VIS instruction latencies, rdtick
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSchedSiFiveP800.td721 // TODO: The latencies and RThroughput for VISlideUpX and VISlideDownX are likely
H A DRISCVSchedSiFiveP400.td78 // SEW = 64 has lower latencies and RThroughputs than other SEWs.
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTarget.td712 // This instruction is not expected to be queried for scheduling latencies

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